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gerrit-public.fairphone.software / toolchain / llvm-project / ef96a8ecd6308cc31e43515c2ce0bae6ffbdbbc6 / . / llvm / test / CodeGen / Mips / llvm-ir / sdiv.ll
blob: 54b7f70b1dac81666f19956d36059d59a4cc6d8e [file] [log] [blame]
Vasileios Kalintiris2ed214f2015-01-26 12:04:40 +0000[diff] [blame]1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32
5; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
6; RUN: -check-prefix=NOT-R6 -check-prefix=R2 -check-prefix=GP32
7; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
8; RUN: -check-prefix=R6 -check-prefix=GP32
9; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
10; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6
11; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
12; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6
13; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
14; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6
15; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
16; RUN: -check-prefix=NOT-R6 -check-prefix=R2 -check-prefix=GP64-NOT-R6
17; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
18; RUN: -check-prefix=R6 -check-prefix=64R6
19
20define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
21entry:
22; ALL-LABEL: sdiv_i1:
23
24 ; NOT-R6: div $zero, $4, $5
25 ; NOT-R6: teq $5, $zero, 7
26 ; NOT-R6: mflo $[[T0:[0-9]+]]
27 ; FIXME: The sll/sra instructions are redundant since div is signed.
28 ; NOT-R6: sll $[[T1:[0-9]+]], $[[T0]], 31
29 ; NOT-R6: sra $2, $[[T1]], 31
30
31 ; R6: div $[[T0:[0-9]+]], $4, $5
32 ; R6: teq $5, $zero, 7
33 ; FIXME: The sll/sra instructions are redundant since div is signed.
34 ; R6: sll $[[T1:[0-9]+]], $[[T0]], 31
35 ; R6: sra $2, $[[T1]], 31
36
37 %r = sdiv i1 %a, %b
38 ret i1 %r
39}
40
41define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) {
42entry:
43; ALL-LABEL: sdiv_i8:
44
45 ; NOT-R2-R6: div $zero, $4, $5
46 ; NOT-R2-R6: teq $5, $zero, 7
47 ; NOT-R2-R6: mflo $[[T0:[0-9]+]]
48 ; FIXME: The sll/sra instructions are redundant since div is signed.
49 ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24
50 ; NOT-R2-R6: sra $2, $[[T1]], 24
51
52 ; R2: div $zero, $4, $5
53 ; R2: teq $5, $zero, 7
54 ; R2: mflo $[[T0:[0-9]+]]
55 ; FIXME: This instruction is redundant.
56 ; R2: seb $2, $[[T0]]
57
58 ; R6: div $[[T0:[0-9]+]], $4, $5
59 ; R6: teq $5, $zero, 7
60 ; FIXME: This instruction is redundant.
61 ; R6: seb $2, $[[T0]]
62
63 %r = sdiv i8 %a, %b
64 ret i8 %r
65}
66
67define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) {
68entry:
69; ALL-LABEL: sdiv_i16:
70
71 ; NOT-R2-R6: div $zero, $4, $5
72 ; NOT-R2-R6: teq $5, $zero, 7
73 ; NOT-R2-R6: mflo $[[T0:[0-9]+]]
74 ; FIXME: The sll/sra instructions are redundant since div is signed.
75 ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16
76 ; NOT-R2-R6: sra $2, $[[T1]], 16
77
78 ; R2: div $zero, $4, $5
79 ; R2: teq $5, $zero, 7
80 ; R2: mflo $[[T0:[0-9]+]]
81 ; FIXME: This is instruction is redundant since div is signed.
82 ; R2: seh $2, $[[T0]]
83
84 ; R6: div $[[T0:[0-9]+]], $4, $5
85 ; R6: teq $5, $zero, 7
86 ; FIXME: This is instruction is redundant since div is signed.
87 ; R6: seh $2, $[[T0]]
88
89 %r = sdiv i16 %a, %b
90 ret i16 %r
91}
92
93define signext i32 @sdiv_i32(i32 signext %a, i32 signext %b) {
94entry:
95; ALL-LABEL: sdiv_i32:
96
97 ; NOT-R6: div $zero, $4, $5
98 ; NOT-R6: teq $5, $zero, 7
99 ; NOT-R6: mflo $2
100
101 ; R6: div $2, $4, $5
102 ; R6: teq $5, $zero, 7
103
104 %r = sdiv i32 %a, %b
105 ret i32 %r
106}
107
108define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) {
109entry:
110; ALL-LABEL: sdiv_i64:
111
112 ; GP32: lw $25, %call16(__divdi3)($gp)
113
114 ; GP64-NOT-R6: ddiv $zero, $4, $5
115 ; GP64-NOT-R6: teq $5, $zero, 7
116 ; GP64-NOT-R6: mflo $2
117
118 ; 64R6: ddiv $2, $4, $5
119 ; 64R6: teq $5, $zero, 7
120
121 %r = sdiv i64 %a, %b
122 ret i64 %r
123}
Vasileios Kalintirisef96a8e2015-01-26 12:33:22 +0000[diff] [blame^]124
125define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) {
126entry:
127 ; ALL-LABEL: sdiv_i128:
128
129 ; GP32: lw $25, %call16(__divti3)($gp)
130
131 ; GP64-NOT-R6: ld $25, %call16(__divti3)($gp)
132 ; 64R6: ld $25, %call16(__divti3)($gp)
133
134 %r = sdiv i128 %a, %b
135 ret i128 %r
136}