| Richard Sandiford | 885140c | 2013-07-16 11:55:57 +0000 | [diff] [blame] | 1 | ; Test sequences that can use RISBG with a normal first operand. |
| 2 | ; |
| 3 | ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s |
| 4 | |
| 5 | ; Test a case with two ANDs. |
| 6 | define i32 @f1(i32 %a, i32 %b) { |
| 7 | ; CHECK-LABEL: f1: |
| 8 | ; CHECK: risbg %r2, %r3, 60, 62, 0 |
| 9 | ; CHECK: br %r14 |
| 10 | %anda = and i32 %a, -15 |
| 11 | %andb = and i32 %b, 14 |
| 12 | %or = or i32 %anda, %andb |
| 13 | ret i32 %or |
| 14 | } |
| 15 | |
| 16 | ; ...and again with i64. |
| 17 | define i64 @f2(i64 %a, i64 %b) { |
| 18 | ; CHECK-LABEL: f2: |
| 19 | ; CHECK: risbg %r2, %r3, 60, 62, 0 |
| 20 | ; CHECK: br %r14 |
| 21 | %anda = and i64 %a, -15 |
| 22 | %andb = and i64 %b, 14 |
| 23 | %or = or i64 %anda, %andb |
| 24 | ret i64 %or |
| 25 | } |
| 26 | |
| 27 | ; Test a case with two ANDs and a shift. |
| 28 | define i32 @f3(i32 %a, i32 %b) { |
| 29 | ; CHECK-LABEL: f3: |
| 30 | ; CHECK: risbg %r2, %r3, 60, 63, 56 |
| 31 | ; CHECK: br %r14 |
| 32 | %anda = and i32 %a, -16 |
| 33 | %shr = lshr i32 %b, 8 |
| 34 | %andb = and i32 %shr, 15 |
| 35 | %or = or i32 %anda, %andb |
| 36 | ret i32 %or |
| 37 | } |
| 38 | |
| 39 | ; ...and again with i64. |
| 40 | define i64 @f4(i64 %a, i64 %b) { |
| 41 | ; CHECK-LABEL: f4: |
| 42 | ; CHECK: risbg %r2, %r3, 60, 63, 56 |
| 43 | ; CHECK: br %r14 |
| 44 | %anda = and i64 %a, -16 |
| 45 | %shr = lshr i64 %b, 8 |
| 46 | %andb = and i64 %shr, 15 |
| 47 | %or = or i64 %anda, %andb |
| 48 | ret i64 %or |
| 49 | } |
| 50 | |
| 51 | ; Test a case with a single AND and a left shift. |
| 52 | define i32 @f5(i32 %a, i32 %b) { |
| 53 | ; CHECK-LABEL: f5: |
| 54 | ; CHECK: risbg %r2, %r3, 32, 53, 10 |
| 55 | ; CHECK: br %r14 |
| 56 | %anda = and i32 %a, 1023 |
| 57 | %shlb = shl i32 %b, 10 |
| 58 | %or = or i32 %anda, %shlb |
| 59 | ret i32 %or |
| 60 | } |
| 61 | |
| 62 | ; ...and again with i64. |
| 63 | define i64 @f6(i64 %a, i64 %b) { |
| 64 | ; CHECK-LABEL: f6: |
| 65 | ; CHECK: risbg %r2, %r3, 0, 53, 10 |
| 66 | ; CHECK: br %r14 |
| 67 | %anda = and i64 %a, 1023 |
| 68 | %shlb = shl i64 %b, 10 |
| 69 | %or = or i64 %anda, %shlb |
| 70 | ret i64 %or |
| 71 | } |
| 72 | |
| 73 | ; Test a case with a single AND and a right shift. |
| 74 | define i32 @f7(i32 %a, i32 %b) { |
| 75 | ; CHECK-LABEL: f7: |
| 76 | ; CHECK: risbg %r2, %r3, 40, 63, 56 |
| 77 | ; CHECK: br %r14 |
| 78 | %anda = and i32 %a, -16777216 |
| 79 | %shrb = lshr i32 %b, 8 |
| 80 | %or = or i32 %anda, %shrb |
| 81 | ret i32 %or |
| 82 | } |
| 83 | |
| 84 | ; ...and again with i64. |
| 85 | define i64 @f8(i64 %a, i64 %b) { |
| 86 | ; CHECK-LABEL: f8: |
| 87 | ; CHECK: risbg %r2, %r3, 8, 63, 56 |
| 88 | ; CHECK: br %r14 |
| 89 | %anda = and i64 %a, -72057594037927936 |
| 90 | %shrb = lshr i64 %b, 8 |
| 91 | %or = or i64 %anda, %shrb |
| 92 | ret i64 %or |
| 93 | } |