Jia Liu | 9d2d2ad | 2012-02-24 02:05:28 +0000 | [diff] [blame] | 1 | //===-- MipsBaseInfo.h - Top level definitions for MIPS MC ------*- C++ -*-===// |
Akira Hatanaka | d9ea7c8 | 2011-10-14 03:04:24 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains small standalone helper functions and enum definitions for |
| 11 | // the Mips target useful for the compiler back-end and the MC libraries. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
Benjamin Kramer | a7c40ef | 2014-08-13 16:26:38 +0000 | [diff] [blame] | 14 | #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSBASEINFO_H |
| 15 | #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSBASEINFO_H |
Akira Hatanaka | d9ea7c8 | 2011-10-14 03:04:24 +0000 | [diff] [blame] | 16 | |
Akira Hatanaka | a06bc1c | 2012-03-27 02:04:18 +0000 | [diff] [blame] | 17 | #include "MipsFixupKinds.h" |
Akira Hatanaka | d9ea7c8 | 2011-10-14 03:04:24 +0000 | [diff] [blame] | 18 | #include "MipsMCTargetDesc.h" |
Akira Hatanaka | a06bc1c | 2012-03-27 02:04:18 +0000 | [diff] [blame] | 19 | #include "llvm/MC/MCExpr.h" |
Akira Hatanaka | d9ea7c8 | 2011-10-14 03:04:24 +0000 | [diff] [blame] | 20 | #include "llvm/Support/DataTypes.h" |
| 21 | #include "llvm/Support/ErrorHandling.h" |
| 22 | |
| 23 | namespace llvm { |
Bruno Cardoso Lopes | c85e3ff | 2011-11-11 22:58:42 +0000 | [diff] [blame] | 24 | |
| 25 | /// MipsII - This namespace holds all of the target specific flags that |
| 26 | /// instruction info tracks. |
| 27 | /// |
| 28 | namespace MipsII { |
| 29 | /// Target Operand Flag enum. |
| 30 | enum TOF { |
| 31 | //===------------------------------------------------------------------===// |
| 32 | // Mips Specific MachineOperand flags. |
| 33 | |
| 34 | MO_NO_FLAG, |
| 35 | |
Daniel Sanders | fe98b2f | 2016-05-03 13:35:44 +0000 | [diff] [blame] | 36 | /// MO_GOT - Represents the offset into the global offset table at which |
Bruno Cardoso Lopes | c85e3ff | 2011-11-11 22:58:42 +0000 | [diff] [blame] | 37 | /// the address the relocation entry symbol resides during execution. |
| 38 | MO_GOT, |
| 39 | |
| 40 | /// MO_GOT_CALL - Represents the offset into the global offset table at |
| 41 | /// which the address of a call site relocation entry symbol resides |
| 42 | /// during execution. This is different from the above since this flag |
| 43 | /// can only be present in call instructions. |
| 44 | MO_GOT_CALL, |
| 45 | |
| 46 | /// MO_GPREL - Represents the offset from the current gp value to be used |
| 47 | /// for the relocatable object file being produced. |
| 48 | MO_GPREL, |
| 49 | |
| 50 | /// MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol |
| 51 | /// address. |
| 52 | MO_ABS_HI, |
| 53 | MO_ABS_LO, |
| 54 | |
| 55 | /// MO_TLSGD - Represents the offset into the global offset table at which |
| 56 | // the module ID and TSL block offset reside during execution (General |
| 57 | // Dynamic TLS). |
| 58 | MO_TLSGD, |
| 59 | |
Akira Hatanaka | bff84e1 | 2011-12-14 18:26:41 +0000 | [diff] [blame] | 60 | /// MO_TLSLDM - Represents the offset into the global offset table at which |
| 61 | // the module ID and TSL block offset reside during execution (Local |
| 62 | // Dynamic TLS). |
| 63 | MO_TLSLDM, |
| 64 | MO_DTPREL_HI, |
| 65 | MO_DTPREL_LO, |
| 66 | |
Bruno Cardoso Lopes | c85e3ff | 2011-11-11 22:58:42 +0000 | [diff] [blame] | 67 | /// MO_GOTTPREL - Represents the offset from the thread pointer (Initial |
| 68 | // Exec TLS). |
| 69 | MO_GOTTPREL, |
| 70 | |
| 71 | /// MO_TPREL_HI/LO - Represents the hi and low part of the offset from |
| 72 | // the thread pointer (Local Exec TLS). |
| 73 | MO_TPREL_HI, |
| 74 | MO_TPREL_LO, |
| 75 | |
| 76 | // N32/64 Flags. |
| 77 | MO_GPOFF_HI, |
| 78 | MO_GPOFF_LO, |
| 79 | MO_GOT_DISP, |
| 80 | MO_GOT_PAGE, |
Akira Hatanaka | 6035fe7 | 2012-07-21 03:09:04 +0000 | [diff] [blame] | 81 | MO_GOT_OFST, |
| 82 | |
Akira Hatanaka | adec58c | 2012-07-23 19:19:20 +0000 | [diff] [blame] | 83 | /// MO_HIGHER/HIGHEST - Represents the highest or higher half word of a |
| 84 | /// 64-bit symbol address. |
Akira Hatanaka | 6035fe7 | 2012-07-21 03:09:04 +0000 | [diff] [blame] | 85 | MO_HIGHER, |
Akira Hatanaka | 03fb5b9 | 2012-11-21 19:59:51 +0000 | [diff] [blame] | 86 | MO_HIGHEST, |
| 87 | |
| 88 | /// MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs. |
| 89 | MO_GOT_HI16, |
| 90 | MO_GOT_LO16, |
| 91 | MO_CALL_HI16, |
| 92 | MO_CALL_LO16 |
Bruno Cardoso Lopes | c85e3ff | 2011-11-11 22:58:42 +0000 | [diff] [blame] | 93 | }; |
| 94 | |
| 95 | enum { |
| 96 | //===------------------------------------------------------------------===// |
| 97 | // Instruction encodings. These are the standard/most common forms for |
| 98 | // Mips instructions. |
| 99 | // |
| 100 | |
| 101 | // Pseudo - This represents an instruction that is a pseudo instruction |
| 102 | // or one that has not been implemented yet. It is illegal to code generate |
| 103 | // it, but tolerated for intermediate implementation stages. |
| 104 | Pseudo = 0, |
| 105 | |
| 106 | /// FrmR - This form is for instructions of the format R. |
| 107 | FrmR = 1, |
| 108 | /// FrmI - This form is for instructions of the format I. |
| 109 | FrmI = 2, |
| 110 | /// FrmJ - This form is for instructions of the format J. |
| 111 | FrmJ = 3, |
| 112 | /// FrmFR - This form is for instructions of the format FR. |
| 113 | FrmFR = 4, |
| 114 | /// FrmFI - This form is for instructions of the format FI. |
| 115 | FrmFI = 5, |
| 116 | /// FrmOther - This form is for instructions that have no specific format. |
| 117 | FrmOther = 6, |
| 118 | |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 119 | FormMask = 15, |
| 120 | /// IsCTI - Instruction is a Control Transfer Instruction. |
| 121 | IsCTI = 1 << 4, |
| 122 | /// HasForbiddenSlot - Instruction has a forbidden slot. |
Hrvoje Varga | dbe4d96 | 2016-09-08 07:41:43 +0000 | [diff] [blame] | 123 | HasForbiddenSlot = 1 << 5, |
| 124 | /// IsPCRelativeLoad - A Load instruction with implicit source register |
| 125 | /// ($pc) with explicit offset and destination register |
Simon Dardis | 730fdb7 | 2017-01-16 13:55:58 +0000 | [diff] [blame] | 126 | IsPCRelativeLoad = 1 << 6, |
| 127 | /// HasFCCRegOperand - Instruction uses an $fcc<x> register. |
| 128 | HasFCCRegOperand = 1 << 7 |
Daniel Sanders | e8efff3 | 2016-03-14 16:24:05 +0000 | [diff] [blame] | 129 | |
Bruno Cardoso Lopes | c85e3ff | 2011-11-11 22:58:42 +0000 | [diff] [blame] | 130 | }; |
Alexander Kornienko | f00654e | 2015-06-23 09:49:53 +0000 | [diff] [blame] | 131 | } |
| 132 | } |
Akira Hatanaka | d9ea7c8 | 2011-10-14 03:04:24 +0000 | [diff] [blame] | 133 | |
| 134 | #endif |