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gerrit-public.fairphone.software / toolchain / llvm-project / f143af3fe951e086b7c158213e6e113c73835723 / . / llvm / test / CodeGen / R600 / r600-encoding.ll
blob: b760c882f4e30d04d3bf3dd8832923e4d755bf56 [file] [log] [blame]
Tom Stellardecc2ad12013-05-17 15:23:21 +0000[diff] [blame]1; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
2; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600-CHECK %s
3
4; The earliest R600 GPUs have a slightly different encoding than the rest of
5; the VLIW4/5 GPUs.
6
7; EG-CHECK: @test
Vincent Lejeune3d5118c2013-05-17 16:50:56 +0000[diff] [blame]8; EG-CHECK: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}]
Tom Stellardecc2ad12013-05-17 15:23:21 +0000[diff] [blame]9
10; R600-CHECK: @test
Vincent Lejeune3d5118c2013-05-17 16:50:56 +0000[diff] [blame]11; R600-CHECK: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}]
Tom Stellardecc2ad12013-05-17 15:23:21 +0000[diff] [blame]12
Vincent Lejeunef143af32013-11-11 22:10:24 +0000[diff] [blame^]13define void @test(<4 x float> inreg %reg0) #0 {
Tom Stellardecc2ad12013-05-17 15:23:21 +0000[diff] [blame]14entry:
Vincent Lejeunef143af32013-11-11 22:10:24 +0000[diff] [blame^]15 %r0 = extractelement <4 x float> %reg0, i32 0
16 %r1 = extractelement <4 x float> %reg0, i32 1
17 %r2 = fmul float %r0, %r1
18 %vec = insertelement <4 x float> undef, float %r2, i32 0
19 call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
Tom Stellardecc2ad12013-05-17 15:23:21 +0000[diff] [blame]20 ret void
21}
22
Vincent Lejeunef143af32013-11-11 22:10:24 +0000[diff] [blame^]23declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
Tom Stellardecc2ad12013-05-17 15:23:21 +0000[diff] [blame]24
Vincent Lejeunef143af32013-11-11 22:10:24 +0000[diff] [blame^]25attributes #0 = { "ShaderType"="0" }