| Erich Keane | ebba592 | 2017-07-21 22:37:03 +0000 | [diff] [blame] | 1 | //===--- AArch64.cpp - Implement AArch64 target feature support -----------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file implements AArch64 TargetInfo objects. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #include "AArch64.h" |
| 15 | #include "clang/Basic/TargetBuiltins.h" |
| 16 | #include "clang/Basic/TargetInfo.h" |
| 17 | #include "llvm/ADT/ArrayRef.h" |
| 18 | |
| 19 | using namespace clang; |
| 20 | using namespace clang::targets; |
| 21 | |
| 22 | const char *const AArch64TargetInfo::GCCRegNames[] = { |
| 23 | // 32-bit Integer registers |
| 24 | "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", "w11", |
| 25 | "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", "w22", |
| 26 | "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", |
| 27 | |
| 28 | // 64-bit Integer registers |
| 29 | "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", |
| 30 | "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22", |
| 31 | "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", |
| 32 | |
| 33 | // 32-bit floating point regsisters |
| 34 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", |
| 35 | "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22", |
| 36 | "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", |
| 37 | |
| 38 | // 64-bit floating point regsisters |
| 39 | "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11", |
| 40 | "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22", |
| 41 | "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", |
| 42 | |
| 43 | // Vector registers |
| 44 | "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11", |
| 45 | "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22", |
| 46 | "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" |
| 47 | }; |
| 48 | |
| 49 | ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { |
| 50 | return llvm::makeArrayRef(GCCRegNames); |
| 51 | } |
| 52 | |
| 53 | const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { |
| 54 | {{"w31"}, "wsp"}, {{"x29"}, "fp"}, {{"x30"}, "lr"}, {{"x31"}, "sp"}, |
| 55 | // The S/D/Q and W/X registers overlap, but aren't really aliases; we |
| 56 | // don't want to substitute one of these for a different-sized one. |
| 57 | }; |
| 58 | |
| 59 | ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { |
| 60 | return llvm::makeArrayRef(GCCRegAliases); |
| 61 | } |
| 62 | |
| 63 | const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { |
| 64 | #define BUILTIN(ID, TYPE, ATTRS) \ |
| 65 | {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, |
| 66 | #include "clang/Basic/BuiltinsNEON.def" |
| 67 | |
| 68 | #define BUILTIN(ID, TYPE, ATTRS) \ |
| 69 | {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, |
| 70 | #include "clang/Basic/BuiltinsAArch64.def" |
| 71 | }; |