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gerrit-public.fairphone.software / toolchain / llvm-project / f65c5ac9c98938ad0de15452012112805a123e7f / . / llvm / lib / Target / AMDGPU / FLATInstructions.td
blob: 1f59f4817181554c003b6eb074e83ed4601aef0e [file] [log] [blame]
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]1//===-- FLATInstructions.td - FLAT Instruction Defintions -----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
Matt Arsenaultdb7c6a82017-06-12 16:53:51 +0000[diff] [blame]10def FLATAtomic : ComplexPattern<i64, 3, "SelectFlatAtomic", [], [], -10>;
11def FLATOffset : ComplexPattern<i64, 3, "SelectFlat", [], [], -10>;
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]12
13//===----------------------------------------------------------------------===//
14// FLAT classes
15//===----------------------------------------------------------------------===//
16
17class FLAT_Pseudo<string opName, dag outs, dag ins,
18 string asmOps, list<dag> pattern=[]> :
19 InstSI<outs, ins, "", pattern>,
20 SIMCInstr<opName, SIEncodingFamily.NONE> {
21
22 let isPseudo = 1;
23 let isCodeGenOnly = 1;
24
25 let SubtargetPredicate = isCIVI;
26
27 let FLAT = 1;
28 // Internally, FLAT instruction are executed as both an LDS and a
29 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT
30 // and are not considered done until both have been decremented.
31 let VM_CNT = 1;
32 let LGKM_CNT = 1;
33
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]34 let UseNamedOperandTable = 1;
35 let hasSideEffects = 0;
36 let SchedRW = [WriteVMEM];
37
38 string Mnemonic = opName;
39 string AsmOperands = asmOps;
40
Matt Arsenault9698f1c2017-06-20 19:54:14 +0000[diff] [blame]41 bits<1> is_flat_global = 0;
42 bits<1> is_flat_scratch = 0;
43
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]44 bits<1> has_vdst = 1;
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]45
46 // We need to distinguish having saddr and enabling saddr because
47 // saddr is only valid for scratch and global instructions. Pre-gfx9
48 // these bits were reserved, so we also don't necessarily want to
49 // set these bits to the disabled value for the original flat
50 // segment instructions.
51 bits<1> has_saddr = 0;
52 bits<1> enabled_saddr = 0;
53 bits<7> saddr_value = 0;
54
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]55 bits<1> has_data = 1;
56 bits<1> has_glc = 1;
57 bits<1> glcValue = 0;
Matt Arsenault9698f1c2017-06-20 19:54:14 +0000[diff] [blame]58
59 // TODO: M0 if it could possibly access LDS (before gfx9? only)?
60 let Uses = !if(is_flat_global, [EXEC], [EXEC, FLAT_SCR]);
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]61}
62
63class FLAT_Real <bits<7> op, FLAT_Pseudo ps> :
64 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
65 Enc64 {
66
67 let isPseudo = 0;
68 let isCodeGenOnly = 0;
69
70 // copy relevant pseudo op flags
71 let SubtargetPredicate = ps.SubtargetPredicate;
72 let AsmMatchConverter = ps.AsmMatchConverter;
Matt Arsenaultfd023142017-06-12 15:55:58 +0000[diff] [blame]73 let TSFlags = ps.TSFlags;
74 let UseNamedOperandTable = ps.UseNamedOperandTable;
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]75
76 // encoding fields
Matt Arsenault97279a82016-11-29 19:30:44 +0000[diff] [blame]77 bits<8> vaddr;
78 bits<8> vdata;
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]79 bits<7> saddr;
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]80 bits<8> vdst;
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]81
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]82 bits<1> slc;
83 bits<1> glc;
Matt Arsenault47ccafe2017-05-11 17:38:33 +0000[diff] [blame]84
Matt Arsenaultfd023142017-06-12 15:55:58 +0000[diff] [blame]85 // Only valid on gfx9
86 bits<1> lds = 0; // XXX - What does this actually do?
Matt Arsenault9698f1c2017-06-20 19:54:14 +0000[diff] [blame]87
88 // Segment, 00=flat, 01=scratch, 10=global, 11=reserved
89 bits<2> seg = !if(ps.is_flat_global, 0b10,
90 !if(ps.is_flat_scratch, 0b01, 0));
Matt Arsenaultfd023142017-06-12 15:55:58 +0000[diff] [blame]91
92 // Signed offset. Highest bit ignored for flat and treated as 12-bit
93 // unsigned for flat acceses.
94 bits<13> offset;
95 bits<1> nv = 0; // XXX - What does this actually do?
96
Matt Arsenault47ccafe2017-05-11 17:38:33 +0000[diff] [blame]97 // We don't use tfe right now, and it was removed in gfx9.
98 bits<1> tfe = 0;
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]99
Matt Arsenaultfd023142017-06-12 15:55:58 +0000[diff] [blame]100 // Only valid on GFX9+
101 let Inst{12-0} = offset;
102 let Inst{13} = lds;
Matt Arsenault9698f1c2017-06-20 19:54:14 +0000[diff] [blame]103 let Inst{15-14} = seg;
Matt Arsenaultfd023142017-06-12 15:55:58 +0000[diff] [blame]104
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]105 let Inst{16} = !if(ps.has_glc, glc, ps.glcValue);
106 let Inst{17} = slc;
107 let Inst{24-18} = op;
108 let Inst{31-26} = 0x37; // Encoding.
Matt Arsenault97279a82016-11-29 19:30:44 +0000[diff] [blame]109 let Inst{39-32} = vaddr;
110 let Inst{47-40} = !if(ps.has_data, vdata, ?);
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]111 let Inst{54-48} = !if(ps.has_saddr, !if(ps.enabled_saddr, saddr, 0x7f), 0);
112
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]113 // 54-48 is reserved.
Matt Arsenaultfd023142017-06-12 15:55:58 +0000[diff] [blame]114 let Inst{55} = nv; // nv on GFX9+, TFE before.
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]115 let Inst{63-56} = !if(ps.has_vdst, vdst, ?);
116}
117
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]118// TODO: Is exec allowed for saddr? The disabled value 0x7f is the
119// same encoding value as exec_hi, so it isn't possible to use that if
120// saddr is 32-bit (which isn't handled here yet).
Matt Arsenaultfd023142017-06-12 15:55:58 +0000[diff] [blame]121class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]122 bit HasSignedOffset = 0, bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]123 opName,
124 (outs regClass:$vdst),
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]125 !if(EnableSaddr,
126 !if(HasSignedOffset,
127 (ins VReg_64:$vaddr, SReg_64:$saddr, offset_s13:$offset, GLC:$glc, slc:$slc),
128 (ins VReg_64:$vaddr, SReg_64:$saddr, offset_u12:$offset, GLC:$glc, slc:$slc)),
129 !if(HasSignedOffset,
130 (ins VReg_64:$vaddr, offset_s13:$offset, GLC:$glc, slc:$slc),
131 (ins VReg_64:$vaddr, offset_u12:$offset, GLC:$glc, slc:$slc))),
132 " $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc"> {
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]133 let has_data = 0;
134 let mayLoad = 1;
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]135 let has_saddr = HasSaddr;
136 let enabled_saddr = EnableSaddr;
137 let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]138}
139
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]140multiclass FLAT_Global_Load_Pseudo<string opName, RegisterClass regClass> {
141 let is_flat_global = 1 in {
142 def "" : FLAT_Load_Pseudo<opName, regClass, 1, 1>;
143 def _SADDR : FLAT_Load_Pseudo<opName, regClass, 1, 1, 1>;
144 }
Matt Arsenault9698f1c2017-06-20 19:54:14 +0000[diff] [blame]145}
146
147class FLAT_Scratch_Load_Pseudo<string opName, RegisterClass regClass> :
148 FLAT_Load_Pseudo<opName, regClass, 1> {
149 let is_flat_scratch = 1;
150}
151
Matt Arsenaultfd023142017-06-12 15:55:58 +0000[diff] [blame]152class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]153 bit HasSignedOffset = 0, bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]154 opName,
155 (outs),
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]156 !if(EnableSaddr,
157 !if(HasSignedOffset,
158 (ins VReg_64:$vaddr, vdataClass:$vdata, SReg_64:$saddr, offset_s13:$offset, GLC:$glc, slc:$slc),
159 (ins VReg_64:$vaddr, vdataClass:$vdata, SReg_64:$saddr, offset_u12:$offset, GLC:$glc, slc:$slc)),
160 !if(HasSignedOffset,
161 (ins VReg_64:$vaddr, vdataClass:$vdata, offset_s13:$offset, GLC:$glc, slc:$slc),
162 (ins VReg_64:$vaddr, vdataClass:$vdata, offset_u12:$offset, GLC:$glc, slc:$slc))),
163 " $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc"> {
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]164 let mayLoad = 0;
165 let mayStore = 1;
166 let has_vdst = 0;
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]167 let has_saddr = HasSaddr;
168 let enabled_saddr = EnableSaddr;
169 let PseudoInstr = opName#!if(!and(HasSaddr, EnableSaddr), "_SADDR", "");
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]170}
171
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]172multiclass FLAT_Global_Store_Pseudo<string opName, RegisterClass regClass> {
173 let is_flat_global = 1 in {
174 def "" : FLAT_Store_Pseudo<opName, regClass, 1, 1>;
175 def _SADDR : FLAT_Store_Pseudo<opName, regClass, 1, 1, 1>;
176 }
Matt Arsenault9698f1c2017-06-20 19:54:14 +0000[diff] [blame]177}
178
179class FLAT_Scratch_Store_Pseudo<string opName, RegisterClass regClass> :
180 FLAT_Store_Pseudo<opName, regClass, 1> {
181 let is_flat_scratch = 1;
182}
183
Matt Arsenaultf65c5ac2017-07-20 17:31:56 +0000[diff] [blame^]184class FLAT_AtomicNoRet_Pseudo<string opName, dag outs, dag ins,
185 string asm, list<dag> pattern = []> :
186 FLAT_Pseudo<opName, outs, ins, asm, pattern> {
187 let mayLoad = 1;
188 let mayStore = 1;
189 let has_glc = 0;
190 let glcValue = 0;
191 let has_vdst = 0;
192}
193
194class FLAT_AtomicRet_Pseudo<string opName, dag outs, dag ins,
195 string asm, list<dag> pattern = []>
196 : FLAT_AtomicNoRet_Pseudo<opName, outs, ins, asm, pattern> {
197 let hasPostISelHook = 1;
198 let has_vdst = 1;
199 let glcValue = 1;
200 let PseudoInstr = NAME # "_RTN";
201}
202
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]203multiclass FLAT_Atomic_Pseudo<
204 string opName,
205 RegisterClass vdst_rc,
206 ValueType vt,
207 SDPatternOperator atomic = null_frag,
208 ValueType data_vt = vt,
Matt Arsenaultf65c5ac2017-07-20 17:31:56 +0000[diff] [blame^]209 RegisterClass data_rc = vdst_rc> {
210 def "" : FLAT_AtomicNoRet_Pseudo <opName,
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]211 (outs),
Matt Arsenaultf65c5ac2017-07-20 17:31:56 +0000[diff] [blame^]212 (ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc),
213 " $vaddr, $vdata$offset$slc">,
214 AtomicNoRet <opName, 0> {
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]215 let PseudoInstr = NAME;
216 }
217
Matt Arsenaultf65c5ac2017-07-20 17:31:56 +0000[diff] [blame^]218 def _RTN : FLAT_AtomicRet_Pseudo <opName,
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]219 (outs vdst_rc:$vdst),
Matt Arsenaultf65c5ac2017-07-20 17:31:56 +0000[diff] [blame^]220 (ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, slc:$slc),
Matt Arsenaultfd023142017-06-12 15:55:58 +0000[diff] [blame]221 " $vdst, $vaddr, $vdata$offset glc$slc",
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]222 [(set vt:$vdst,
Matt Arsenaultfd023142017-06-12 15:55:58 +0000[diff] [blame]223 (atomic (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
Matt Arsenaultf65c5ac2017-07-20 17:31:56 +0000[diff] [blame^]224 AtomicNoRet <opName, 1>;
225}
226
227multiclass FLAT_Global_Atomic_Pseudo<
228 string opName,
229 RegisterClass vdst_rc,
230 ValueType vt,
231 SDPatternOperator atomic = null_frag,
232 ValueType data_vt = vt,
233 RegisterClass data_rc = vdst_rc> {
234
235 def "" : FLAT_AtomicNoRet_Pseudo <opName,
236 (outs),
237 (ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, slc:$slc),
238 " $vaddr, $vdata, off$offset$slc">,
239 AtomicNoRet <opName, 0> {
240 let has_saddr = 1;
241 let PseudoInstr = NAME;
242 }
243
244 def _RTN : FLAT_AtomicRet_Pseudo <opName,
245 (outs vdst_rc:$vdst),
246 (ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, slc:$slc),
247 " $vdst, $vaddr, $vdata, off$offset glc$slc",
248 [(set vt:$vdst,
249 (atomic (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
250 AtomicNoRet <opName, 1> {
251 let has_saddr = 1;
252 }
253
254 def _SADDR : FLAT_AtomicNoRet_Pseudo <opName,
255 (outs),
256 (ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, slc:$slc),
257 " $vaddr, $vdata$saddr$offset$slc">,
258 AtomicNoRet <opName#"_saddr", 0> {
259 let has_saddr = 1;
260 let enabled_saddr = 1;
261 let PseudoInstr = NAME#"_SADDR";
262 }
263
264 def _SADDR_RTN : FLAT_AtomicRet_Pseudo <opName,
265 (outs vdst_rc:$vdst),
266 (ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, slc:$slc),
267 " $vdst, $vaddr, $vdata$saddr$offset glc$slc">,
268 AtomicNoRet <opName#"_saddr", 1> {
269 let has_saddr = 1;
270 let enabled_saddr = 1;
271 let PseudoInstr = NAME#"_SADDR_RTN";
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]272 }
273}
274
275class flat_binary_atomic_op<SDNode atomic_op> : PatFrag<
276 (ops node:$ptr, node:$value),
277 (atomic_op node:$ptr, node:$value),
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000[diff] [blame]278 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUASI.FLAT_ADDRESS;}]
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]279>;
280
281def atomic_cmp_swap_flat : flat_binary_atomic_op<AMDGPUatomic_cmp_swap>;
282def atomic_swap_flat : flat_binary_atomic_op<atomic_swap>;
283def atomic_add_flat : flat_binary_atomic_op<atomic_load_add>;
284def atomic_and_flat : flat_binary_atomic_op<atomic_load_and>;
285def atomic_max_flat : flat_binary_atomic_op<atomic_load_max>;
286def atomic_min_flat : flat_binary_atomic_op<atomic_load_min>;
287def atomic_or_flat : flat_binary_atomic_op<atomic_load_or>;
288def atomic_sub_flat : flat_binary_atomic_op<atomic_load_sub>;
289def atomic_umax_flat : flat_binary_atomic_op<atomic_load_umax>;
290def atomic_umin_flat : flat_binary_atomic_op<atomic_load_umin>;
291def atomic_xor_flat : flat_binary_atomic_op<atomic_load_xor>;
292def atomic_inc_flat : flat_binary_atomic_op<SIatomic_inc>;
293def atomic_dec_flat : flat_binary_atomic_op<SIatomic_dec>;
294
295
296
297//===----------------------------------------------------------------------===//
298// Flat Instructions
299//===----------------------------------------------------------------------===//
300
301def FLAT_LOAD_UBYTE : FLAT_Load_Pseudo <"flat_load_ubyte", VGPR_32>;
302def FLAT_LOAD_SBYTE : FLAT_Load_Pseudo <"flat_load_sbyte", VGPR_32>;
303def FLAT_LOAD_USHORT : FLAT_Load_Pseudo <"flat_load_ushort", VGPR_32>;
304def FLAT_LOAD_SSHORT : FLAT_Load_Pseudo <"flat_load_sshort", VGPR_32>;
305def FLAT_LOAD_DWORD : FLAT_Load_Pseudo <"flat_load_dword", VGPR_32>;
306def FLAT_LOAD_DWORDX2 : FLAT_Load_Pseudo <"flat_load_dwordx2", VReg_64>;
307def FLAT_LOAD_DWORDX4 : FLAT_Load_Pseudo <"flat_load_dwordx4", VReg_128>;
308def FLAT_LOAD_DWORDX3 : FLAT_Load_Pseudo <"flat_load_dwordx3", VReg_96>;
309
310def FLAT_STORE_BYTE : FLAT_Store_Pseudo <"flat_store_byte", VGPR_32>;
311def FLAT_STORE_SHORT : FLAT_Store_Pseudo <"flat_store_short", VGPR_32>;
312def FLAT_STORE_DWORD : FLAT_Store_Pseudo <"flat_store_dword", VGPR_32>;
313def FLAT_STORE_DWORDX2 : FLAT_Store_Pseudo <"flat_store_dwordx2", VReg_64>;
314def FLAT_STORE_DWORDX4 : FLAT_Store_Pseudo <"flat_store_dwordx4", VReg_128>;
315def FLAT_STORE_DWORDX3 : FLAT_Store_Pseudo <"flat_store_dwordx3", VReg_96>;
316
317defm FLAT_ATOMIC_CMPSWAP : FLAT_Atomic_Pseudo <"flat_atomic_cmpswap",
318 VGPR_32, i32, atomic_cmp_swap_flat,
319 v2i32, VReg_64>;
320
321defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_Atomic_Pseudo <"flat_atomic_cmpswap_x2",
322 VReg_64, i64, atomic_cmp_swap_flat,
323 v2i64, VReg_128>;
324
325defm FLAT_ATOMIC_SWAP : FLAT_Atomic_Pseudo <"flat_atomic_swap",
326 VGPR_32, i32, atomic_swap_flat>;
327
328defm FLAT_ATOMIC_SWAP_X2 : FLAT_Atomic_Pseudo <"flat_atomic_swap_x2",
329 VReg_64, i64, atomic_swap_flat>;
330
331defm FLAT_ATOMIC_ADD : FLAT_Atomic_Pseudo <"flat_atomic_add",
332 VGPR_32, i32, atomic_add_flat>;
333
334defm FLAT_ATOMIC_SUB : FLAT_Atomic_Pseudo <"flat_atomic_sub",
335 VGPR_32, i32, atomic_sub_flat>;
336
337defm FLAT_ATOMIC_SMIN : FLAT_Atomic_Pseudo <"flat_atomic_smin",
338 VGPR_32, i32, atomic_min_flat>;
339
340defm FLAT_ATOMIC_UMIN : FLAT_Atomic_Pseudo <"flat_atomic_umin",
341 VGPR_32, i32, atomic_umin_flat>;
342
343defm FLAT_ATOMIC_SMAX : FLAT_Atomic_Pseudo <"flat_atomic_smax",
344 VGPR_32, i32, atomic_max_flat>;
345
346defm FLAT_ATOMIC_UMAX : FLAT_Atomic_Pseudo <"flat_atomic_umax",
347 VGPR_32, i32, atomic_umax_flat>;
348
349defm FLAT_ATOMIC_AND : FLAT_Atomic_Pseudo <"flat_atomic_and",
350 VGPR_32, i32, atomic_and_flat>;
351
352defm FLAT_ATOMIC_OR : FLAT_Atomic_Pseudo <"flat_atomic_or",
353 VGPR_32, i32, atomic_or_flat>;
354
355defm FLAT_ATOMIC_XOR : FLAT_Atomic_Pseudo <"flat_atomic_xor",
356 VGPR_32, i32, atomic_xor_flat>;
357
358defm FLAT_ATOMIC_INC : FLAT_Atomic_Pseudo <"flat_atomic_inc",
359 VGPR_32, i32, atomic_inc_flat>;
360
361defm FLAT_ATOMIC_DEC : FLAT_Atomic_Pseudo <"flat_atomic_dec",
362 VGPR_32, i32, atomic_dec_flat>;
363
364defm FLAT_ATOMIC_ADD_X2 : FLAT_Atomic_Pseudo <"flat_atomic_add_x2",
365 VReg_64, i64, atomic_add_flat>;
366
367defm FLAT_ATOMIC_SUB_X2 : FLAT_Atomic_Pseudo <"flat_atomic_sub_x2",
368 VReg_64, i64, atomic_sub_flat>;
369
370defm FLAT_ATOMIC_SMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_smin_x2",
371 VReg_64, i64, atomic_min_flat>;
372
373defm FLAT_ATOMIC_UMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_umin_x2",
374 VReg_64, i64, atomic_umin_flat>;
375
376defm FLAT_ATOMIC_SMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_smax_x2",
377 VReg_64, i64, atomic_max_flat>;
378
379defm FLAT_ATOMIC_UMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_umax_x2",
380 VReg_64, i64, atomic_umax_flat>;
381
382defm FLAT_ATOMIC_AND_X2 : FLAT_Atomic_Pseudo <"flat_atomic_and_x2",
383 VReg_64, i64, atomic_and_flat>;
384
385defm FLAT_ATOMIC_OR_X2 : FLAT_Atomic_Pseudo <"flat_atomic_or_x2",
386 VReg_64, i64, atomic_or_flat>;
387
388defm FLAT_ATOMIC_XOR_X2 : FLAT_Atomic_Pseudo <"flat_atomic_xor_x2",
389 VReg_64, i64, atomic_xor_flat>;
390
391defm FLAT_ATOMIC_INC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_inc_x2",
392 VReg_64, i64, atomic_inc_flat>;
393
394defm FLAT_ATOMIC_DEC_X2 : FLAT_Atomic_Pseudo <"flat_atomic_dec_x2",
395 VReg_64, i64, atomic_dec_flat>;
396
397let SubtargetPredicate = isCI in { // CI Only flat instructions : FIXME Only?
398
399defm FLAT_ATOMIC_FCMPSWAP : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap",
400 VGPR_32, f32, null_frag, v2f32, VReg_64>;
401
402defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fcmpswap_x2",
403 VReg_64, f64, null_frag, v2f64, VReg_128>;
404
405defm FLAT_ATOMIC_FMIN : FLAT_Atomic_Pseudo <"flat_atomic_fmin",
406 VGPR_32, f32>;
407
408defm FLAT_ATOMIC_FMAX : FLAT_Atomic_Pseudo <"flat_atomic_fmax",
409 VGPR_32, f32>;
410
411defm FLAT_ATOMIC_FMIN_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmin_x2",
412 VReg_64, f64>;
413
414defm FLAT_ATOMIC_FMAX_X2 : FLAT_Atomic_Pseudo <"flat_atomic_fmax_x2",
415 VReg_64, f64>;
416
417} // End SubtargetPredicate = isCI
418
Matt Arsenault9698f1c2017-06-20 19:54:14 +0000[diff] [blame]419let SubtargetPredicate = HasFlatGlobalInsts in {
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]420defm GLOBAL_LOAD_UBYTE : FLAT_Global_Load_Pseudo <"global_load_ubyte", VGPR_32>;
421defm GLOBAL_LOAD_SBYTE : FLAT_Global_Load_Pseudo <"global_load_sbyte", VGPR_32>;
422defm GLOBAL_LOAD_USHORT : FLAT_Global_Load_Pseudo <"global_load_ushort", VGPR_32>;
423defm GLOBAL_LOAD_SSHORT : FLAT_Global_Load_Pseudo <"global_load_sshort", VGPR_32>;
424defm GLOBAL_LOAD_DWORD : FLAT_Global_Load_Pseudo <"global_load_dword", VGPR_32>;
425defm GLOBAL_LOAD_DWORDX2 : FLAT_Global_Load_Pseudo <"global_load_dwordx2", VReg_64>;
426defm GLOBAL_LOAD_DWORDX3 : FLAT_Global_Load_Pseudo <"global_load_dwordx3", VReg_96>;
427defm GLOBAL_LOAD_DWORDX4 : FLAT_Global_Load_Pseudo <"global_load_dwordx4", VReg_128>;
Matt Arsenault9698f1c2017-06-20 19:54:14 +0000[diff] [blame]428
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]429defm GLOBAL_STORE_BYTE : FLAT_Global_Store_Pseudo <"global_store_byte", VGPR_32>;
430defm GLOBAL_STORE_SHORT : FLAT_Global_Store_Pseudo <"global_store_short", VGPR_32>;
431defm GLOBAL_STORE_DWORD : FLAT_Global_Store_Pseudo <"global_store_dword", VGPR_32>;
432defm GLOBAL_STORE_DWORDX2 : FLAT_Global_Store_Pseudo <"global_store_dwordx2", VReg_64>;
433defm GLOBAL_STORE_DWORDX3 : FLAT_Global_Store_Pseudo <"global_store_dwordx3", VReg_96>;
434defm GLOBAL_STORE_DWORDX4 : FLAT_Global_Store_Pseudo <"global_store_dwordx4", VReg_128>;
Matt Arsenault9698f1c2017-06-20 19:54:14 +0000[diff] [blame]435
Matt Arsenaultf65c5ac2017-07-20 17:31:56 +0000[diff] [blame^]436
437let is_flat_global = 1 in {
438defm GLOBAL_ATOMIC_CMPSWAP : FLAT_Global_Atomic_Pseudo <"global_atomic_cmpswap",
439 VGPR_32, i32, AMDGPUatomic_cmp_swap_global,
440 v2i32, VReg_64>;
441
442defm GLOBAL_ATOMIC_CMPSWAP_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_cmpswap_x2",
443 VReg_64, i64, AMDGPUatomic_cmp_swap_global,
444 v2i64, VReg_128>;
445
446defm GLOBAL_ATOMIC_SWAP : FLAT_Global_Atomic_Pseudo <"global_atomic_swap",
447 VGPR_32, i32, atomic_swap_global>;
448
449defm GLOBAL_ATOMIC_SWAP_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_swap_x2",
450 VReg_64, i64, atomic_swap_global>;
451
452defm GLOBAL_ATOMIC_ADD : FLAT_Global_Atomic_Pseudo <"global_atomic_add",
453 VGPR_32, i32, atomic_add_global>;
454
455defm GLOBAL_ATOMIC_SUB : FLAT_Global_Atomic_Pseudo <"global_atomic_sub",
456 VGPR_32, i32, atomic_sub_global>;
457
458defm GLOBAL_ATOMIC_SMIN : FLAT_Global_Atomic_Pseudo <"global_atomic_smin",
459 VGPR_32, i32, atomic_min_global>;
460
461defm GLOBAL_ATOMIC_UMIN : FLAT_Global_Atomic_Pseudo <"global_atomic_umin",
462 VGPR_32, i32, atomic_umin_global>;
463
464defm GLOBAL_ATOMIC_SMAX : FLAT_Global_Atomic_Pseudo <"global_atomic_smax",
465 VGPR_32, i32, atomic_max_global>;
466
467defm GLOBAL_ATOMIC_UMAX : FLAT_Global_Atomic_Pseudo <"global_atomic_umax",
468 VGPR_32, i32, atomic_umax_global>;
469
470defm GLOBAL_ATOMIC_AND : FLAT_Global_Atomic_Pseudo <"global_atomic_and",
471 VGPR_32, i32, atomic_and_global>;
472
473defm GLOBAL_ATOMIC_OR : FLAT_Global_Atomic_Pseudo <"global_atomic_or",
474 VGPR_32, i32, atomic_or_global>;
475
476defm GLOBAL_ATOMIC_XOR : FLAT_Global_Atomic_Pseudo <"global_atomic_xor",
477 VGPR_32, i32, atomic_xor_global>;
478
479defm GLOBAL_ATOMIC_INC : FLAT_Global_Atomic_Pseudo <"global_atomic_inc",
480 VGPR_32, i32, atomic_inc_global>;
481
482defm GLOBAL_ATOMIC_DEC : FLAT_Global_Atomic_Pseudo <"global_atomic_dec",
483 VGPR_32, i32, atomic_dec_global>;
484
485defm GLOBAL_ATOMIC_ADD_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_add_x2",
486 VReg_64, i64, atomic_add_global>;
487
488defm GLOBAL_ATOMIC_SUB_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_sub_x2",
489 VReg_64, i64, atomic_sub_global>;
490
491defm GLOBAL_ATOMIC_SMIN_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_smin_x2",
492 VReg_64, i64, atomic_min_global>;
493
494defm GLOBAL_ATOMIC_UMIN_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_umin_x2",
495 VReg_64, i64, atomic_umin_global>;
496
497defm GLOBAL_ATOMIC_SMAX_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_smax_x2",
498 VReg_64, i64, atomic_max_global>;
499
500defm GLOBAL_ATOMIC_UMAX_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_umax_x2",
501 VReg_64, i64, atomic_umax_global>;
502
503defm GLOBAL_ATOMIC_AND_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_and_x2",
504 VReg_64, i64, atomic_and_global>;
505
506defm GLOBAL_ATOMIC_OR_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_or_x2",
507 VReg_64, i64, atomic_or_global>;
508
509defm GLOBAL_ATOMIC_XOR_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_xor_x2",
510 VReg_64, i64, atomic_xor_global>;
511
512defm GLOBAL_ATOMIC_INC_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_inc_x2",
513 VReg_64, i64, atomic_inc_global>;
514
515defm GLOBAL_ATOMIC_DEC_X2 : FLAT_Global_Atomic_Pseudo <"global_atomic_dec_x2",
516 VReg_64, i64, atomic_dec_global>;
517} // End is_flat_global = 1
518
Matt Arsenault9698f1c2017-06-20 19:54:14 +0000[diff] [blame]519} // End SubtargetPredicate = HasFlatGlobalInsts
520
521
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]522//===----------------------------------------------------------------------===//
523// Flat Patterns
524//===----------------------------------------------------------------------===//
525
526class flat_ld <SDPatternOperator ld> : PatFrag<(ops node:$ptr),
527 (ld node:$ptr), [{
528 auto const AS = cast<MemSDNode>(N)->getAddressSpace();
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000[diff] [blame]529 return AS == AMDGPUASI.FLAT_ADDRESS ||
530 AS == AMDGPUASI.GLOBAL_ADDRESS ||
531 AS == AMDGPUASI.CONSTANT_ADDRESS;
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]532}]>;
533
534class flat_st <SDPatternOperator st> : PatFrag<(ops node:$val, node:$ptr),
535 (st node:$val, node:$ptr), [{
536 auto const AS = cast<MemSDNode>(N)->getAddressSpace();
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000[diff] [blame]537 return AS == AMDGPUASI.FLAT_ADDRESS ||
538 AS == AMDGPUASI.GLOBAL_ADDRESS;
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]539}]>;
540
541def atomic_flat_load : flat_ld <atomic_load>;
542def flat_load : flat_ld <load>;
543def flat_az_extloadi8 : flat_ld <az_extloadi8>;
544def flat_sextloadi8 : flat_ld <sextloadi8>;
545def flat_az_extloadi16 : flat_ld <az_extloadi16>;
546def flat_sextloadi16 : flat_ld <sextloadi16>;
547
548def atomic_flat_store : flat_st <atomic_store>;
549def flat_store : flat_st <store>;
550def flat_truncstorei8 : flat_st <truncstorei8>;
551def flat_truncstorei16 : flat_st <truncstorei16>;
552
553// Patterns for global loads with no offset.
554class FlatLoadPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
Matt Arsenaultdb7c6a82017-06-12 16:53:51 +0000[diff] [blame]555 (vt (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc))),
556 (inst $vaddr, $offset, 0, $slc)
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]557>;
558
559class FlatLoadAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
Matt Arsenaultdb7c6a82017-06-12 16:53:51 +0000[diff] [blame]560 (vt (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc))),
561 (inst $vaddr, $offset, 1, $slc)
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]562>;
563
564class FlatStorePat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
Matt Arsenaultdb7c6a82017-06-12 16:53:51 +0000[diff] [blame]565 (node vt:$data, (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc)),
566 (inst $vaddr, $data, $offset, 0, $slc)
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]567>;
568
569class FlatStoreAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt> : Pat <
570 // atomic store follows atomic binop convention so the address comes
571 // first.
Matt Arsenaultdb7c6a82017-06-12 16:53:51 +0000[diff] [blame]572 (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), vt:$data),
573 (inst $vaddr, $data, $offset, 1, $slc)
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]574>;
575
576class FlatAtomicPat <FLAT_Pseudo inst, SDPatternOperator node, ValueType vt,
577 ValueType data_vt = vt> : Pat <
Matt Arsenaultdb7c6a82017-06-12 16:53:51 +0000[diff] [blame]578 (vt (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$data)),
579 (inst $vaddr, $data, $offset, $slc)
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]580>;
581
582let Predicates = [isCIVI] in {
583
584def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i32>;
585def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i32>;
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]586def : FlatLoadPat <FLAT_LOAD_UBYTE, flat_az_extloadi8, i16>;
587def : FlatLoadPat <FLAT_LOAD_SBYTE, flat_sextloadi8, i16>;
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]588def : FlatLoadPat <FLAT_LOAD_USHORT, flat_az_extloadi16, i32>;
589def : FlatLoadPat <FLAT_LOAD_SSHORT, flat_sextloadi16, i32>;
590def : FlatLoadPat <FLAT_LOAD_DWORD, flat_load, i32>;
591def : FlatLoadPat <FLAT_LOAD_DWORDX2, flat_load, v2i32>;
592def : FlatLoadPat <FLAT_LOAD_DWORDX4, flat_load, v4i32>;
593
594def : FlatLoadAtomicPat <FLAT_LOAD_DWORD, atomic_flat_load, i32>;
595def : FlatLoadAtomicPat <FLAT_LOAD_DWORDX2, atomic_flat_load, i64>;
596
597def : FlatStorePat <FLAT_STORE_BYTE, flat_truncstorei8, i32>;
598def : FlatStorePat <FLAT_STORE_SHORT, flat_truncstorei16, i32>;
599def : FlatStorePat <FLAT_STORE_DWORD, flat_store, i32>;
600def : FlatStorePat <FLAT_STORE_DWORDX2, flat_store, v2i32>;
601def : FlatStorePat <FLAT_STORE_DWORDX4, flat_store, v4i32>;
602
603def : FlatStoreAtomicPat <FLAT_STORE_DWORD, atomic_flat_store, i32>;
604def : FlatStoreAtomicPat <FLAT_STORE_DWORDX2, atomic_flat_store, i64>;
605
606def : FlatAtomicPat <FLAT_ATOMIC_ADD_RTN, atomic_add_global, i32>;
607def : FlatAtomicPat <FLAT_ATOMIC_SUB_RTN, atomic_sub_global, i32>;
608def : FlatAtomicPat <FLAT_ATOMIC_INC_RTN, atomic_inc_global, i32>;
609def : FlatAtomicPat <FLAT_ATOMIC_DEC_RTN, atomic_dec_global, i32>;
610def : FlatAtomicPat <FLAT_ATOMIC_AND_RTN, atomic_and_global, i32>;
611def : FlatAtomicPat <FLAT_ATOMIC_SMAX_RTN, atomic_max_global, i32>;
612def : FlatAtomicPat <FLAT_ATOMIC_UMAX_RTN, atomic_umax_global, i32>;
613def : FlatAtomicPat <FLAT_ATOMIC_SMIN_RTN, atomic_min_global, i32>;
614def : FlatAtomicPat <FLAT_ATOMIC_UMIN_RTN, atomic_umin_global, i32>;
615def : FlatAtomicPat <FLAT_ATOMIC_OR_RTN, atomic_or_global, i32>;
616def : FlatAtomicPat <FLAT_ATOMIC_SWAP_RTN, atomic_swap_global, i32>;
Jan Vesely206a5102016-12-23 15:34:51 +0000[diff] [blame]617def : FlatAtomicPat <FLAT_ATOMIC_CMPSWAP_RTN, AMDGPUatomic_cmp_swap_global, i32, v2i32>;
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]618def : FlatAtomicPat <FLAT_ATOMIC_XOR_RTN, atomic_xor_global, i32>;
619
620def : FlatAtomicPat <FLAT_ATOMIC_ADD_X2_RTN, atomic_add_global, i64>;
621def : FlatAtomicPat <FLAT_ATOMIC_SUB_X2_RTN, atomic_sub_global, i64>;
622def : FlatAtomicPat <FLAT_ATOMIC_INC_X2_RTN, atomic_inc_global, i64>;
623def : FlatAtomicPat <FLAT_ATOMIC_DEC_X2_RTN, atomic_dec_global, i64>;
624def : FlatAtomicPat <FLAT_ATOMIC_AND_X2_RTN, atomic_and_global, i64>;
625def : FlatAtomicPat <FLAT_ATOMIC_SMAX_X2_RTN, atomic_max_global, i64>;
626def : FlatAtomicPat <FLAT_ATOMIC_UMAX_X2_RTN, atomic_umax_global, i64>;
627def : FlatAtomicPat <FLAT_ATOMIC_SMIN_X2_RTN, atomic_min_global, i64>;
628def : FlatAtomicPat <FLAT_ATOMIC_UMIN_X2_RTN, atomic_umin_global, i64>;
629def : FlatAtomicPat <FLAT_ATOMIC_OR_X2_RTN, atomic_or_global, i64>;
630def : FlatAtomicPat <FLAT_ATOMIC_SWAP_X2_RTN, atomic_swap_global, i64>;
Jan Vesely206a5102016-12-23 15:34:51 +0000[diff] [blame]631def : FlatAtomicPat <FLAT_ATOMIC_CMPSWAP_X2_RTN, AMDGPUatomic_cmp_swap_global, i64, v2i64>;
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]632def : FlatAtomicPat <FLAT_ATOMIC_XOR_X2_RTN, atomic_xor_global, i64>;
633
634} // End Predicates = [isCIVI]
635
Tom Stellard115a6152016-11-10 16:02:37 +0000[diff] [blame]636let Predicates = [isVI] in {
637 def : FlatStorePat <FLAT_STORE_BYTE, flat_truncstorei8, i16>;
638 def : FlatStorePat <FLAT_STORE_SHORT, flat_store, i16>;
639}
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]640
641
642//===----------------------------------------------------------------------===//
643// Target
644//===----------------------------------------------------------------------===//
645
646//===----------------------------------------------------------------------===//
647// CI
648//===----------------------------------------------------------------------===//
649
650class FLAT_Real_ci <bits<7> op, FLAT_Pseudo ps> :
651 FLAT_Real <op, ps>,
652 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SI> {
653 let AssemblerPredicate = isCIOnly;
654 let DecoderNamespace="CI";
655}
656
657def FLAT_LOAD_UBYTE_ci : FLAT_Real_ci <0x8, FLAT_LOAD_UBYTE>;
658def FLAT_LOAD_SBYTE_ci : FLAT_Real_ci <0x9, FLAT_LOAD_SBYTE>;
659def FLAT_LOAD_USHORT_ci : FLAT_Real_ci <0xa, FLAT_LOAD_USHORT>;
660def FLAT_LOAD_SSHORT_ci : FLAT_Real_ci <0xb, FLAT_LOAD_SSHORT>;
661def FLAT_LOAD_DWORD_ci : FLAT_Real_ci <0xc, FLAT_LOAD_DWORD>;
662def FLAT_LOAD_DWORDX2_ci : FLAT_Real_ci <0xd, FLAT_LOAD_DWORDX2>;
663def FLAT_LOAD_DWORDX4_ci : FLAT_Real_ci <0xe, FLAT_LOAD_DWORDX4>;
664def FLAT_LOAD_DWORDX3_ci : FLAT_Real_ci <0xf, FLAT_LOAD_DWORDX3>;
665
666def FLAT_STORE_BYTE_ci : FLAT_Real_ci <0x18, FLAT_STORE_BYTE>;
667def FLAT_STORE_SHORT_ci : FLAT_Real_ci <0x1a, FLAT_STORE_SHORT>;
668def FLAT_STORE_DWORD_ci : FLAT_Real_ci <0x1c, FLAT_STORE_DWORD>;
669def FLAT_STORE_DWORDX2_ci : FLAT_Real_ci <0x1d, FLAT_STORE_DWORDX2>;
670def FLAT_STORE_DWORDX4_ci : FLAT_Real_ci <0x1e, FLAT_STORE_DWORDX4>;
671def FLAT_STORE_DWORDX3_ci : FLAT_Real_ci <0x1f, FLAT_STORE_DWORDX3>;
672
673multiclass FLAT_Real_Atomics_ci <bits<7> op, FLAT_Pseudo ps> {
674 def _ci : FLAT_Real_ci<op, !cast<FLAT_Pseudo>(ps.PseudoInstr)>;
675 def _RTN_ci : FLAT_Real_ci<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN")>;
676}
677
678defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_ci <0x30, FLAT_ATOMIC_SWAP>;
679defm FLAT_ATOMIC_CMPSWAP : FLAT_Real_Atomics_ci <0x31, FLAT_ATOMIC_CMPSWAP>;
680defm FLAT_ATOMIC_ADD : FLAT_Real_Atomics_ci <0x32, FLAT_ATOMIC_ADD>;
681defm FLAT_ATOMIC_SUB : FLAT_Real_Atomics_ci <0x33, FLAT_ATOMIC_SUB>;
682defm FLAT_ATOMIC_SMIN : FLAT_Real_Atomics_ci <0x35, FLAT_ATOMIC_SMIN>;
683defm FLAT_ATOMIC_UMIN : FLAT_Real_Atomics_ci <0x36, FLAT_ATOMIC_UMIN>;
684defm FLAT_ATOMIC_SMAX : FLAT_Real_Atomics_ci <0x37, FLAT_ATOMIC_SMAX>;
685defm FLAT_ATOMIC_UMAX : FLAT_Real_Atomics_ci <0x38, FLAT_ATOMIC_UMAX>;
686defm FLAT_ATOMIC_AND : FLAT_Real_Atomics_ci <0x39, FLAT_ATOMIC_AND>;
687defm FLAT_ATOMIC_OR : FLAT_Real_Atomics_ci <0x3a, FLAT_ATOMIC_OR>;
688defm FLAT_ATOMIC_XOR : FLAT_Real_Atomics_ci <0x3b, FLAT_ATOMIC_XOR>;
689defm FLAT_ATOMIC_INC : FLAT_Real_Atomics_ci <0x3c, FLAT_ATOMIC_INC>;
690defm FLAT_ATOMIC_DEC : FLAT_Real_Atomics_ci <0x3d, FLAT_ATOMIC_DEC>;
691defm FLAT_ATOMIC_SWAP_X2 : FLAT_Real_Atomics_ci <0x50, FLAT_ATOMIC_SWAP_X2>;
692defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_Real_Atomics_ci <0x51, FLAT_ATOMIC_CMPSWAP_X2>;
693defm FLAT_ATOMIC_ADD_X2 : FLAT_Real_Atomics_ci <0x52, FLAT_ATOMIC_ADD_X2>;
694defm FLAT_ATOMIC_SUB_X2 : FLAT_Real_Atomics_ci <0x53, FLAT_ATOMIC_SUB_X2>;
695defm FLAT_ATOMIC_SMIN_X2 : FLAT_Real_Atomics_ci <0x55, FLAT_ATOMIC_SMIN_X2>;
696defm FLAT_ATOMIC_UMIN_X2 : FLAT_Real_Atomics_ci <0x56, FLAT_ATOMIC_UMIN_X2>;
697defm FLAT_ATOMIC_SMAX_X2 : FLAT_Real_Atomics_ci <0x57, FLAT_ATOMIC_SMAX_X2>;
698defm FLAT_ATOMIC_UMAX_X2 : FLAT_Real_Atomics_ci <0x58, FLAT_ATOMIC_UMAX_X2>;
699defm FLAT_ATOMIC_AND_X2 : FLAT_Real_Atomics_ci <0x59, FLAT_ATOMIC_AND_X2>;
700defm FLAT_ATOMIC_OR_X2 : FLAT_Real_Atomics_ci <0x5a, FLAT_ATOMIC_OR_X2>;
701defm FLAT_ATOMIC_XOR_X2 : FLAT_Real_Atomics_ci <0x5b, FLAT_ATOMIC_XOR_X2>;
702defm FLAT_ATOMIC_INC_X2 : FLAT_Real_Atomics_ci <0x5c, FLAT_ATOMIC_INC_X2>;
703defm FLAT_ATOMIC_DEC_X2 : FLAT_Real_Atomics_ci <0x5d, FLAT_ATOMIC_DEC_X2>;
704
705// CI Only flat instructions
706defm FLAT_ATOMIC_FCMPSWAP : FLAT_Real_Atomics_ci <0x3e, FLAT_ATOMIC_FCMPSWAP>;
707defm FLAT_ATOMIC_FMIN : FLAT_Real_Atomics_ci <0x3f, FLAT_ATOMIC_FMIN>;
708defm FLAT_ATOMIC_FMAX : FLAT_Real_Atomics_ci <0x40, FLAT_ATOMIC_FMAX>;
709defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_Real_Atomics_ci <0x5e, FLAT_ATOMIC_FCMPSWAP_X2>;
710defm FLAT_ATOMIC_FMIN_X2 : FLAT_Real_Atomics_ci <0x5f, FLAT_ATOMIC_FMIN_X2>;
711defm FLAT_ATOMIC_FMAX_X2 : FLAT_Real_Atomics_ci <0x60, FLAT_ATOMIC_FMAX_X2>;
712
713
714//===----------------------------------------------------------------------===//
715// VI
716//===----------------------------------------------------------------------===//
717
718class FLAT_Real_vi <bits<7> op, FLAT_Pseudo ps> :
719 FLAT_Real <op, ps>,
720 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.VI> {
721 let AssemblerPredicate = isVI;
722 let DecoderNamespace="VI";
723}
724
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]725multiclass FLAT_Real_AllAddr_vi<bits<7> op> {
726 def _vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(NAME)>;
727 def _SADDR_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(NAME#"_SADDR")>;
728}
729
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]730def FLAT_LOAD_UBYTE_vi : FLAT_Real_vi <0x10, FLAT_LOAD_UBYTE>;
731def FLAT_LOAD_SBYTE_vi : FLAT_Real_vi <0x11, FLAT_LOAD_SBYTE>;
732def FLAT_LOAD_USHORT_vi : FLAT_Real_vi <0x12, FLAT_LOAD_USHORT>;
733def FLAT_LOAD_SSHORT_vi : FLAT_Real_vi <0x13, FLAT_LOAD_SSHORT>;
734def FLAT_LOAD_DWORD_vi : FLAT_Real_vi <0x14, FLAT_LOAD_DWORD>;
735def FLAT_LOAD_DWORDX2_vi : FLAT_Real_vi <0x15, FLAT_LOAD_DWORDX2>;
736def FLAT_LOAD_DWORDX4_vi : FLAT_Real_vi <0x17, FLAT_LOAD_DWORDX4>;
737def FLAT_LOAD_DWORDX3_vi : FLAT_Real_vi <0x16, FLAT_LOAD_DWORDX3>;
738
739def FLAT_STORE_BYTE_vi : FLAT_Real_vi <0x18, FLAT_STORE_BYTE>;
740def FLAT_STORE_SHORT_vi : FLAT_Real_vi <0x1a, FLAT_STORE_SHORT>;
741def FLAT_STORE_DWORD_vi : FLAT_Real_vi <0x1c, FLAT_STORE_DWORD>;
742def FLAT_STORE_DWORDX2_vi : FLAT_Real_vi <0x1d, FLAT_STORE_DWORDX2>;
743def FLAT_STORE_DWORDX4_vi : FLAT_Real_vi <0x1f, FLAT_STORE_DWORDX4>;
744def FLAT_STORE_DWORDX3_vi : FLAT_Real_vi <0x1e, FLAT_STORE_DWORDX3>;
745
746multiclass FLAT_Real_Atomics_vi <bits<7> op, FLAT_Pseudo ps> {
747 def _vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr)>;
748 def _RTN_vi : FLAT_Real_vi<op, !cast<FLAT_Pseudo>(ps.PseudoInstr # "_RTN")>;
749}
750
Matt Arsenaultf65c5ac2017-07-20 17:31:56 +0000[diff] [blame^]751multiclass FLAT_Global_Real_Atomics_vi<bits<7> op> :
752 FLAT_Real_AllAddr_vi<op> {
753 def _RTN_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_RTN")>;
754 def _SADDR_RTN_vi : FLAT_Real_vi <op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN")>;
755}
756
757
Valery Pykhtin8bc65962016-09-05 11:22:51 +0000[diff] [blame]758defm FLAT_ATOMIC_SWAP : FLAT_Real_Atomics_vi <0x40, FLAT_ATOMIC_SWAP>;
759defm FLAT_ATOMIC_CMPSWAP : FLAT_Real_Atomics_vi <0x41, FLAT_ATOMIC_CMPSWAP>;
760defm FLAT_ATOMIC_ADD : FLAT_Real_Atomics_vi <0x42, FLAT_ATOMIC_ADD>;
761defm FLAT_ATOMIC_SUB : FLAT_Real_Atomics_vi <0x43, FLAT_ATOMIC_SUB>;
762defm FLAT_ATOMIC_SMIN : FLAT_Real_Atomics_vi <0x44, FLAT_ATOMIC_SMIN>;
763defm FLAT_ATOMIC_UMIN : FLAT_Real_Atomics_vi <0x45, FLAT_ATOMIC_UMIN>;
764defm FLAT_ATOMIC_SMAX : FLAT_Real_Atomics_vi <0x46, FLAT_ATOMIC_SMAX>;
765defm FLAT_ATOMIC_UMAX : FLAT_Real_Atomics_vi <0x47, FLAT_ATOMIC_UMAX>;
766defm FLAT_ATOMIC_AND : FLAT_Real_Atomics_vi <0x48, FLAT_ATOMIC_AND>;
767defm FLAT_ATOMIC_OR : FLAT_Real_Atomics_vi <0x49, FLAT_ATOMIC_OR>;
768defm FLAT_ATOMIC_XOR : FLAT_Real_Atomics_vi <0x4a, FLAT_ATOMIC_XOR>;
769defm FLAT_ATOMIC_INC : FLAT_Real_Atomics_vi <0x4b, FLAT_ATOMIC_INC>;
770defm FLAT_ATOMIC_DEC : FLAT_Real_Atomics_vi <0x4c, FLAT_ATOMIC_DEC>;
771defm FLAT_ATOMIC_SWAP_X2 : FLAT_Real_Atomics_vi <0x60, FLAT_ATOMIC_SWAP_X2>;
772defm FLAT_ATOMIC_CMPSWAP_X2 : FLAT_Real_Atomics_vi <0x61, FLAT_ATOMIC_CMPSWAP_X2>;
773defm FLAT_ATOMIC_ADD_X2 : FLAT_Real_Atomics_vi <0x62, FLAT_ATOMIC_ADD_X2>;
774defm FLAT_ATOMIC_SUB_X2 : FLAT_Real_Atomics_vi <0x63, FLAT_ATOMIC_SUB_X2>;
775defm FLAT_ATOMIC_SMIN_X2 : FLAT_Real_Atomics_vi <0x64, FLAT_ATOMIC_SMIN_X2>;
776defm FLAT_ATOMIC_UMIN_X2 : FLAT_Real_Atomics_vi <0x65, FLAT_ATOMIC_UMIN_X2>;
777defm FLAT_ATOMIC_SMAX_X2 : FLAT_Real_Atomics_vi <0x66, FLAT_ATOMIC_SMAX_X2>;
778defm FLAT_ATOMIC_UMAX_X2 : FLAT_Real_Atomics_vi <0x67, FLAT_ATOMIC_UMAX_X2>;
779defm FLAT_ATOMIC_AND_X2 : FLAT_Real_Atomics_vi <0x68, FLAT_ATOMIC_AND_X2>;
780defm FLAT_ATOMIC_OR_X2 : FLAT_Real_Atomics_vi <0x69, FLAT_ATOMIC_OR_X2>;
781defm FLAT_ATOMIC_XOR_X2 : FLAT_Real_Atomics_vi <0x6a, FLAT_ATOMIC_XOR_X2>;
782defm FLAT_ATOMIC_INC_X2 : FLAT_Real_Atomics_vi <0x6b, FLAT_ATOMIC_INC_X2>;
783defm FLAT_ATOMIC_DEC_X2 : FLAT_Real_Atomics_vi <0x6c, FLAT_ATOMIC_DEC_X2>;
784
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]785defm GLOBAL_LOAD_UBYTE : FLAT_Real_AllAddr_vi <0x10>;
786defm GLOBAL_LOAD_SBYTE : FLAT_Real_AllAddr_vi <0x11>;
787defm GLOBAL_LOAD_USHORT : FLAT_Real_AllAddr_vi <0x12>;
788defm GLOBAL_LOAD_SSHORT : FLAT_Real_AllAddr_vi <0x13>;
789defm GLOBAL_LOAD_DWORD : FLAT_Real_AllAddr_vi <0x14>;
790defm GLOBAL_LOAD_DWORDX2 : FLAT_Real_AllAddr_vi <0x15>;
791defm GLOBAL_LOAD_DWORDX4 : FLAT_Real_AllAddr_vi <0x17>;
792defm GLOBAL_LOAD_DWORDX3 : FLAT_Real_AllAddr_vi <0x16>;
Matt Arsenault9698f1c2017-06-20 19:54:14 +0000[diff] [blame]793
Matt Arsenault04004712017-07-20 05:17:54 +0000[diff] [blame]794defm GLOBAL_STORE_BYTE : FLAT_Real_AllAddr_vi <0x18>;
795defm GLOBAL_STORE_SHORT : FLAT_Real_AllAddr_vi <0x1a>;
796defm GLOBAL_STORE_DWORD : FLAT_Real_AllAddr_vi <0x1c>;
797defm GLOBAL_STORE_DWORDX2 : FLAT_Real_AllAddr_vi <0x1d>;
798defm GLOBAL_STORE_DWORDX4 : FLAT_Real_AllAddr_vi <0x1f>;
799defm GLOBAL_STORE_DWORDX3 : FLAT_Real_AllAddr_vi <0x1e>;
Matt Arsenaultf65c5ac2017-07-20 17:31:56 +0000[diff] [blame^]800
801defm GLOBAL_ATOMIC_SWAP : FLAT_Global_Real_Atomics_vi <0x40>;
802defm GLOBAL_ATOMIC_CMPSWAP : FLAT_Global_Real_Atomics_vi <0x41>;
803defm GLOBAL_ATOMIC_ADD : FLAT_Global_Real_Atomics_vi <0x42>;
804defm GLOBAL_ATOMIC_SUB : FLAT_Global_Real_Atomics_vi <0x43>;
805defm GLOBAL_ATOMIC_SMIN : FLAT_Global_Real_Atomics_vi <0x44>;
806defm GLOBAL_ATOMIC_UMIN : FLAT_Global_Real_Atomics_vi <0x45>;
807defm GLOBAL_ATOMIC_SMAX : FLAT_Global_Real_Atomics_vi <0x46>;
808defm GLOBAL_ATOMIC_UMAX : FLAT_Global_Real_Atomics_vi <0x47>;
809defm GLOBAL_ATOMIC_AND : FLAT_Global_Real_Atomics_vi <0x48>;
810defm GLOBAL_ATOMIC_OR : FLAT_Global_Real_Atomics_vi <0x49>;
811defm GLOBAL_ATOMIC_XOR : FLAT_Global_Real_Atomics_vi <0x4a>;
812defm GLOBAL_ATOMIC_INC : FLAT_Global_Real_Atomics_vi <0x4b>;
813defm GLOBAL_ATOMIC_DEC : FLAT_Global_Real_Atomics_vi <0x4c>;
814defm GLOBAL_ATOMIC_SWAP_X2 : FLAT_Global_Real_Atomics_vi <0x60>;
815defm GLOBAL_ATOMIC_CMPSWAP_X2 : FLAT_Global_Real_Atomics_vi <0x61>;
816defm GLOBAL_ATOMIC_ADD_X2 : FLAT_Global_Real_Atomics_vi <0x62>;
817defm GLOBAL_ATOMIC_SUB_X2 : FLAT_Global_Real_Atomics_vi <0x63>;
818defm GLOBAL_ATOMIC_SMIN_X2 : FLAT_Global_Real_Atomics_vi <0x64>;
819defm GLOBAL_ATOMIC_UMIN_X2 : FLAT_Global_Real_Atomics_vi <0x65>;
820defm GLOBAL_ATOMIC_SMAX_X2 : FLAT_Global_Real_Atomics_vi <0x66>;
821defm GLOBAL_ATOMIC_UMAX_X2 : FLAT_Global_Real_Atomics_vi <0x67>;
822defm GLOBAL_ATOMIC_AND_X2 : FLAT_Global_Real_Atomics_vi <0x68>;
823defm GLOBAL_ATOMIC_OR_X2 : FLAT_Global_Real_Atomics_vi <0x69>;
824defm GLOBAL_ATOMIC_XOR_X2 : FLAT_Global_Real_Atomics_vi <0x6a>;
825defm GLOBAL_ATOMIC_INC_X2 : FLAT_Global_Real_Atomics_vi <0x6b>;
826defm GLOBAL_ATOMIC_DEC_X2 : FLAT_Global_Real_Atomics_vi <0x6c>;