Quentin Colombet | b4e7118 | 2016-12-22 21:56:19 +0000 | [diff] [blame] | 1 | //===- llvm/CodeGen/GlobalISel/Utils.cpp -------------------------*- C++ -*-==// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | /// \file This file implements the utility functions used by the GlobalISel |
| 10 | /// pipeline. |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | |
| 13 | #include "llvm/CodeGen/GlobalISel/Utils.h" |
Ahmed Bougacha | ae9dade | 2017-02-23 21:05:42 +0000 | [diff] [blame] | 14 | #include "llvm/ADT/Twine.h" |
Quentin Colombet | b4e7118 | 2016-12-22 21:56:19 +0000 | [diff] [blame] | 15 | #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" |
| 16 | #include "llvm/CodeGen/MachineInstr.h" |
| 17 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Ahmed Bougacha | ae9dade | 2017-02-23 21:05:42 +0000 | [diff] [blame] | 18 | #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" |
Quentin Colombet | b4e7118 | 2016-12-22 21:56:19 +0000 | [diff] [blame] | 19 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Ahmed Bougacha | ae9dade | 2017-02-23 21:05:42 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/TargetPassConfig.h" |
Quentin Colombet | b4e7118 | 2016-12-22 21:56:19 +0000 | [diff] [blame] | 21 | #include "llvm/Target/TargetInstrInfo.h" |
| 22 | #include "llvm/Target/TargetRegisterInfo.h" |
| 23 | |
| 24 | #define DEBUG_TYPE "globalisel-utils" |
| 25 | |
| 26 | using namespace llvm; |
| 27 | |
| 28 | unsigned llvm::constrainOperandRegClass( |
| 29 | const MachineFunction &MF, const TargetRegisterInfo &TRI, |
| 30 | MachineRegisterInfo &MRI, const TargetInstrInfo &TII, |
| 31 | const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, |
| 32 | unsigned Reg, unsigned OpIdx) { |
| 33 | // Assume physical registers are properly constrained. |
| 34 | assert(TargetRegisterInfo::isVirtualRegister(Reg) && |
| 35 | "PhysReg not implemented"); |
| 36 | |
| 37 | const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); |
| 38 | |
| 39 | if (!RBI.constrainGenericRegister(Reg, *RegClass, MRI)) { |
| 40 | unsigned NewReg = MRI.createVirtualRegister(RegClass); |
| 41 | BuildMI(*InsertPt.getParent(), InsertPt, InsertPt.getDebugLoc(), |
| 42 | TII.get(TargetOpcode::COPY), NewReg) |
| 43 | .addReg(Reg); |
| 44 | return NewReg; |
| 45 | } |
| 46 | |
| 47 | return Reg; |
| 48 | } |
Ahmed Bougacha | ae9dade | 2017-02-23 21:05:42 +0000 | [diff] [blame] | 49 | |
| 50 | void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, |
| 51 | MachineOptimizationRemarkEmitter &MORE, |
| 52 | MachineOptimizationRemarkMissed &R) { |
| 53 | MF.getProperties().set(MachineFunctionProperties::Property::FailedISel); |
| 54 | |
| 55 | // Print the function name explicitly if we don't have a debug location (which |
| 56 | // makes the diagnostic less useful) or if we're going to emit a raw error. |
| 57 | if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled()) |
| 58 | R << (" (in function: " + MF.getName() + ")").str(); |
| 59 | |
| 60 | if (TPC.isGlobalISelAbortEnabled()) |
| 61 | report_fatal_error(R.getMsg()); |
| 62 | else |
| 63 | MORE.emit(R); |
| 64 | } |
| 65 | |
| 66 | void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC, |
| 67 | MachineOptimizationRemarkEmitter &MORE, |
| 68 | const char *PassName, StringRef Msg, |
| 69 | const MachineInstr &MI) { |
| 70 | MachineOptimizationRemarkMissed R(PassName, "GISelFailure: ", |
| 71 | MI.getDebugLoc(), MI.getParent()); |
| 72 | R << Msg << ": " << ore::MNV("Inst", MI); |
| 73 | reportGISelFailure(MF, TPC, MORE, R); |
| 74 | } |