blob: 9b1e52770ce423f541fbc8fcd73cfcb1cc049ab9 [file] [log] [blame]
Tim Northovere3d42362013-02-01 11:40:47 +00001; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
Tim Northovere0e3aef2013-01-31 12:12:40 +00002
3@var32 = global i32 0
4@var64 = global i64 0
5
6define void @test_zr() {
Stephen Linf799e3f2013-07-13 20:38:47 +00007; CHECK-LABEL: test_zr:
Tim Northovere0e3aef2013-01-31 12:12:40 +00008
9 store i32 0, i32* @var32
10; CHECK: str wzr, [{{x[0-9]+}}, #:lo12:var32]
11 store i64 0, i64* @var64
12; CHECK: str xzr, [{{x[0-9]+}}, #:lo12:var64]
13
14 ret void
15; CHECK: ret
16}
17
18define void @test_sp(i32 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +000019; CHECK-LABEL: test_sp:
Tim Northovere0e3aef2013-01-31 12:12:40 +000020
21; Important correctness point here is that LLVM doesn't try to use xzr
22; as an addressing register: "str w0, [xzr]" is not a valid A64
23; instruction (0b11111 in the Rn field would mean "sp").
24 %addr = getelementptr i32* null, i64 0
25 store i32 %val, i32* %addr
26; CHECK: mov x[[NULL:[0-9]+]], xzr
27; CHECK: str {{w[0-9]+}}, [x[[NULL]]]
28
29 ret void
30; CHECK: ret
Stephen Linf799e3f2013-07-13 20:38:47 +000031}