| Tim Northover | f79c3a5 | 2013-08-20 08:57:11 +0000 | [diff] [blame^] | 1 | ; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=swift %s -o - | FileCheck %s |
| 2 | ; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEONFP %s |
| 3 | ; RUN: llc -mtriple=armv7 -mattr=-neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEON %s |
| 4 | |
| 5 | define arm_aapcs_vfpcc float @test_vmov_f32() { |
| 6 | ; CHECK-LABEL: test_vmov_f32: |
| 7 | ; CHECK: vmov.f32 d0, #1.0 |
| 8 | |
| 9 | ; CHECK-NONEONFP: vmov.f32 s0, #1.0 |
| 10 | ret float 1.0 |
| 11 | } |
| 12 | |
| 13 | define arm_aapcs_vfpcc float @test_vmov_imm() { |
| 14 | ; CHECK-LABEL: test_vmov_imm: |
| 15 | ; CHECK: vmov.i32 d0, #0 |
| 16 | |
| 17 | ; CHECK-NONEON-LABEL: test_vmov_imm: |
| 18 | ; CHECK_NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} |
| 19 | ret float 0.0 |
| 20 | } |
| 21 | |
| 22 | define arm_aapcs_vfpcc float @test_vmvn_imm() { |
| 23 | ; CHECK-LABEL: test_vmvn_imm: |
| 24 | ; CHECK: vmvn.i32 d0, #0xb0000000 |
| 25 | |
| 26 | ; CHECK-NONEON-LABEL: test_vmvn_imm: |
| 27 | ; CHECK_NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} |
| 28 | ret float 8589934080.0 |
| 29 | } |
| 30 | |
| 31 | define arm_aapcs_vfpcc double @test_vmov_f64() { |
| 32 | ; CHECK-LABEL: test_vmov_f64: |
| 33 | ; CHECK: vmov.f64 d0, #1.0 |
| 34 | |
| 35 | ; CHECK-NONEON-LABEL: test_vmov_f64: |
| 36 | ; CHECK_NONEON: vmov.f64 d0, #1.0 |
| 37 | |
| 38 | ret double 1.0 |
| 39 | } |
| 40 | |
| 41 | define arm_aapcs_vfpcc double @test_vmov_double_imm() { |
| 42 | ; CHECK-LABEL: test_vmov_double_imm: |
| 43 | ; CHECK: vmov.i32 d0, #0 |
| 44 | |
| 45 | ; CHECK-NONEON-LABEL: test_vmov_double_imm: |
| 46 | ; CHECK_NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} |
| 47 | ret double 0.0 |
| 48 | } |
| 49 | |
| 50 | define arm_aapcs_vfpcc double @test_vmvn_double_imm() { |
| 51 | ; CHECK-LABEL: test_vmvn_double_imm: |
| 52 | ; CHECK: vmvn.i32 d0, #0xb0000000 |
| 53 | |
| 54 | ; CHECK-NONEON-LABEL: test_vmvn_double_imm: |
| 55 | ; CHECK_NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} |
| 56 | ret double 0x4fffffff4fffffff |
| 57 | } |
| 58 | |
| 59 | ; Make sure we don't ignore the high half of 64-bit values when deciding whether |
| 60 | ; a vmov/vmvn is possible. |
| 61 | define arm_aapcs_vfpcc double @test_notvmvn_double_imm() { |
| 62 | ; CHECK-LABEL: test_notvmvn_double_imm: |
| 63 | ; CHECK: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} |
| 64 | |
| 65 | ; CHECK-NONEON-LABEL: test_notvmvn_double_imm: |
| 66 | ; CHECK_NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} |
| 67 | ret double 0x4fffffffffffffff |
| 68 | } |