| Konstantin Zhuravlyov | f86e4b7 | 2016-11-13 07:01:11 +0000 | [diff] [blame^] | 1 | ; RUN: llc -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s |
| 2 | ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s |
| 3 | |
| 4 | ; GCN-LABEL: {{^}}uitofp_i16_to_f16 |
| 5 | ; GCN: buffer_load_ushort v[[A_I16:[0-9]+]] |
| 6 | ; SI: v_cvt_f32_u32_e32 v[[A_F32:[0-9]+]], v[[A_I16]] |
| 7 | ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]] |
| 8 | ; VI: v_cvt_f16_u16_e32 v[[R_F16:[0-9]+]], v[[A_I16]] |
| 9 | ; GCN: buffer_store_short v[[R_F16]] |
| 10 | ; GCN: s_endpgm |
| 11 | define void @uitofp_i16_to_f16( |
| 12 | half addrspace(1)* %r, |
| 13 | i16 addrspace(1)* %a) { |
| 14 | entry: |
| 15 | %a.val = load i16, i16 addrspace(1)* %a |
| 16 | %r.val = uitofp i16 %a.val to half |
| 17 | store half %r.val, half addrspace(1)* %r |
| 18 | ret void |
| 19 | } |
| 20 | |
| 21 | ; GCN-LABEL: {{^}}uitofp_i32_to_f16 |
| 22 | ; GCN: buffer_load_dword v[[A_I32:[0-9]+]] |
| 23 | ; GCN: v_cvt_f32_u32_e32 v[[A_I16:[0-9]+]], v[[A_I32]] |
| 24 | ; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_I16]] |
| 25 | ; GCN: buffer_store_short v[[R_F16]] |
| 26 | ; GCN: s_endpgm |
| 27 | define void @uitofp_i32_to_f16( |
| 28 | half addrspace(1)* %r, |
| 29 | i32 addrspace(1)* %a) { |
| 30 | entry: |
| 31 | %a.val = load i32, i32 addrspace(1)* %a |
| 32 | %r.val = uitofp i32 %a.val to half |
| 33 | store half %r.val, half addrspace(1)* %r |
| 34 | ret void |
| 35 | } |
| 36 | |
| 37 | ; f16 = uitofp i64 is in uint_to_fp.i64.ll |
| 38 | |
| 39 | ; GCN-LABEL: {{^}}uitofp_v2i16_to_v2f16 |
| 40 | ; GCN: buffer_load_dword v[[A_V2_I16:[0-9]+]] |
| 41 | ; SI: s_mov_b32 s[[MASK:[0-9]+]], 0xffff{{$}} |
| 42 | ; SI: v_and_b32_e32 v[[A_I16_0:[0-9]+]], s[[MASK]], v[[A_V2_I16]] |
| 43 | ; GCN: v_lshrrev_b32_e32 v[[A_I16_1:[0-9]+]], 16, v[[A_V2_I16]] |
| 44 | ; SI: v_cvt_f32_u32_e32 v[[A_F32_1:[0-9]+]], v[[A_I16_1]] |
| 45 | ; SI: v_cvt_f32_u32_e32 v[[A_F32_0:[0-9]+]], v[[A_I16_0]] |
| 46 | ; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[A_F32_1]] |
| 47 | ; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[A_F32_0]] |
| 48 | ; VI: v_cvt_f16_u16_e32 v[[R_F16_0:[0-9]+]], v[[A_V2_I16]] |
| 49 | ; VI: v_cvt_f16_u16_e32 v[[R_F16_1:[0-9]+]], v[[A_I16_1]] |
| 50 | ; VI: v_and_b32_e32 v[[R_F16_LO:[0-9]+]], 0xffff, v[[R_F16_0]] |
| 51 | ; GCN: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]] |
| 52 | ; SI: v_and_b32_e32 v[[R_F16_LO:[0-9]+]], s[[MASK]], v[[R_F16_0]] |
| 53 | ; GCN: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_LO]] |
| 54 | ; GCN: buffer_store_dword v[[R_V2_F16]] |
| 55 | ; GCN: s_endpgm |
| 56 | define void @uitofp_v2i16_to_v2f16( |
| 57 | <2 x half> addrspace(1)* %r, |
| 58 | <2 x i16> addrspace(1)* %a) { |
| 59 | entry: |
| 60 | %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a |
| 61 | %r.val = uitofp <2 x i16> %a.val to <2 x half> |
| 62 | store <2 x half> %r.val, <2 x half> addrspace(1)* %r |
| 63 | ret void |
| 64 | } |
| 65 | |
| 66 | ; GCN-LABEL: {{^}}uitofp_v2i32_to_v2f16 |
| 67 | ; GCN: buffer_load_dwordx2 |
| 68 | ; GCN: v_cvt_f32_u32_e32 |
| 69 | ; GCN: v_cvt_f32_u32_e32 |
| 70 | ; GCN: v_cvt_f16_f32_e32 |
| 71 | ; GCN: v_cvt_f16_f32_e32 |
| 72 | ; GCN-DAG: v_and_b32_e32 |
| 73 | ; GCN-DAG: v_lshlrev_b32_e32 |
| 74 | ; GCN-DAG: v_or_b32_e32 |
| 75 | ; GCN: buffer_store_dword |
| 76 | ; GCN: s_endpgm |
| 77 | define void @uitofp_v2i32_to_v2f16( |
| 78 | <2 x half> addrspace(1)* %r, |
| 79 | <2 x i32> addrspace(1)* %a) { |
| 80 | entry: |
| 81 | %a.val = load <2 x i32>, <2 x i32> addrspace(1)* %a |
| 82 | %r.val = uitofp <2 x i32> %a.val to <2 x half> |
| 83 | store <2 x half> %r.val, <2 x half> addrspace(1)* %r |
| 84 | ret void |
| 85 | } |
| 86 | |
| 87 | ; f16 = uitofp i64 is in uint_to_fp.i64.ll |