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gerrit-public.fairphone.software / toolchain / llvm-project / f8b51c5f90c60aceedef9ed185eeac58f501075a / . / llvm / test / CodeGen / PowerPC / 2006-08-15-SelectionCrash.ll
blob: 851fd90ba8e304a00b61530202aa7b3fae3b1761 [file] [log] [blame]
Ehsan Amiria538b0f2016-08-03 18:17:35 +0000[diff] [blame]1; RUN: llc -verify-machineinstrs < %s
Mehdi Aminid178f4f2015-09-16 05:34:32 +0000[diff] [blame]2; REQUIRES: default_triple
Chris Lattner75b57132006-08-15 23:45:28 +0000[diff] [blame]3
Tanya Lattner8bf97c22008-03-25 04:26:08 +0000[diff] [blame]4 %struct..0anon = type { i32 }
5 %struct.rtx_def = type { i16, i8, i8, [1 x %struct..0anon] }
Chris Lattner75b57132006-08-15 23:45:28 +0000[diff] [blame]6
Tanya Lattner8bf97c22008-03-25 04:26:08 +0000[diff] [blame]7define fastcc void @immed_double_const(i32 %i0, i32 %i1) {
Chris Lattner75b57132006-08-15 23:45:28 +0000[diff] [blame]8entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]9 %tmp1 = load i32, i32* null ; <i32> [#uses=1]
Tanya Lattner8bf97c22008-03-25 04:26:08 +0000[diff] [blame]10 switch i32 %tmp1, label %bb103 [
11 i32 1, label %bb
12 i32 3, label %bb
Chris Lattner75b57132006-08-15 23:45:28 +0000[diff] [blame]13 ]
Chris Lattner75b57132006-08-15 23:45:28 +0000[diff] [blame]14bb: ; preds = %entry, %entry
Tanya Lattner8bf97c22008-03-25 04:26:08 +0000[diff] [blame]15 %tmp14 = icmp sgt i32 0, 31 ; <i1> [#uses=1]
16 br i1 %tmp14, label %cond_next77, label %cond_next17
Chris Lattner75b57132006-08-15 23:45:28 +0000[diff] [blame]17cond_next17: ; preds = %bb
18 ret void
Chris Lattner75b57132006-08-15 23:45:28 +0000[diff] [blame]19cond_next77: ; preds = %bb
Tanya Lattner8bf97c22008-03-25 04:26:08 +0000[diff] [blame]20 %tmp79.not = icmp ne i32 %i1, 0 ; <i1> [#uses=1]
21 %tmp84 = icmp slt i32 %i0, 0 ; <i1> [#uses=2]
22 %bothcond1 = or i1 %tmp79.not, %tmp84 ; <i1> [#uses=1]
23 br i1 %bothcond1, label %bb88, label %bb99
Chris Lattner75b57132006-08-15 23:45:28 +0000[diff] [blame]24bb88: ; preds = %cond_next77
Tanya Lattner8bf97c22008-03-25 04:26:08 +0000[diff] [blame]25 %bothcond2 = and i1 false, %tmp84 ; <i1> [#uses=0]
Chris Lattner75b57132006-08-15 23:45:28 +0000[diff] [blame]26 ret void
Chris Lattner75b57132006-08-15 23:45:28 +0000[diff] [blame]27bb99: ; preds = %cond_next77
28 ret void
Chris Lattner75b57132006-08-15 23:45:28 +0000[diff] [blame]29bb103: ; preds = %entry
30 ret void
31}