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Andrea Di Biagio3a6b0922018-03-08 13:05:02 +00001//===--------------------- BackendStatistics.h ------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10///
11/// This file implements a printer class for printing generic Backend
12/// statistics related to the dispatch logic, scheduler and retire unit.
13///
14/// Example:
15/// ========
16///
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000017/// Dynamic Dispatch Stall Cycles:
18/// RAT - Register unavailable: 0
19/// RCU - Retire tokens unavailable: 0
20/// SCHEDQ - Scheduler full: 42
21/// LQ - Load queue full: 0
22/// SQ - Store queue full: 0
23/// GROUP - Static restrictions on the dispatch group: 0
24///
25///
26/// Register Alias Table:
27/// Total number of mappings created: 210
28/// Max number of mappings used: 35
29///
30///
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000031/// Dispatch Logic - number of cycles where we saw N instructions dispatched:
32/// [# dispatched], [# cycles]
33/// 0, 15 (11.5%)
34/// 5, 4 (3.1%)
35///
36/// Schedulers - number of cycles where we saw N instructions issued:
37/// [# issued], [# cycles]
38/// 0, 7 (5.4%)
39/// 1, 4 (3.1%)
40/// 2, 8 (6.2%)
41///
42/// Retire Control Unit - number of cycles where we saw N instructions retired:
43/// [# retired], [# cycles]
44/// 0, 9 (6.9%)
45/// 1, 6 (4.6%)
46/// 2, 1 (0.8%)
47/// 4, 3 (2.3%)
48///
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000049///
50/// Scheduler's queue usage:
51/// JALU01, 0/20
52/// JFPU01, 18/18
53/// JLSAGU, 0/12
54///
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000055//===----------------------------------------------------------------------===//
56
57#ifndef LLVM_TOOLS_LLVM_MCA_BACKENDSTATISTICS_H
58#define LLVM_TOOLS_LLVM_MCA_BACKENDSTATISTICS_H
59
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000060#include "Backend.h"
61#include "View.h"
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000062#include "llvm/Support/raw_ostream.h"
63#include <map>
64
65namespace mca {
66
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000067class BackendStatistics : public View {
68 // TODO: remove the dependency from Backend.
69 const Backend &B;
70
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000071 using Histogram = std::map<unsigned, unsigned>;
72 Histogram DispatchGroupSizePerCycle;
73 Histogram RetiredPerCycle;
74 Histogram IssuedPerCycle;
75
76 unsigned NumDispatched;
77 unsigned NumIssued;
78 unsigned NumRetired;
79 unsigned NumCycles;
80
81 void updateHistograms() {
82 DispatchGroupSizePerCycle[NumDispatched]++;
83 IssuedPerCycle[NumIssued]++;
84 RetiredPerCycle[NumRetired]++;
85 NumDispatched = 0;
86 NumIssued = 0;
87 NumRetired = 0;
88 }
89
90 void printRetireUnitStatistics(llvm::raw_ostream &OS) const;
91 void printDispatchUnitStatistics(llvm::raw_ostream &OS) const;
92 void printSchedulerStatistics(llvm::raw_ostream &OS) const;
93
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000094 void printDispatchStalls(llvm::raw_ostream &OS, unsigned RATStalls,
95 unsigned RCUStalls, unsigned SQStalls,
96 unsigned LDQStalls, unsigned STQStalls,
97 unsigned DGStalls) const;
98 void printRATStatistics(llvm::raw_ostream &OS, unsigned Mappings,
99 unsigned MaxUsedMappings) const;
100 void printRCUStatistics(llvm::raw_ostream &OS, const Histogram &Histogram,
101 unsigned Cycles) const;
102 void printDispatchUnitUsage(llvm::raw_ostream &OS, const Histogram &Stats,
103 unsigned Cycles) const;
104 void printIssuePerCycle(const Histogram &IssuePerCycle,
105 unsigned TotalCycles) const;
106 void printSchedulerUsage(llvm::raw_ostream &OS, const llvm::MCSchedModel &SM,
107 const llvm::ArrayRef<BufferUsageEntry> &Usage) const;
108
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000109public:
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +0000110 BackendStatistics(const Backend &backend)
Andrea Di Biagioddba3ef2018-03-10 20:52:59 +0000111 : B(backend), NumDispatched(0), NumIssued(0), NumRetired(0), NumCycles(0) {}
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000112
Clement Courbet844f22d2018-03-13 13:11:01 +0000113 void onInstructionEvent(const HWInstructionEvent &Event) override;
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000114
115 void onCycleBegin(unsigned Cycle) override { NumCycles++; }
116
117 void onCycleEnd(unsigned Cycle) override { updateHistograms(); }
118
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +0000119 void printView(llvm::raw_ostream &OS) const override {
Andrea Di Biagio53e6ade2018-03-09 12:50:42 +0000120 printDispatchStalls(OS, B.getNumRATStalls(), B.getNumRCUStalls(),
121 B.getNumSQStalls(), B.getNumLDQStalls(),
122 B.getNumSTQStalls(), B.getNumDispatchGroupStalls());
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +0000123 printRATStatistics(OS, B.getTotalRegisterMappingsCreated(),
Andrea Di Biagio53e6ade2018-03-09 12:50:42 +0000124 B.getMaxUsedRegisterMappings());
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000125 printDispatchUnitStatistics(OS);
126 printSchedulerStatistics(OS);
127 printRetireUnitStatistics(OS);
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +0000128
129 std::vector<BufferUsageEntry> Usage;
130 B.getBuffersUsage(Usage);
131 printSchedulerUsage(OS, B.getSchedModel(), Usage);
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000132 }
133};
134
135} // namespace mca
136
137#endif