| Logan Chien | a436e4c | 2013-01-30 15:48:50 +0000 | [diff] [blame] | 1 | //===-- ARMUnwindOp.h - ARM Unwind Opcodes ----------------------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines the constants for the ARM unwind opcodes and exception |
| 11 | // handling table entry kinds. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #ifndef ARM_UNWIND_OP_H |
| 16 | #define ARM_UNWIND_OP_H |
| 17 | |
| 18 | namespace llvm { |
| 19 | |
| 20 | /// ARM exception handling table entry kinds |
| 21 | enum ARMEHTEntryKind { |
| 22 | EHT_GENERIC = 0x00, |
| 23 | EHT_COMPACT = 0x80 |
| 24 | }; |
| 25 | |
| 26 | enum { |
| 27 | /// Special entry for the function never unwind |
| 28 | EXIDX_CANTUNWIND = 0x1 |
| 29 | }; |
| 30 | |
| 31 | /// ARM-defined frame unwinding opcodes |
| 32 | enum ARMUnwindOpcodes { |
| 33 | // Format: 00xxxxxx |
| 34 | // Purpose: vsp = vsp + ((x << 2) + 4) |
| 35 | UNWIND_OPCODE_INC_VSP = 0x00, |
| 36 | |
| 37 | // Format: 01xxxxxx |
| 38 | // Purpose: vsp = vsp - ((x << 2) + 4) |
| 39 | UNWIND_OPCODE_DEC_VSP = 0x40, |
| 40 | |
| 41 | // Format: 10000000 00000000 |
| 42 | // Purpose: refuse to unwind |
| 43 | UNWIND_OPCODE_REFUSE = 0x8000, |
| 44 | |
| 45 | // Format: 1000xxxx xxxxxxxx |
| 46 | // Purpose: pop r[15:12], r[11:4] |
| 47 | // Constraint: x != 0 |
| 48 | UNWIND_OPCODE_POP_REG_MASK_R4 = 0x8000, |
| 49 | |
| 50 | // Format: 1001xxxx |
| 51 | // Purpose: vsp = r[x] |
| 52 | // Constraint: x != 13 && x != 15 |
| 53 | UNWIND_OPCODE_SET_VSP = 0x90, |
| 54 | |
| 55 | // Format: 10100xxx |
| 56 | // Purpose: pop r[(4+x):4] |
| 57 | UNWIND_OPCODE_POP_REG_RANGE_R4 = 0xa0, |
| 58 | |
| 59 | // Format: 10101xxx |
| 60 | // Purpose: pop r14, r[(4+x):4] |
| 61 | UNWIND_OPCODE_POP_REG_RANGE_R4_R14 = 0xa8, |
| 62 | |
| 63 | // Format: 10110000 |
| 64 | // Purpose: finish |
| 65 | UNWIND_OPCODE_FINISH = 0xb0, |
| 66 | |
| 67 | // Format: 10110001 0000xxxx |
| 68 | // Purpose: pop r[3:0] |
| 69 | // Constraint: x != 0 |
| 70 | UNWIND_OPCODE_POP_REG_MASK = 0xb100, |
| 71 | |
| 72 | // Format: 10110010 x(uleb128) |
| 73 | // Purpose: vsp = vsp + ((x << 2) + 0x204) |
| 74 | UNWIND_OPCODE_INC_VSP_ULEB128 = 0xb2, |
| 75 | |
| 76 | // Format: 10110011 xxxxyyyy |
| 77 | // Purpose: pop d[(x+y):x] |
| 78 | UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDX = 0xb300, |
| 79 | |
| 80 | // Format: 10111xxx |
| 81 | // Purpose: pop d[(8+x):8] |
| 82 | UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDX_D8 = 0xb8, |
| 83 | |
| 84 | // Format: 11000xxx |
| 85 | // Purpose: pop wR[(10+x):10] |
| 86 | UNWIND_OPCODE_POP_WIRELESS_MMX_REG_RANGE_WR10 = 0xc0, |
| 87 | |
| 88 | // Format: 11000110 xxxxyyyy |
| 89 | // Purpose: pop wR[(x+y):x] |
| 90 | UNWIND_OPCODE_POP_WIRELESS_MMX_REG_RANGE = 0xc600, |
| 91 | |
| 92 | // Format: 11000111 0000xxxx |
| 93 | // Purpose: pop wCGR[3:0] |
| 94 | // Constraint: x != 0 |
| 95 | UNWIND_OPCODE_POP_WIRELESS_MMX_REG_MASK = 0xc700, |
| 96 | |
| 97 | // Format: 11001000 xxxxyyyy |
| 98 | // Purpose: pop d[(16+x+y):(16+x)] |
| 99 | UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD_D16 = 0xc800, |
| 100 | |
| 101 | // Format: 11001001 xxxxyyyy |
| 102 | // Purpose: pop d[(x+y):x] |
| 103 | UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD = 0xc900, |
| 104 | |
| 105 | // Format: 11010xxx |
| 106 | // Purpose: pop d[(8+x):8] |
| 107 | UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD_D8 = 0xd0 |
| 108 | }; |
| 109 | |
| 110 | } |
| 111 | |
| 112 | #endif // ARM_UNWIND_OP_H |