| Justin Holewinski | ae556d3 | 2012-05-04 20:18:50 +0000 | [diff] [blame] | 1 | //===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the niversity of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the NVPTX implementation of the TargetInstrInfo class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef NVPTXINSTRUCTIONINFO_H |
| 15 | #define NVPTXINSTRUCTIONINFO_H |
| 16 | |
| 17 | #include "NVPTX.h" |
| 18 | #include "NVPTXRegisterInfo.h" |
| 19 | #include "llvm/Target/TargetInstrInfo.h" |
| 20 | |
| 21 | #define GET_INSTRINFO_HEADER |
| 22 | #include "NVPTXGenInstrInfo.inc" |
| 23 | |
| 24 | namespace llvm { |
| 25 | |
| 26 | class NVPTXInstrInfo : public NVPTXGenInstrInfo |
| 27 | { |
| 28 | NVPTXTargetMachine &TM; |
| 29 | const NVPTXRegisterInfo RegInfo; |
| 30 | public: |
| 31 | explicit NVPTXInstrInfo(NVPTXTargetMachine &TM); |
| 32 | |
| 33 | virtual const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; } |
| 34 | |
| 35 | /* The following virtual functions are used in register allocation. |
| 36 | * They are not implemented because the existing interface and the logic |
| 37 | * at the caller side do not work for the elementized vector load and store. |
| 38 | * |
| 39 | * virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, |
| 40 | * int &FrameIndex) const; |
| 41 | * virtual unsigned isStoreToStackSlot(const MachineInstr *MI, |
| 42 | * int &FrameIndex) const; |
| 43 | * virtual void storeRegToStackSlot(MachineBasicBlock &MBB, |
| 44 | * MachineBasicBlock::iterator MBBI, |
| 45 | * unsigned SrcReg, bool isKill, int FrameIndex, |
| 46 | * const TargetRegisterClass *RC) const; |
| 47 | * virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, |
| 48 | * MachineBasicBlock::iterator MBBI, |
| 49 | * unsigned DestReg, int FrameIndex, |
| 50 | * const TargetRegisterClass *RC) const; |
| 51 | */ |
| 52 | |
| 53 | virtual void copyPhysReg(MachineBasicBlock &MBB, |
| 54 | MachineBasicBlock::iterator I, DebugLoc DL, |
| 55 | unsigned DestReg, unsigned SrcReg, |
| 56 | bool KillSrc) const ; |
| 57 | virtual bool isMoveInstr(const MachineInstr &MI, |
| 58 | unsigned &SrcReg, |
| 59 | unsigned &DestReg) const; |
| 60 | bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const; |
| 61 | bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const; |
| 62 | bool isReadSpecialReg(MachineInstr &MI) const; |
| 63 | |
| 64 | virtual bool CanTailMerge(const MachineInstr *MI) const ; |
| 65 | // Branch analysis. |
| 66 | virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, |
| 67 | MachineBasicBlock *&FBB, |
| 68 | SmallVectorImpl<MachineOperand> &Cond, |
| 69 | bool AllowModify) const; |
| 70 | virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; |
| 71 | virtual unsigned InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, |
| 72 | MachineBasicBlock *FBB, |
| 73 | const SmallVectorImpl<MachineOperand> &Cond, |
| 74 | DebugLoc DL) const; |
| 75 | unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const { |
| 76 | return MI.getOperand(2).getImm(); |
| 77 | } |
| 78 | |
| 79 | }; |
| 80 | |
| 81 | } // namespace llvm |
| 82 | |
| 83 | #endif |