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gerrit-public.fairphone.software / toolchain / llvm-project / f913fd6eb0c228041b77a645d76993760d3b1421 / . / clang / test / CodeGenOpenCL / atomic-ops-libcall.cl
blob: a6f7e14f29c3c9b79e56d4db6e3144a778f7f051 [file] [log] [blame]
Yaxun Liu99d56d22017-08-15 16:30:31 +0000[diff] [blame]1// RUN: %clang_cc1 < %s -cl-std=CL2.0 -triple spir64 -emit-llvm | FileCheck -check-prefix=SPIR %s
2// RUN: %clang_cc1 < %s -cl-std=CL2.0 -triple armv5e-none-linux-gnueabi -emit-llvm | FileCheck -check-prefix=ARM %s
3typedef enum memory_order {
4 memory_order_relaxed = __ATOMIC_RELAXED,
5 memory_order_acquire = __ATOMIC_ACQUIRE,
6 memory_order_release = __ATOMIC_RELEASE,
7 memory_order_acq_rel = __ATOMIC_ACQ_REL,
8 memory_order_seq_cst = __ATOMIC_SEQ_CST
9} memory_order;
10
11typedef enum memory_scope {
12 memory_scope_work_item = __OPENCL_MEMORY_SCOPE_WORK_ITEM,
13 memory_scope_work_group = __OPENCL_MEMORY_SCOPE_WORK_GROUP,
14 memory_scope_device = __OPENCL_MEMORY_SCOPE_DEVICE,
15 memory_scope_all_svm_devices = __OPENCL_MEMORY_SCOPE_ALL_SVM_DEVICES,
16#if defined(cl_intel_subgroups) || defined(cl_khr_subgroups)
17 memory_scope_sub_group = __OPENCL_MEMORY_SCOPE_SUB_GROUP
18#endif
19} memory_scope;
Yaxun Liu39195062017-08-04 18:16:31 +0000[diff] [blame]20
Yaxun Liu1f33d8e2017-09-13 18:56:25 +0000[diff] [blame]21void f(atomic_int *i, global atomic_int *gi, local atomic_int *li, private atomic_int *pi, atomic_uint *ui, int cmp, int order, int scope) {
Yaxun Liu39195062017-08-04 18:16:31 +0000[diff] [blame]22 int x;
23 // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_load_4(i8 addrspace(4)* {{%[0-9]+}}, i32 5, i32 1)
24 // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_load_4(i8* {{%[0-9]+}}, i32 5, i32 1)
25 x = __opencl_atomic_load(i, memory_order_seq_cst, memory_scope_work_group);
Yaxun Liu1f33d8e2017-09-13 18:56:25 +0000[diff] [blame]26
Yaxun Liu39195062017-08-04 18:16:31 +0000[diff] [blame]27 // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1)
28 // ARM: call void @__opencl_atomic_store_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1)
29 __opencl_atomic_store(i, 1, memory_order_seq_cst, memory_scope_work_group);
Yaxun Liu1f33d8e2017-09-13 18:56:25 +0000[diff] [blame]30
31 // SPIR: %[[GP:[0-9]+]] = addrspacecast i8 addrspace(1)* {{%[0-9]+}} to i8 addrspace(4)*
32 // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* %[[GP]], i32 {{%[0-9]+}}, i32 5, i32 1)
33 // ARM: call void @__opencl_atomic_store_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1)
34 __opencl_atomic_store(gi, 1, memory_order_seq_cst, memory_scope_work_group);
35
36 // SPIR: %[[GP:[0-9]+]] = addrspacecast i8 addrspace(3)* {{%[0-9]+}} to i8 addrspace(4)*
37 // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* %[[GP]], i32 {{%[0-9]+}}, i32 5, i32 1)
38 // ARM: call void @__opencl_atomic_store_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1)
39 __opencl_atomic_store(li, 1, memory_order_seq_cst, memory_scope_work_group);
40
41 // SPIR: %[[GP:[0-9]+]] = addrspacecast i8* {{%[0-9]+}} to i8 addrspace(4)*
42 // SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* %[[GP]], i32 {{%[0-9]+}}, i32 5, i32 1)
43 // ARM: call void @__opencl_atomic_store_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1)
44 __opencl_atomic_store(pi, 1, memory_order_seq_cst, memory_scope_work_group);
45
Yaxun Liu39195062017-08-04 18:16:31 +0000[diff] [blame]46 // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_add_4(i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1)
47 // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_add_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1)
48 x = __opencl_atomic_fetch_add(i, 3, memory_order_seq_cst, memory_scope_work_group);
Yaxun Liu1f33d8e2017-09-13 18:56:25 +0000[diff] [blame]49
Yaxun Liu39195062017-08-04 18:16:31 +0000[diff] [blame]50 // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_min_4(i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1)
51 // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_min_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1)
52 x = __opencl_atomic_fetch_min(i, 3, memory_order_seq_cst, memory_scope_work_group);
Yaxun Liu1f33d8e2017-09-13 18:56:25 +0000[diff] [blame]53
Yaxun Liu39195062017-08-04 18:16:31 +0000[diff] [blame]54 // SPIR: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_umin_4(i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1)
55 // ARM: {{%[^ ]*}} = call i32 @__opencl_atomic_fetch_umin_4(i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 1)
56 x = __opencl_atomic_fetch_min(ui, 3, memory_order_seq_cst, memory_scope_work_group);
Yaxun Liu1f33d8e2017-09-13 18:56:25 +0000[diff] [blame]57
Yaxun Liu39195062017-08-04 18:16:31 +0000[diff] [blame]58 // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 1)
59 // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 1)
60 x = __opencl_atomic_compare_exchange_strong(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_work_group);
Yaxun Liu1f33d8e2017-09-13 18:56:25 +0000[diff] [blame]61
Yaxun Liu39195062017-08-04 18:16:31 +0000[diff] [blame]62 // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 1)
63 // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 1)
64 x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_work_group);
Yaxun Liu1f33d8e2017-09-13 18:56:25 +0000[diff] [blame]65
Yaxun Liu39195062017-08-04 18:16:31 +0000[diff] [blame]66 // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 2)
67 // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 2)
68 x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_device);
Yaxun Liu1f33d8e2017-09-13 18:56:25 +0000[diff] [blame]69
Yaxun Liu39195062017-08-04 18:16:31 +0000[diff] [blame]70 // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 3)
71 // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 3)
72 x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_all_svm_devices);
Yaxun Liu1f33d8e2017-09-13 18:56:25 +0000[diff] [blame]73
Yaxun Liu39195062017-08-04 18:16:31 +0000[diff] [blame]74#ifdef cl_khr_subgroups
75 // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 5, i32 5, i32 4)
76 x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_sub_group);
77#endif
Yaxun Liu1f33d8e2017-09-13 18:56:25 +0000[diff] [blame]78
Yaxun Liu30d652a2017-08-15 16:02:49 +0000[diff] [blame]79 // SPIR: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8 addrspace(4)* {{%[0-9]+}}, i8 addrspace(4)* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}})
80 // ARM: {{%[^ ]*}} = call zeroext i1 @__opencl_atomic_compare_exchange_4(i8* {{%[0-9]+}}, i8* {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 %{{.*}}, i32 %{{.*}}, i32 %{{.*}})
81 x = __opencl_atomic_compare_exchange_weak(i, &cmp, 1, order, order, scope);
Yaxun Liu39195062017-08-04 18:16:31 +0000[diff] [blame]82}