blob: 09750da4cb8c72fc59f8a3cc1e4575687ecde206 [file] [log] [blame]
Matt Arsenaultd0799df2016-01-30 05:10:59 +00001; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefix=NOHSA -check-prefix=ALL %s
Matt Arsenault39319482015-11-06 18:01:57 +00002
3declare i32 @llvm.r600.read.tgid.x() #0
4declare i32 @llvm.r600.read.tgid.y() #0
5declare i32 @llvm.r600.read.tgid.z() #0
6
7declare i32 @llvm.r600.read.tidig.x() #0
8declare i32 @llvm.r600.read.tidig.y() #0
9declare i32 @llvm.r600.read.tidig.z() #0
10
11declare i32 @llvm.r600.read.local.size.x() #0
12declare i32 @llvm.r600.read.local.size.y() #0
13declare i32 @llvm.r600.read.local.size.z() #0
14
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000015; ALL: define amdgpu_kernel void @use_tgid_x(i32 addrspace(1)* %ptr) #1 {
16define amdgpu_kernel void @use_tgid_x(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +000017 %val = call i32 @llvm.r600.read.tgid.x()
18 store i32 %val, i32 addrspace(1)* %ptr
19 ret void
20}
21
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000022; ALL: define amdgpu_kernel void @use_tgid_y(i32 addrspace(1)* %ptr) #2 {
23define amdgpu_kernel void @use_tgid_y(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +000024 %val = call i32 @llvm.r600.read.tgid.y()
25 store i32 %val, i32 addrspace(1)* %ptr
26 ret void
27}
28
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000029; ALL: define amdgpu_kernel void @multi_use_tgid_y(i32 addrspace(1)* %ptr) #2 {
30define amdgpu_kernel void @multi_use_tgid_y(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +000031 %val0 = call i32 @llvm.r600.read.tgid.y()
32 store volatile i32 %val0, i32 addrspace(1)* %ptr
33 %val1 = call i32 @llvm.r600.read.tgid.y()
34 store volatile i32 %val1, i32 addrspace(1)* %ptr
35 ret void
36}
37
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000038; ALL: define amdgpu_kernel void @use_tgid_x_y(i32 addrspace(1)* %ptr) #2 {
39define amdgpu_kernel void @use_tgid_x_y(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +000040 %val0 = call i32 @llvm.r600.read.tgid.x()
41 %val1 = call i32 @llvm.r600.read.tgid.y()
42 store volatile i32 %val0, i32 addrspace(1)* %ptr
43 store volatile i32 %val1, i32 addrspace(1)* %ptr
44 ret void
45}
46
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000047; ALL: define amdgpu_kernel void @use_tgid_z(i32 addrspace(1)* %ptr) #3 {
48define amdgpu_kernel void @use_tgid_z(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +000049 %val = call i32 @llvm.r600.read.tgid.z()
50 store i32 %val, i32 addrspace(1)* %ptr
51 ret void
52}
53
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000054; ALL: define amdgpu_kernel void @use_tgid_x_z(i32 addrspace(1)* %ptr) #3 {
55define amdgpu_kernel void @use_tgid_x_z(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +000056 %val0 = call i32 @llvm.r600.read.tgid.x()
57 %val1 = call i32 @llvm.r600.read.tgid.z()
58 store volatile i32 %val0, i32 addrspace(1)* %ptr
59 store volatile i32 %val1, i32 addrspace(1)* %ptr
60 ret void
61}
62
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000063; ALL: define amdgpu_kernel void @use_tgid_y_z(i32 addrspace(1)* %ptr) #4 {
64define amdgpu_kernel void @use_tgid_y_z(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +000065 %val0 = call i32 @llvm.r600.read.tgid.y()
66 %val1 = call i32 @llvm.r600.read.tgid.z()
67 store volatile i32 %val0, i32 addrspace(1)* %ptr
68 store volatile i32 %val1, i32 addrspace(1)* %ptr
69 ret void
70}
71
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000072; ALL: define amdgpu_kernel void @use_tgid_x_y_z(i32 addrspace(1)* %ptr) #4 {
73define amdgpu_kernel void @use_tgid_x_y_z(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +000074 %val0 = call i32 @llvm.r600.read.tgid.x()
75 %val1 = call i32 @llvm.r600.read.tgid.y()
76 %val2 = call i32 @llvm.r600.read.tgid.z()
77 store volatile i32 %val0, i32 addrspace(1)* %ptr
78 store volatile i32 %val1, i32 addrspace(1)* %ptr
79 store volatile i32 %val2, i32 addrspace(1)* %ptr
80 ret void
81}
82
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000083; ALL: define amdgpu_kernel void @use_tidig_x(i32 addrspace(1)* %ptr) #1 {
84define amdgpu_kernel void @use_tidig_x(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +000085 %val = call i32 @llvm.r600.read.tidig.x()
86 store i32 %val, i32 addrspace(1)* %ptr
87 ret void
88}
89
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000090; ALL: define amdgpu_kernel void @use_tidig_y(i32 addrspace(1)* %ptr) #5 {
91define amdgpu_kernel void @use_tidig_y(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +000092 %val = call i32 @llvm.r600.read.tidig.y()
93 store i32 %val, i32 addrspace(1)* %ptr
94 ret void
95}
96
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000097; ALL: define amdgpu_kernel void @use_tidig_z(i32 addrspace(1)* %ptr) #6 {
98define amdgpu_kernel void @use_tidig_z(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +000099 %val = call i32 @llvm.r600.read.tidig.z()
100 store i32 %val, i32 addrspace(1)* %ptr
101 ret void
102}
103
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000104; ALL: define amdgpu_kernel void @use_tidig_x_tgid_x(i32 addrspace(1)* %ptr) #1 {
105define amdgpu_kernel void @use_tidig_x_tgid_x(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +0000106 %val0 = call i32 @llvm.r600.read.tidig.x()
107 %val1 = call i32 @llvm.r600.read.tgid.x()
108 store volatile i32 %val0, i32 addrspace(1)* %ptr
109 store volatile i32 %val1, i32 addrspace(1)* %ptr
110 ret void
111}
112
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000113; ALL: define amdgpu_kernel void @use_tidig_y_tgid_y(i32 addrspace(1)* %ptr) #7 {
114define amdgpu_kernel void @use_tidig_y_tgid_y(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +0000115 %val0 = call i32 @llvm.r600.read.tidig.y()
116 %val1 = call i32 @llvm.r600.read.tgid.y()
117 store volatile i32 %val0, i32 addrspace(1)* %ptr
118 store volatile i32 %val1, i32 addrspace(1)* %ptr
119 ret void
120}
121
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000122; ALL: define amdgpu_kernel void @use_tidig_x_y_z(i32 addrspace(1)* %ptr) #8 {
123define amdgpu_kernel void @use_tidig_x_y_z(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +0000124 %val0 = call i32 @llvm.r600.read.tidig.x()
125 %val1 = call i32 @llvm.r600.read.tidig.y()
126 %val2 = call i32 @llvm.r600.read.tidig.z()
127 store volatile i32 %val0, i32 addrspace(1)* %ptr
128 store volatile i32 %val1, i32 addrspace(1)* %ptr
129 store volatile i32 %val2, i32 addrspace(1)* %ptr
130 ret void
131}
132
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000133; ALL: define amdgpu_kernel void @use_all_workitems(i32 addrspace(1)* %ptr) #9 {
134define amdgpu_kernel void @use_all_workitems(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +0000135 %val0 = call i32 @llvm.r600.read.tidig.x()
136 %val1 = call i32 @llvm.r600.read.tidig.y()
137 %val2 = call i32 @llvm.r600.read.tidig.z()
138 %val3 = call i32 @llvm.r600.read.tgid.x()
139 %val4 = call i32 @llvm.r600.read.tgid.y()
140 %val5 = call i32 @llvm.r600.read.tgid.z()
141 store volatile i32 %val0, i32 addrspace(1)* %ptr
142 store volatile i32 %val1, i32 addrspace(1)* %ptr
143 store volatile i32 %val2, i32 addrspace(1)* %ptr
144 store volatile i32 %val3, i32 addrspace(1)* %ptr
145 store volatile i32 %val4, i32 addrspace(1)* %ptr
146 store volatile i32 %val5, i32 addrspace(1)* %ptr
147 ret void
148}
149
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000150; HSA: define amdgpu_kernel void @use_get_local_size_x(i32 addrspace(1)* %ptr) #10 {
151; NOHSA: define amdgpu_kernel void @use_get_local_size_x(i32 addrspace(1)* %ptr) #1 {
152define amdgpu_kernel void @use_get_local_size_x(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +0000153 %val = call i32 @llvm.r600.read.local.size.x()
154 store i32 %val, i32 addrspace(1)* %ptr
155 ret void
156}
157
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000158; HSA: define amdgpu_kernel void @use_get_local_size_y(i32 addrspace(1)* %ptr) #10 {
159; NOHSA: define amdgpu_kernel void @use_get_local_size_y(i32 addrspace(1)* %ptr) #1 {
160define amdgpu_kernel void @use_get_local_size_y(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +0000161 %val = call i32 @llvm.r600.read.local.size.y()
162 store i32 %val, i32 addrspace(1)* %ptr
163 ret void
164}
165
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000166; HSA: define amdgpu_kernel void @use_get_local_size_z(i32 addrspace(1)* %ptr) #10 {
167; NOHSA: define amdgpu_kernel void @use_get_local_size_z(i32 addrspace(1)* %ptr) #1 {
168define amdgpu_kernel void @use_get_local_size_z(i32 addrspace(1)* %ptr) #1 {
Matt Arsenault39319482015-11-06 18:01:57 +0000169 %val = call i32 @llvm.r600.read.local.size.z()
170 store i32 %val, i32 addrspace(1)* %ptr
171 ret void
172}
173
174attributes #0 = { nounwind readnone }
175attributes #1 = { nounwind }
176
177; HSA: attributes #0 = { nounwind readnone }
178; HSA: attributes #1 = { nounwind }
179; HSA: attributes #2 = { nounwind "amdgpu-work-group-id-y" }
180; HSA: attributes #3 = { nounwind "amdgpu-work-group-id-z" }
181; HSA: attributes #4 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" }
182; HSA: attributes #5 = { nounwind "amdgpu-work-item-id-y" }
183; HSA: attributes #6 = { nounwind "amdgpu-work-item-id-z" }
184; HSA: attributes #7 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-item-id-y" }
185; HSA: attributes #8 = { nounwind "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" }
186; HSA: attributes #9 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" }
187; HSA: attributes #10 = { nounwind "amdgpu-dispatch-ptr" }