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gerrit-public.fairphone.software / toolchain / llvm-project / fbb4d1e43d0db9f8d1514a0209bb01f56e49d75f / . / llvm / test / CodeGen / RISCV / interrupt-attr-nocall.ll
blob: c36a01ca3d984a02ddbceafdbbe32f4bd24ebb33 [file] [log] [blame]
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple riscv32-unknown-elf -o - %s \
3; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32
4; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f -o - %s \
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]5; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32IF
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]6; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -o - %s \
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]7; RUN: 2>&1 | FileCheck %s -check-prefix CHECK-RV32IFD
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]8;
9; TODO: Add RV64 tests when we can lower global addresses.
10
11; Checking all registers that are used are being saved.
12; This includes Caller (arguments and temps) and
13; Callee saved registers.
14;
15; extern int a, b, c;
16; __attribute__((interrupt)) void foo_no_call(void) {
17; c = a + b;
18; }
19;
20
21@a = external global i32
22@b = external global i32
23@c = external global i32
24
Alex Bradbury3966b022019-05-16 13:56:23 +0000[diff] [blame]25define void @foo_i32() nounwind #0 {
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]26; CHECK-RV32-LABEL: foo_i32:
27; CHECK-RV32: # %bb.0:
28; CHECK-RV32-NEXT: addi sp, sp, -16
29; CHECK-RV32-NEXT: sw a0, 12(sp)
30; CHECK-RV32-NEXT: sw a1, 8(sp)
31; CHECK-RV32-NEXT: lui a0, %hi(a)
32; CHECK-RV32-NEXT: lw a0, %lo(a)(a0)
33; CHECK-RV32-NEXT: lui a1, %hi(b)
34; CHECK-RV32-NEXT: lw a1, %lo(b)(a1)
35; CHECK-RV32-NEXT: add a0, a1, a0
36; CHECK-RV32-NEXT: lui a1, %hi(c)
37; CHECK-RV32-NEXT: sw a0, %lo(c)(a1)
38; CHECK-RV32-NEXT: lw a1, 8(sp)
39; CHECK-RV32-NEXT: lw a0, 12(sp)
40; CHECK-RV32-NEXT: addi sp, sp, 16
41; CHECK-RV32-NEXT: mret
42;
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]43; CHECK-RV32IF-LABEL: foo_i32:
44; CHECK-RV32IF: # %bb.0:
45; CHECK-RV32IF-NEXT: addi sp, sp, -16
46; CHECK-RV32IF-NEXT: sw a0, 12(sp)
47; CHECK-RV32IF-NEXT: sw a1, 8(sp)
48; CHECK-RV32IF-NEXT: lui a0, %hi(a)
49; CHECK-RV32IF-NEXT: lw a0, %lo(a)(a0)
50; CHECK-RV32IF-NEXT: lui a1, %hi(b)
51; CHECK-RV32IF-NEXT: lw a1, %lo(b)(a1)
52; CHECK-RV32IF-NEXT: add a0, a1, a0
53; CHECK-RV32IF-NEXT: lui a1, %hi(c)
54; CHECK-RV32IF-NEXT: sw a0, %lo(c)(a1)
55; CHECK-RV32IF-NEXT: lw a1, 8(sp)
56; CHECK-RV32IF-NEXT: lw a0, 12(sp)
57; CHECK-RV32IF-NEXT: addi sp, sp, 16
58; CHECK-RV32IF-NEXT: mret
59;
60; CHECK-RV32IFD-LABEL: foo_i32:
61; CHECK-RV32IFD: # %bb.0:
62; CHECK-RV32IFD-NEXT: addi sp, sp, -16
63; CHECK-RV32IFD-NEXT: sw a0, 12(sp)
64; CHECK-RV32IFD-NEXT: sw a1, 8(sp)
65; CHECK-RV32IFD-NEXT: lui a0, %hi(a)
66; CHECK-RV32IFD-NEXT: lw a0, %lo(a)(a0)
67; CHECK-RV32IFD-NEXT: lui a1, %hi(b)
68; CHECK-RV32IFD-NEXT: lw a1, %lo(b)(a1)
69; CHECK-RV32IFD-NEXT: add a0, a1, a0
70; CHECK-RV32IFD-NEXT: lui a1, %hi(c)
71; CHECK-RV32IFD-NEXT: sw a0, %lo(c)(a1)
72; CHECK-RV32IFD-NEXT: lw a1, 8(sp)
73; CHECK-RV32IFD-NEXT: lw a0, 12(sp)
74; CHECK-RV32IFD-NEXT: addi sp, sp, 16
75; CHECK-RV32IFD-NEXT: mret
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]76 %1 = load i32, i32* @a
77 %2 = load i32, i32* @b
78 %add = add nsw i32 %2, %1
79 store i32 %add, i32* @c
80 ret void
81}
82
83;
84; Additionally check frame pointer and return address are properly saved.
85;
86
Alex Bradbury3966b022019-05-16 13:56:23 +0000[diff] [blame]87define void @foo_fp_i32() nounwind #1 {
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]88; CHECK-RV32-LABEL: foo_fp_i32:
89; CHECK-RV32: # %bb.0:
90; CHECK-RV32-NEXT: addi sp, sp, -16
91; CHECK-RV32-NEXT: sw ra, 12(sp)
92; CHECK-RV32-NEXT: sw s0, 8(sp)
93; CHECK-RV32-NEXT: sw a0, 4(sp)
94; CHECK-RV32-NEXT: sw a1, 0(sp)
95; CHECK-RV32-NEXT: addi s0, sp, 16
96; CHECK-RV32-NEXT: lui a0, %hi(a)
97; CHECK-RV32-NEXT: lw a0, %lo(a)(a0)
98; CHECK-RV32-NEXT: lui a1, %hi(b)
99; CHECK-RV32-NEXT: lw a1, %lo(b)(a1)
100; CHECK-RV32-NEXT: add a0, a1, a0
101; CHECK-RV32-NEXT: lui a1, %hi(c)
102; CHECK-RV32-NEXT: sw a0, %lo(c)(a1)
103; CHECK-RV32-NEXT: lw a1, 0(sp)
104; CHECK-RV32-NEXT: lw a0, 4(sp)
105; CHECK-RV32-NEXT: lw s0, 8(sp)
106; CHECK-RV32-NEXT: lw ra, 12(sp)
107; CHECK-RV32-NEXT: addi sp, sp, 16
108; CHECK-RV32-NEXT: mret
109;
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]110; CHECK-RV32IF-LABEL: foo_fp_i32:
111; CHECK-RV32IF: # %bb.0:
112; CHECK-RV32IF-NEXT: addi sp, sp, -16
113; CHECK-RV32IF-NEXT: sw ra, 12(sp)
114; CHECK-RV32IF-NEXT: sw s0, 8(sp)
115; CHECK-RV32IF-NEXT: sw a0, 4(sp)
116; CHECK-RV32IF-NEXT: sw a1, 0(sp)
117; CHECK-RV32IF-NEXT: addi s0, sp, 16
118; CHECK-RV32IF-NEXT: lui a0, %hi(a)
119; CHECK-RV32IF-NEXT: lw a0, %lo(a)(a0)
120; CHECK-RV32IF-NEXT: lui a1, %hi(b)
121; CHECK-RV32IF-NEXT: lw a1, %lo(b)(a1)
122; CHECK-RV32IF-NEXT: add a0, a1, a0
123; CHECK-RV32IF-NEXT: lui a1, %hi(c)
124; CHECK-RV32IF-NEXT: sw a0, %lo(c)(a1)
125; CHECK-RV32IF-NEXT: lw a1, 0(sp)
126; CHECK-RV32IF-NEXT: lw a0, 4(sp)
127; CHECK-RV32IF-NEXT: lw s0, 8(sp)
128; CHECK-RV32IF-NEXT: lw ra, 12(sp)
129; CHECK-RV32IF-NEXT: addi sp, sp, 16
130; CHECK-RV32IF-NEXT: mret
131;
132; CHECK-RV32IFD-LABEL: foo_fp_i32:
133; CHECK-RV32IFD: # %bb.0:
134; CHECK-RV32IFD-NEXT: addi sp, sp, -16
135; CHECK-RV32IFD-NEXT: sw ra, 12(sp)
136; CHECK-RV32IFD-NEXT: sw s0, 8(sp)
137; CHECK-RV32IFD-NEXT: sw a0, 4(sp)
138; CHECK-RV32IFD-NEXT: sw a1, 0(sp)
139; CHECK-RV32IFD-NEXT: addi s0, sp, 16
140; CHECK-RV32IFD-NEXT: lui a0, %hi(a)
141; CHECK-RV32IFD-NEXT: lw a0, %lo(a)(a0)
142; CHECK-RV32IFD-NEXT: lui a1, %hi(b)
143; CHECK-RV32IFD-NEXT: lw a1, %lo(b)(a1)
144; CHECK-RV32IFD-NEXT: add a0, a1, a0
145; CHECK-RV32IFD-NEXT: lui a1, %hi(c)
146; CHECK-RV32IFD-NEXT: sw a0, %lo(c)(a1)
147; CHECK-RV32IFD-NEXT: lw a1, 0(sp)
148; CHECK-RV32IFD-NEXT: lw a0, 4(sp)
149; CHECK-RV32IFD-NEXT: lw s0, 8(sp)
150; CHECK-RV32IFD-NEXT: lw ra, 12(sp)
151; CHECK-RV32IFD-NEXT: addi sp, sp, 16
152; CHECK-RV32IFD-NEXT: mret
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]153 %1 = load i32, i32* @a
154 %2 = load i32, i32* @b
155 %add = add nsw i32 %2, %1
156 store i32 %add, i32* @c
157 ret void
158}
159
160@e = external global float
161@f = external global float
162@d = external global float
163
Alex Bradbury3966b022019-05-16 13:56:23 +0000[diff] [blame]164define void @foo_float() nounwind #0 {
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]165; CHECK-RV32-LABEL: foo_float:
166; CHECK-RV32: # %bb.0:
167; CHECK-RV32-NEXT: addi sp, sp, -64
168; CHECK-RV32-NEXT: sw ra, 60(sp)
169; CHECK-RV32-NEXT: sw t0, 56(sp)
170; CHECK-RV32-NEXT: sw t1, 52(sp)
171; CHECK-RV32-NEXT: sw t2, 48(sp)
172; CHECK-RV32-NEXT: sw a0, 44(sp)
173; CHECK-RV32-NEXT: sw a1, 40(sp)
174; CHECK-RV32-NEXT: sw a2, 36(sp)
175; CHECK-RV32-NEXT: sw a3, 32(sp)
176; CHECK-RV32-NEXT: sw a4, 28(sp)
177; CHECK-RV32-NEXT: sw a5, 24(sp)
178; CHECK-RV32-NEXT: sw a6, 20(sp)
179; CHECK-RV32-NEXT: sw a7, 16(sp)
180; CHECK-RV32-NEXT: sw t3, 12(sp)
181; CHECK-RV32-NEXT: sw t4, 8(sp)
182; CHECK-RV32-NEXT: sw t5, 4(sp)
183; CHECK-RV32-NEXT: sw t6, 0(sp)
184; CHECK-RV32-NEXT: lui a0, %hi(e)
185; CHECK-RV32-NEXT: lw a0, %lo(e)(a0)
186; CHECK-RV32-NEXT: lui a1, %hi(f)
187; CHECK-RV32-NEXT: lw a1, %lo(f)(a1)
188; CHECK-RV32-NEXT: call __addsf3
189; CHECK-RV32-NEXT: lui a1, %hi(d)
190; CHECK-RV32-NEXT: sw a0, %lo(d)(a1)
191; CHECK-RV32-NEXT: lw t6, 0(sp)
192; CHECK-RV32-NEXT: lw t5, 4(sp)
193; CHECK-RV32-NEXT: lw t4, 8(sp)
194; CHECK-RV32-NEXT: lw t3, 12(sp)
195; CHECK-RV32-NEXT: lw a7, 16(sp)
196; CHECK-RV32-NEXT: lw a6, 20(sp)
197; CHECK-RV32-NEXT: lw a5, 24(sp)
198; CHECK-RV32-NEXT: lw a4, 28(sp)
199; CHECK-RV32-NEXT: lw a3, 32(sp)
200; CHECK-RV32-NEXT: lw a2, 36(sp)
201; CHECK-RV32-NEXT: lw a1, 40(sp)
202; CHECK-RV32-NEXT: lw a0, 44(sp)
203; CHECK-RV32-NEXT: lw t2, 48(sp)
204; CHECK-RV32-NEXT: lw t1, 52(sp)
205; CHECK-RV32-NEXT: lw t0, 56(sp)
206; CHECK-RV32-NEXT: lw ra, 60(sp)
207; CHECK-RV32-NEXT: addi sp, sp, 64
208; CHECK-RV32-NEXT: mret
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]209;
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]210; CHECK-RV32IF-LABEL: foo_float:
211; CHECK-RV32IF: # %bb.0:
212; CHECK-RV32IF-NEXT: addi sp, sp, -16
213; CHECK-RV32IF-NEXT: sw a0, 12(sp)
214; CHECK-RV32IF-NEXT: fsw ft0, 8(sp)
215; CHECK-RV32IF-NEXT: fsw ft1, 4(sp)
Luis Marques2d550d12019-09-17 10:52:09 +0000[diff] [blame]216; CHECK-RV32IF-NEXT: lui a0, %hi(e)
Luis Marques3d0fbaf2019-09-17 11:15:35 +0000[diff] [blame]217; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0)
218; CHECK-RV32IF-NEXT: lui a0, %hi(f)
219; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0)
220; CHECK-RV32IF-NEXT: fadd.s ft0, ft0, ft1
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]221; CHECK-RV32IF-NEXT: lui a0, %hi(d)
222; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0)
223; CHECK-RV32IF-NEXT: flw ft1, 4(sp)
224; CHECK-RV32IF-NEXT: flw ft0, 8(sp)
225; CHECK-RV32IF-NEXT: lw a0, 12(sp)
226; CHECK-RV32IF-NEXT: addi sp, sp, 16
227; CHECK-RV32IF-NEXT: mret
228;
229; CHECK-RV32IFD-LABEL: foo_float:
230; CHECK-RV32IFD: # %bb.0:
231; CHECK-RV32IFD-NEXT: addi sp, sp, -32
232; CHECK-RV32IFD-NEXT: sw a0, 28(sp)
233; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp)
234; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp)
Luis Marques2d550d12019-09-17 10:52:09 +0000[diff] [blame]235; CHECK-RV32IFD-NEXT: lui a0, %hi(e)
Luis Marques3d0fbaf2019-09-17 11:15:35 +0000[diff] [blame]236; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0)
237; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
238; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0)
239; CHECK-RV32IFD-NEXT: fadd.s ft0, ft0, ft1
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]240; CHECK-RV32IFD-NEXT: lui a0, %hi(d)
241; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0)
242; CHECK-RV32IFD-NEXT: fld ft1, 8(sp)
243; CHECK-RV32IFD-NEXT: fld ft0, 16(sp)
244; CHECK-RV32IFD-NEXT: lw a0, 28(sp)
245; CHECK-RV32IFD-NEXT: addi sp, sp, 32
246; CHECK-RV32IFD-NEXT: mret
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]247 %1 = load float, float* @e
248 %2 = load float, float* @f
249 %add = fadd float %1, %2
250 store float %add, float* @d
251 ret void
252}
253
254;
255; Additionally check frame pointer and return address are properly saved.
256;
Alex Bradbury3966b022019-05-16 13:56:23 +0000[diff] [blame]257define void @foo_fp_float() nounwind #1 {
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]258; CHECK-RV32-LABEL: foo_fp_float:
259; CHECK-RV32: # %bb.0:
260; CHECK-RV32-NEXT: addi sp, sp, -80
261; CHECK-RV32-NEXT: sw ra, 76(sp)
262; CHECK-RV32-NEXT: sw t0, 72(sp)
263; CHECK-RV32-NEXT: sw t1, 68(sp)
264; CHECK-RV32-NEXT: sw t2, 64(sp)
265; CHECK-RV32-NEXT: sw s0, 60(sp)
266; CHECK-RV32-NEXT: sw a0, 56(sp)
267; CHECK-RV32-NEXT: sw a1, 52(sp)
268; CHECK-RV32-NEXT: sw a2, 48(sp)
269; CHECK-RV32-NEXT: sw a3, 44(sp)
270; CHECK-RV32-NEXT: sw a4, 40(sp)
271; CHECK-RV32-NEXT: sw a5, 36(sp)
272; CHECK-RV32-NEXT: sw a6, 32(sp)
273; CHECK-RV32-NEXT: sw a7, 28(sp)
274; CHECK-RV32-NEXT: sw t3, 24(sp)
275; CHECK-RV32-NEXT: sw t4, 20(sp)
276; CHECK-RV32-NEXT: sw t5, 16(sp)
277; CHECK-RV32-NEXT: sw t6, 12(sp)
278; CHECK-RV32-NEXT: addi s0, sp, 80
279; CHECK-RV32-NEXT: lui a0, %hi(e)
280; CHECK-RV32-NEXT: lw a0, %lo(e)(a0)
281; CHECK-RV32-NEXT: lui a1, %hi(f)
282; CHECK-RV32-NEXT: lw a1, %lo(f)(a1)
283; CHECK-RV32-NEXT: call __addsf3
284; CHECK-RV32-NEXT: lui a1, %hi(d)
285; CHECK-RV32-NEXT: sw a0, %lo(d)(a1)
286; CHECK-RV32-NEXT: lw t6, 12(sp)
287; CHECK-RV32-NEXT: lw t5, 16(sp)
288; CHECK-RV32-NEXT: lw t4, 20(sp)
289; CHECK-RV32-NEXT: lw t3, 24(sp)
290; CHECK-RV32-NEXT: lw a7, 28(sp)
291; CHECK-RV32-NEXT: lw a6, 32(sp)
292; CHECK-RV32-NEXT: lw a5, 36(sp)
293; CHECK-RV32-NEXT: lw a4, 40(sp)
294; CHECK-RV32-NEXT: lw a3, 44(sp)
295; CHECK-RV32-NEXT: lw a2, 48(sp)
296; CHECK-RV32-NEXT: lw a1, 52(sp)
297; CHECK-RV32-NEXT: lw a0, 56(sp)
298; CHECK-RV32-NEXT: lw s0, 60(sp)
299; CHECK-RV32-NEXT: lw t2, 64(sp)
300; CHECK-RV32-NEXT: lw t1, 68(sp)
301; CHECK-RV32-NEXT: lw t0, 72(sp)
302; CHECK-RV32-NEXT: lw ra, 76(sp)
303; CHECK-RV32-NEXT: addi sp, sp, 80
304; CHECK-RV32-NEXT: mret
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]305;
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]306; CHECK-RV32IF-LABEL: foo_fp_float:
307; CHECK-RV32IF: # %bb.0:
308; CHECK-RV32IF-NEXT: addi sp, sp, -32
309; CHECK-RV32IF-NEXT: sw ra, 28(sp)
310; CHECK-RV32IF-NEXT: sw s0, 24(sp)
311; CHECK-RV32IF-NEXT: sw a0, 20(sp)
312; CHECK-RV32IF-NEXT: fsw ft0, 16(sp)
313; CHECK-RV32IF-NEXT: fsw ft1, 12(sp)
314; CHECK-RV32IF-NEXT: addi s0, sp, 32
Luis Marques2d550d12019-09-17 10:52:09 +0000[diff] [blame]315; CHECK-RV32IF-NEXT: lui a0, %hi(e)
Luis Marques3d0fbaf2019-09-17 11:15:35 +0000[diff] [blame]316; CHECK-RV32IF-NEXT: flw ft0, %lo(e)(a0)
317; CHECK-RV32IF-NEXT: lui a0, %hi(f)
318; CHECK-RV32IF-NEXT: flw ft1, %lo(f)(a0)
319; CHECK-RV32IF-NEXT: fadd.s ft0, ft0, ft1
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]320; CHECK-RV32IF-NEXT: lui a0, %hi(d)
321; CHECK-RV32IF-NEXT: fsw ft0, %lo(d)(a0)
322; CHECK-RV32IF-NEXT: flw ft1, 12(sp)
323; CHECK-RV32IF-NEXT: flw ft0, 16(sp)
324; CHECK-RV32IF-NEXT: lw a0, 20(sp)
325; CHECK-RV32IF-NEXT: lw s0, 24(sp)
326; CHECK-RV32IF-NEXT: lw ra, 28(sp)
327; CHECK-RV32IF-NEXT: addi sp, sp, 32
328; CHECK-RV32IF-NEXT: mret
329;
330; CHECK-RV32IFD-LABEL: foo_fp_float:
331; CHECK-RV32IFD: # %bb.0:
332; CHECK-RV32IFD-NEXT: addi sp, sp, -32
333; CHECK-RV32IFD-NEXT: sw ra, 28(sp)
334; CHECK-RV32IFD-NEXT: sw s0, 24(sp)
335; CHECK-RV32IFD-NEXT: sw a0, 20(sp)
336; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp)
337; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp)
338; CHECK-RV32IFD-NEXT: addi s0, sp, 32
Luis Marques2d550d12019-09-17 10:52:09 +0000[diff] [blame]339; CHECK-RV32IFD-NEXT: lui a0, %hi(e)
Luis Marques3d0fbaf2019-09-17 11:15:35 +0000[diff] [blame]340; CHECK-RV32IFD-NEXT: flw ft0, %lo(e)(a0)
341; CHECK-RV32IFD-NEXT: lui a0, %hi(f)
342; CHECK-RV32IFD-NEXT: flw ft1, %lo(f)(a0)
343; CHECK-RV32IFD-NEXT: fadd.s ft0, ft0, ft1
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]344; CHECK-RV32IFD-NEXT: lui a0, %hi(d)
345; CHECK-RV32IFD-NEXT: fsw ft0, %lo(d)(a0)
346; CHECK-RV32IFD-NEXT: fld ft1, 0(sp)
347; CHECK-RV32IFD-NEXT: fld ft0, 8(sp)
348; CHECK-RV32IFD-NEXT: lw a0, 20(sp)
349; CHECK-RV32IFD-NEXT: lw s0, 24(sp)
350; CHECK-RV32IFD-NEXT: lw ra, 28(sp)
351; CHECK-RV32IFD-NEXT: addi sp, sp, 32
352; CHECK-RV32IFD-NEXT: mret
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]353 %1 = load float, float* @e
354 %2 = load float, float* @f
355 %add = fadd float %1, %2
356 store float %add, float* @d
357 ret void
358}
359
360@h = external global double
361@i = external global double
362@g = external global double
363
Alex Bradbury3966b022019-05-16 13:56:23 +0000[diff] [blame]364define void @foo_double() nounwind #0 {
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]365; CHECK-RV32-LABEL: foo_double:
366; CHECK-RV32: # %bb.0:
367; CHECK-RV32-NEXT: addi sp, sp, -64
368; CHECK-RV32-NEXT: sw ra, 60(sp)
369; CHECK-RV32-NEXT: sw t0, 56(sp)
370; CHECK-RV32-NEXT: sw t1, 52(sp)
371; CHECK-RV32-NEXT: sw t2, 48(sp)
372; CHECK-RV32-NEXT: sw a0, 44(sp)
373; CHECK-RV32-NEXT: sw a1, 40(sp)
374; CHECK-RV32-NEXT: sw a2, 36(sp)
375; CHECK-RV32-NEXT: sw a3, 32(sp)
376; CHECK-RV32-NEXT: sw a4, 28(sp)
377; CHECK-RV32-NEXT: sw a5, 24(sp)
378; CHECK-RV32-NEXT: sw a6, 20(sp)
379; CHECK-RV32-NEXT: sw a7, 16(sp)
380; CHECK-RV32-NEXT: sw t3, 12(sp)
381; CHECK-RV32-NEXT: sw t4, 8(sp)
382; CHECK-RV32-NEXT: sw t5, 4(sp)
383; CHECK-RV32-NEXT: sw t6, 0(sp)
384; CHECK-RV32-NEXT: lui a1, %hi(h)
385; CHECK-RV32-NEXT: lw a0, %lo(h)(a1)
386; CHECK-RV32-NEXT: addi a1, a1, %lo(h)
387; CHECK-RV32-NEXT: lw a1, 4(a1)
388; CHECK-RV32-NEXT: lui a3, %hi(i)
389; CHECK-RV32-NEXT: lw a2, %lo(i)(a3)
390; CHECK-RV32-NEXT: addi a3, a3, %lo(i)
391; CHECK-RV32-NEXT: lw a3, 4(a3)
392; CHECK-RV32-NEXT: call __adddf3
393; CHECK-RV32-NEXT: lui a2, %hi(g)
394; CHECK-RV32-NEXT: addi a3, a2, %lo(g)
395; CHECK-RV32-NEXT: sw a1, 4(a3)
396; CHECK-RV32-NEXT: sw a0, %lo(g)(a2)
397; CHECK-RV32-NEXT: lw t6, 0(sp)
398; CHECK-RV32-NEXT: lw t5, 4(sp)
399; CHECK-RV32-NEXT: lw t4, 8(sp)
400; CHECK-RV32-NEXT: lw t3, 12(sp)
401; CHECK-RV32-NEXT: lw a7, 16(sp)
402; CHECK-RV32-NEXT: lw a6, 20(sp)
403; CHECK-RV32-NEXT: lw a5, 24(sp)
404; CHECK-RV32-NEXT: lw a4, 28(sp)
405; CHECK-RV32-NEXT: lw a3, 32(sp)
406; CHECK-RV32-NEXT: lw a2, 36(sp)
407; CHECK-RV32-NEXT: lw a1, 40(sp)
408; CHECK-RV32-NEXT: lw a0, 44(sp)
409; CHECK-RV32-NEXT: lw t2, 48(sp)
410; CHECK-RV32-NEXT: lw t1, 52(sp)
411; CHECK-RV32-NEXT: lw t0, 56(sp)
412; CHECK-RV32-NEXT: lw ra, 60(sp)
413; CHECK-RV32-NEXT: addi sp, sp, 64
414; CHECK-RV32-NEXT: mret
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]415;
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]416; CHECK-RV32IF-LABEL: foo_double:
417; CHECK-RV32IF: # %bb.0:
418; CHECK-RV32IF-NEXT: addi sp, sp, -192
419; CHECK-RV32IF-NEXT: sw ra, 188(sp)
420; CHECK-RV32IF-NEXT: sw t0, 184(sp)
421; CHECK-RV32IF-NEXT: sw t1, 180(sp)
422; CHECK-RV32IF-NEXT: sw t2, 176(sp)
423; CHECK-RV32IF-NEXT: sw a0, 172(sp)
424; CHECK-RV32IF-NEXT: sw a1, 168(sp)
425; CHECK-RV32IF-NEXT: sw a2, 164(sp)
426; CHECK-RV32IF-NEXT: sw a3, 160(sp)
427; CHECK-RV32IF-NEXT: sw a4, 156(sp)
428; CHECK-RV32IF-NEXT: sw a5, 152(sp)
429; CHECK-RV32IF-NEXT: sw a6, 148(sp)
430; CHECK-RV32IF-NEXT: sw a7, 144(sp)
431; CHECK-RV32IF-NEXT: sw t3, 140(sp)
432; CHECK-RV32IF-NEXT: sw t4, 136(sp)
433; CHECK-RV32IF-NEXT: sw t5, 132(sp)
434; CHECK-RV32IF-NEXT: sw t6, 128(sp)
435; CHECK-RV32IF-NEXT: fsw ft0, 124(sp)
436; CHECK-RV32IF-NEXT: fsw ft1, 120(sp)
437; CHECK-RV32IF-NEXT: fsw ft2, 116(sp)
438; CHECK-RV32IF-NEXT: fsw ft3, 112(sp)
439; CHECK-RV32IF-NEXT: fsw ft4, 108(sp)
440; CHECK-RV32IF-NEXT: fsw ft5, 104(sp)
441; CHECK-RV32IF-NEXT: fsw ft6, 100(sp)
442; CHECK-RV32IF-NEXT: fsw ft7, 96(sp)
443; CHECK-RV32IF-NEXT: fsw fa0, 92(sp)
444; CHECK-RV32IF-NEXT: fsw fa1, 88(sp)
445; CHECK-RV32IF-NEXT: fsw fa2, 84(sp)
446; CHECK-RV32IF-NEXT: fsw fa3, 80(sp)
447; CHECK-RV32IF-NEXT: fsw fa4, 76(sp)
448; CHECK-RV32IF-NEXT: fsw fa5, 72(sp)
449; CHECK-RV32IF-NEXT: fsw fa6, 68(sp)
450; CHECK-RV32IF-NEXT: fsw fa7, 64(sp)
451; CHECK-RV32IF-NEXT: fsw ft8, 60(sp)
452; CHECK-RV32IF-NEXT: fsw ft9, 56(sp)
453; CHECK-RV32IF-NEXT: fsw ft10, 52(sp)
454; CHECK-RV32IF-NEXT: fsw ft11, 48(sp)
455; CHECK-RV32IF-NEXT: fsw fs0, 44(sp)
456; CHECK-RV32IF-NEXT: fsw fs1, 40(sp)
457; CHECK-RV32IF-NEXT: fsw fs2, 36(sp)
458; CHECK-RV32IF-NEXT: fsw fs3, 32(sp)
459; CHECK-RV32IF-NEXT: fsw fs4, 28(sp)
460; CHECK-RV32IF-NEXT: fsw fs5, 24(sp)
461; CHECK-RV32IF-NEXT: fsw fs6, 20(sp)
462; CHECK-RV32IF-NEXT: fsw fs7, 16(sp)
463; CHECK-RV32IF-NEXT: fsw fs8, 12(sp)
464; CHECK-RV32IF-NEXT: fsw fs9, 8(sp)
465; CHECK-RV32IF-NEXT: fsw fs10, 4(sp)
466; CHECK-RV32IF-NEXT: fsw fs11, 0(sp)
467; CHECK-RV32IF-NEXT: lui a1, %hi(h)
468; CHECK-RV32IF-NEXT: lw a0, %lo(h)(a1)
469; CHECK-RV32IF-NEXT: addi a1, a1, %lo(h)
470; CHECK-RV32IF-NEXT: lw a1, 4(a1)
471; CHECK-RV32IF-NEXT: lui a3, %hi(i)
472; CHECK-RV32IF-NEXT: lw a2, %lo(i)(a3)
473; CHECK-RV32IF-NEXT: addi a3, a3, %lo(i)
474; CHECK-RV32IF-NEXT: lw a3, 4(a3)
475; CHECK-RV32IF-NEXT: call __adddf3
476; CHECK-RV32IF-NEXT: lui a2, %hi(g)
477; CHECK-RV32IF-NEXT: addi a3, a2, %lo(g)
478; CHECK-RV32IF-NEXT: sw a1, 4(a3)
479; CHECK-RV32IF-NEXT: sw a0, %lo(g)(a2)
480; CHECK-RV32IF-NEXT: flw fs11, 0(sp)
481; CHECK-RV32IF-NEXT: flw fs10, 4(sp)
482; CHECK-RV32IF-NEXT: flw fs9, 8(sp)
483; CHECK-RV32IF-NEXT: flw fs8, 12(sp)
484; CHECK-RV32IF-NEXT: flw fs7, 16(sp)
485; CHECK-RV32IF-NEXT: flw fs6, 20(sp)
486; CHECK-RV32IF-NEXT: flw fs5, 24(sp)
487; CHECK-RV32IF-NEXT: flw fs4, 28(sp)
488; CHECK-RV32IF-NEXT: flw fs3, 32(sp)
489; CHECK-RV32IF-NEXT: flw fs2, 36(sp)
490; CHECK-RV32IF-NEXT: flw fs1, 40(sp)
491; CHECK-RV32IF-NEXT: flw fs0, 44(sp)
492; CHECK-RV32IF-NEXT: flw ft11, 48(sp)
493; CHECK-RV32IF-NEXT: flw ft10, 52(sp)
494; CHECK-RV32IF-NEXT: flw ft9, 56(sp)
495; CHECK-RV32IF-NEXT: flw ft8, 60(sp)
496; CHECK-RV32IF-NEXT: flw fa7, 64(sp)
497; CHECK-RV32IF-NEXT: flw fa6, 68(sp)
498; CHECK-RV32IF-NEXT: flw fa5, 72(sp)
499; CHECK-RV32IF-NEXT: flw fa4, 76(sp)
500; CHECK-RV32IF-NEXT: flw fa3, 80(sp)
501; CHECK-RV32IF-NEXT: flw fa2, 84(sp)
502; CHECK-RV32IF-NEXT: flw fa1, 88(sp)
503; CHECK-RV32IF-NEXT: flw fa0, 92(sp)
504; CHECK-RV32IF-NEXT: flw ft7, 96(sp)
505; CHECK-RV32IF-NEXT: flw ft6, 100(sp)
506; CHECK-RV32IF-NEXT: flw ft5, 104(sp)
507; CHECK-RV32IF-NEXT: flw ft4, 108(sp)
508; CHECK-RV32IF-NEXT: flw ft3, 112(sp)
509; CHECK-RV32IF-NEXT: flw ft2, 116(sp)
510; CHECK-RV32IF-NEXT: flw ft1, 120(sp)
511; CHECK-RV32IF-NEXT: flw ft0, 124(sp)
512; CHECK-RV32IF-NEXT: lw t6, 128(sp)
513; CHECK-RV32IF-NEXT: lw t5, 132(sp)
514; CHECK-RV32IF-NEXT: lw t4, 136(sp)
515; CHECK-RV32IF-NEXT: lw t3, 140(sp)
516; CHECK-RV32IF-NEXT: lw a7, 144(sp)
517; CHECK-RV32IF-NEXT: lw a6, 148(sp)
518; CHECK-RV32IF-NEXT: lw a5, 152(sp)
519; CHECK-RV32IF-NEXT: lw a4, 156(sp)
520; CHECK-RV32IF-NEXT: lw a3, 160(sp)
521; CHECK-RV32IF-NEXT: lw a2, 164(sp)
522; CHECK-RV32IF-NEXT: lw a1, 168(sp)
523; CHECK-RV32IF-NEXT: lw a0, 172(sp)
524; CHECK-RV32IF-NEXT: lw t2, 176(sp)
525; CHECK-RV32IF-NEXT: lw t1, 180(sp)
526; CHECK-RV32IF-NEXT: lw t0, 184(sp)
527; CHECK-RV32IF-NEXT: lw ra, 188(sp)
528; CHECK-RV32IF-NEXT: addi sp, sp, 192
529; CHECK-RV32IF-NEXT: mret
530;
531; CHECK-RV32IFD-LABEL: foo_double:
532; CHECK-RV32IFD: # %bb.0:
533; CHECK-RV32IFD-NEXT: addi sp, sp, -32
534; CHECK-RV32IFD-NEXT: sw a0, 28(sp)
535; CHECK-RV32IFD-NEXT: fsd ft0, 16(sp)
536; CHECK-RV32IFD-NEXT: fsd ft1, 8(sp)
Luis Marques2d550d12019-09-17 10:52:09 +0000[diff] [blame]537; CHECK-RV32IFD-NEXT: lui a0, %hi(h)
Luis Marques3d0fbaf2019-09-17 11:15:35 +0000[diff] [blame]538; CHECK-RV32IFD-NEXT: fld ft0, %lo(h)(a0)
539; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
540; CHECK-RV32IFD-NEXT: fld ft1, %lo(i)(a0)
541; CHECK-RV32IFD-NEXT: fadd.d ft0, ft0, ft1
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]542; CHECK-RV32IFD-NEXT: lui a0, %hi(g)
543; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0)
544; CHECK-RV32IFD-NEXT: fld ft1, 8(sp)
545; CHECK-RV32IFD-NEXT: fld ft0, 16(sp)
546; CHECK-RV32IFD-NEXT: lw a0, 28(sp)
547; CHECK-RV32IFD-NEXT: addi sp, sp, 32
548; CHECK-RV32IFD-NEXT: mret
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]549 %1 = load double, double* @h
550 %2 = load double, double* @i
551 %add = fadd double %1, %2
552 store double %add, double* @g
553 ret void
554}
555
556;
557; Additionally check frame pointer and return address are properly saved.
558;
Alex Bradbury3966b022019-05-16 13:56:23 +0000[diff] [blame]559define void @foo_fp_double() nounwind #1 {
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]560; CHECK-RV32-LABEL: foo_fp_double:
561; CHECK-RV32: # %bb.0:
562; CHECK-RV32-NEXT: addi sp, sp, -80
563; CHECK-RV32-NEXT: sw ra, 76(sp)
564; CHECK-RV32-NEXT: sw t0, 72(sp)
565; CHECK-RV32-NEXT: sw t1, 68(sp)
566; CHECK-RV32-NEXT: sw t2, 64(sp)
567; CHECK-RV32-NEXT: sw s0, 60(sp)
568; CHECK-RV32-NEXT: sw a0, 56(sp)
569; CHECK-RV32-NEXT: sw a1, 52(sp)
570; CHECK-RV32-NEXT: sw a2, 48(sp)
571; CHECK-RV32-NEXT: sw a3, 44(sp)
572; CHECK-RV32-NEXT: sw a4, 40(sp)
573; CHECK-RV32-NEXT: sw a5, 36(sp)
574; CHECK-RV32-NEXT: sw a6, 32(sp)
575; CHECK-RV32-NEXT: sw a7, 28(sp)
576; CHECK-RV32-NEXT: sw t3, 24(sp)
577; CHECK-RV32-NEXT: sw t4, 20(sp)
578; CHECK-RV32-NEXT: sw t5, 16(sp)
579; CHECK-RV32-NEXT: sw t6, 12(sp)
580; CHECK-RV32-NEXT: addi s0, sp, 80
581; CHECK-RV32-NEXT: lui a1, %hi(h)
582; CHECK-RV32-NEXT: lw a0, %lo(h)(a1)
583; CHECK-RV32-NEXT: addi a1, a1, %lo(h)
584; CHECK-RV32-NEXT: lw a1, 4(a1)
585; CHECK-RV32-NEXT: lui a3, %hi(i)
586; CHECK-RV32-NEXT: lw a2, %lo(i)(a3)
587; CHECK-RV32-NEXT: addi a3, a3, %lo(i)
588; CHECK-RV32-NEXT: lw a3, 4(a3)
589; CHECK-RV32-NEXT: call __adddf3
590; CHECK-RV32-NEXT: lui a2, %hi(g)
591; CHECK-RV32-NEXT: addi a3, a2, %lo(g)
592; CHECK-RV32-NEXT: sw a1, 4(a3)
593; CHECK-RV32-NEXT: sw a0, %lo(g)(a2)
594; CHECK-RV32-NEXT: lw t6, 12(sp)
595; CHECK-RV32-NEXT: lw t5, 16(sp)
596; CHECK-RV32-NEXT: lw t4, 20(sp)
597; CHECK-RV32-NEXT: lw t3, 24(sp)
598; CHECK-RV32-NEXT: lw a7, 28(sp)
599; CHECK-RV32-NEXT: lw a6, 32(sp)
600; CHECK-RV32-NEXT: lw a5, 36(sp)
601; CHECK-RV32-NEXT: lw a4, 40(sp)
602; CHECK-RV32-NEXT: lw a3, 44(sp)
603; CHECK-RV32-NEXT: lw a2, 48(sp)
604; CHECK-RV32-NEXT: lw a1, 52(sp)
605; CHECK-RV32-NEXT: lw a0, 56(sp)
606; CHECK-RV32-NEXT: lw s0, 60(sp)
607; CHECK-RV32-NEXT: lw t2, 64(sp)
608; CHECK-RV32-NEXT: lw t1, 68(sp)
609; CHECK-RV32-NEXT: lw t0, 72(sp)
610; CHECK-RV32-NEXT: lw ra, 76(sp)
611; CHECK-RV32-NEXT: addi sp, sp, 80
612; CHECK-RV32-NEXT: mret
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]613;
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]614; CHECK-RV32IF-LABEL: foo_fp_double:
615; CHECK-RV32IF: # %bb.0:
616; CHECK-RV32IF-NEXT: addi sp, sp, -208
617; CHECK-RV32IF-NEXT: sw ra, 204(sp)
618; CHECK-RV32IF-NEXT: sw t0, 200(sp)
619; CHECK-RV32IF-NEXT: sw t1, 196(sp)
620; CHECK-RV32IF-NEXT: sw t2, 192(sp)
621; CHECK-RV32IF-NEXT: sw s0, 188(sp)
622; CHECK-RV32IF-NEXT: sw a0, 184(sp)
623; CHECK-RV32IF-NEXT: sw a1, 180(sp)
624; CHECK-RV32IF-NEXT: sw a2, 176(sp)
625; CHECK-RV32IF-NEXT: sw a3, 172(sp)
626; CHECK-RV32IF-NEXT: sw a4, 168(sp)
627; CHECK-RV32IF-NEXT: sw a5, 164(sp)
628; CHECK-RV32IF-NEXT: sw a6, 160(sp)
629; CHECK-RV32IF-NEXT: sw a7, 156(sp)
630; CHECK-RV32IF-NEXT: sw t3, 152(sp)
631; CHECK-RV32IF-NEXT: sw t4, 148(sp)
632; CHECK-RV32IF-NEXT: sw t5, 144(sp)
633; CHECK-RV32IF-NEXT: sw t6, 140(sp)
634; CHECK-RV32IF-NEXT: fsw ft0, 136(sp)
635; CHECK-RV32IF-NEXT: fsw ft1, 132(sp)
636; CHECK-RV32IF-NEXT: fsw ft2, 128(sp)
637; CHECK-RV32IF-NEXT: fsw ft3, 124(sp)
638; CHECK-RV32IF-NEXT: fsw ft4, 120(sp)
639; CHECK-RV32IF-NEXT: fsw ft5, 116(sp)
640; CHECK-RV32IF-NEXT: fsw ft6, 112(sp)
641; CHECK-RV32IF-NEXT: fsw ft7, 108(sp)
642; CHECK-RV32IF-NEXT: fsw fa0, 104(sp)
643; CHECK-RV32IF-NEXT: fsw fa1, 100(sp)
644; CHECK-RV32IF-NEXT: fsw fa2, 96(sp)
645; CHECK-RV32IF-NEXT: fsw fa3, 92(sp)
646; CHECK-RV32IF-NEXT: fsw fa4, 88(sp)
647; CHECK-RV32IF-NEXT: fsw fa5, 84(sp)
648; CHECK-RV32IF-NEXT: fsw fa6, 80(sp)
649; CHECK-RV32IF-NEXT: fsw fa7, 76(sp)
650; CHECK-RV32IF-NEXT: fsw ft8, 72(sp)
651; CHECK-RV32IF-NEXT: fsw ft9, 68(sp)
652; CHECK-RV32IF-NEXT: fsw ft10, 64(sp)
653; CHECK-RV32IF-NEXT: fsw ft11, 60(sp)
654; CHECK-RV32IF-NEXT: fsw fs0, 56(sp)
655; CHECK-RV32IF-NEXT: fsw fs1, 52(sp)
656; CHECK-RV32IF-NEXT: fsw fs2, 48(sp)
657; CHECK-RV32IF-NEXT: fsw fs3, 44(sp)
658; CHECK-RV32IF-NEXT: fsw fs4, 40(sp)
659; CHECK-RV32IF-NEXT: fsw fs5, 36(sp)
660; CHECK-RV32IF-NEXT: fsw fs6, 32(sp)
661; CHECK-RV32IF-NEXT: fsw fs7, 28(sp)
662; CHECK-RV32IF-NEXT: fsw fs8, 24(sp)
663; CHECK-RV32IF-NEXT: fsw fs9, 20(sp)
664; CHECK-RV32IF-NEXT: fsw fs10, 16(sp)
665; CHECK-RV32IF-NEXT: fsw fs11, 12(sp)
666; CHECK-RV32IF-NEXT: addi s0, sp, 208
667; CHECK-RV32IF-NEXT: lui a1, %hi(h)
668; CHECK-RV32IF-NEXT: lw a0, %lo(h)(a1)
669; CHECK-RV32IF-NEXT: addi a1, a1, %lo(h)
670; CHECK-RV32IF-NEXT: lw a1, 4(a1)
671; CHECK-RV32IF-NEXT: lui a3, %hi(i)
672; CHECK-RV32IF-NEXT: lw a2, %lo(i)(a3)
673; CHECK-RV32IF-NEXT: addi a3, a3, %lo(i)
674; CHECK-RV32IF-NEXT: lw a3, 4(a3)
675; CHECK-RV32IF-NEXT: call __adddf3
676; CHECK-RV32IF-NEXT: lui a2, %hi(g)
677; CHECK-RV32IF-NEXT: addi a3, a2, %lo(g)
678; CHECK-RV32IF-NEXT: sw a1, 4(a3)
679; CHECK-RV32IF-NEXT: sw a0, %lo(g)(a2)
680; CHECK-RV32IF-NEXT: flw fs11, 12(sp)
681; CHECK-RV32IF-NEXT: flw fs10, 16(sp)
682; CHECK-RV32IF-NEXT: flw fs9, 20(sp)
683; CHECK-RV32IF-NEXT: flw fs8, 24(sp)
684; CHECK-RV32IF-NEXT: flw fs7, 28(sp)
685; CHECK-RV32IF-NEXT: flw fs6, 32(sp)
686; CHECK-RV32IF-NEXT: flw fs5, 36(sp)
687; CHECK-RV32IF-NEXT: flw fs4, 40(sp)
688; CHECK-RV32IF-NEXT: flw fs3, 44(sp)
689; CHECK-RV32IF-NEXT: flw fs2, 48(sp)
690; CHECK-RV32IF-NEXT: flw fs1, 52(sp)
691; CHECK-RV32IF-NEXT: flw fs0, 56(sp)
692; CHECK-RV32IF-NEXT: flw ft11, 60(sp)
693; CHECK-RV32IF-NEXT: flw ft10, 64(sp)
694; CHECK-RV32IF-NEXT: flw ft9, 68(sp)
695; CHECK-RV32IF-NEXT: flw ft8, 72(sp)
696; CHECK-RV32IF-NEXT: flw fa7, 76(sp)
697; CHECK-RV32IF-NEXT: flw fa6, 80(sp)
698; CHECK-RV32IF-NEXT: flw fa5, 84(sp)
699; CHECK-RV32IF-NEXT: flw fa4, 88(sp)
700; CHECK-RV32IF-NEXT: flw fa3, 92(sp)
701; CHECK-RV32IF-NEXT: flw fa2, 96(sp)
702; CHECK-RV32IF-NEXT: flw fa1, 100(sp)
703; CHECK-RV32IF-NEXT: flw fa0, 104(sp)
704; CHECK-RV32IF-NEXT: flw ft7, 108(sp)
705; CHECK-RV32IF-NEXT: flw ft6, 112(sp)
706; CHECK-RV32IF-NEXT: flw ft5, 116(sp)
707; CHECK-RV32IF-NEXT: flw ft4, 120(sp)
708; CHECK-RV32IF-NEXT: flw ft3, 124(sp)
709; CHECK-RV32IF-NEXT: flw ft2, 128(sp)
710; CHECK-RV32IF-NEXT: flw ft1, 132(sp)
711; CHECK-RV32IF-NEXT: flw ft0, 136(sp)
712; CHECK-RV32IF-NEXT: lw t6, 140(sp)
713; CHECK-RV32IF-NEXT: lw t5, 144(sp)
714; CHECK-RV32IF-NEXT: lw t4, 148(sp)
715; CHECK-RV32IF-NEXT: lw t3, 152(sp)
716; CHECK-RV32IF-NEXT: lw a7, 156(sp)
717; CHECK-RV32IF-NEXT: lw a6, 160(sp)
718; CHECK-RV32IF-NEXT: lw a5, 164(sp)
719; CHECK-RV32IF-NEXT: lw a4, 168(sp)
720; CHECK-RV32IF-NEXT: lw a3, 172(sp)
721; CHECK-RV32IF-NEXT: lw a2, 176(sp)
722; CHECK-RV32IF-NEXT: lw a1, 180(sp)
723; CHECK-RV32IF-NEXT: lw a0, 184(sp)
724; CHECK-RV32IF-NEXT: lw s0, 188(sp)
725; CHECK-RV32IF-NEXT: lw t2, 192(sp)
726; CHECK-RV32IF-NEXT: lw t1, 196(sp)
727; CHECK-RV32IF-NEXT: lw t0, 200(sp)
728; CHECK-RV32IF-NEXT: lw ra, 204(sp)
729; CHECK-RV32IF-NEXT: addi sp, sp, 208
730; CHECK-RV32IF-NEXT: mret
731;
732; CHECK-RV32IFD-LABEL: foo_fp_double:
733; CHECK-RV32IFD: # %bb.0:
734; CHECK-RV32IFD-NEXT: addi sp, sp, -32
735; CHECK-RV32IFD-NEXT: sw ra, 28(sp)
736; CHECK-RV32IFD-NEXT: sw s0, 24(sp)
737; CHECK-RV32IFD-NEXT: sw a0, 20(sp)
738; CHECK-RV32IFD-NEXT: fsd ft0, 8(sp)
739; CHECK-RV32IFD-NEXT: fsd ft1, 0(sp)
740; CHECK-RV32IFD-NEXT: addi s0, sp, 32
Luis Marques2d550d12019-09-17 10:52:09 +0000[diff] [blame]741; CHECK-RV32IFD-NEXT: lui a0, %hi(h)
Luis Marques3d0fbaf2019-09-17 11:15:35 +0000[diff] [blame]742; CHECK-RV32IFD-NEXT: fld ft0, %lo(h)(a0)
743; CHECK-RV32IFD-NEXT: lui a0, %hi(i)
744; CHECK-RV32IFD-NEXT: fld ft1, %lo(i)(a0)
745; CHECK-RV32IFD-NEXT: fadd.d ft0, ft0, ft1
Luis Marquesc2b3d522019-08-30 12:11:47 +0000[diff] [blame]746; CHECK-RV32IFD-NEXT: lui a0, %hi(g)
747; CHECK-RV32IFD-NEXT: fsd ft0, %lo(g)(a0)
748; CHECK-RV32IFD-NEXT: fld ft1, 0(sp)
749; CHECK-RV32IFD-NEXT: fld ft0, 8(sp)
750; CHECK-RV32IFD-NEXT: lw a0, 20(sp)
751; CHECK-RV32IFD-NEXT: lw s0, 24(sp)
752; CHECK-RV32IFD-NEXT: lw ra, 28(sp)
753; CHECK-RV32IFD-NEXT: addi sp, sp, 32
754; CHECK-RV32IFD-NEXT: mret
Ana Pazos2e4106b2018-07-26 17:49:43 +0000[diff] [blame]755 %1 = load double, double* @h
756 %2 = load double, double* @i
757 %add = fadd double %1, %2
758 store double %add, double* @g
759 ret void
760}
761
762attributes #0 = { "interrupt"="machine" }
Fangrui Song502a77f2019-12-24 15:52:21 -0800[diff] [blame]763attributes #1 = { "interrupt"="machine" "frame-pointer"="all" }