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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- SIMachineFunctionInfo.cpp - SI Machine Function Info -------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8/// \file
9//===----------------------------------------------------------------------===//
10
11
12#include "SIMachineFunctionInfo.h"
Tom Stellard96468902014-09-24 01:33:17 +000013#include "AMDGPUSubtarget.h"
Tom Stellardeba61072014-05-02 15:41:42 +000014#include "SIInstrInfo.h"
Tom Stellard96468902014-09-24 01:33:17 +000015#include "llvm/CodeGen/MachineInstrBuilder.h"
Tom Stellardc5cf2f02014-08-21 20:40:54 +000016#include "llvm/CodeGen/MachineFrameInfo.h"
Tom Stellardc149dc02013-11-27 21:23:35 +000017#include "llvm/CodeGen/MachineRegisterInfo.h"
Tom Stellardeba61072014-05-02 15:41:42 +000018#include "llvm/IR/Function.h"
19#include "llvm/IR/LLVMContext.h"
Tom Stellardc149dc02013-11-27 21:23:35 +000020
21#define MAX_LANES 64
Tom Stellard75aadc22012-12-11 21:25:42 +000022
23using namespace llvm;
24
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +000025
26// Pin the vtable to this file.
27void SIMachineFunctionInfo::anchor() {}
28
Tom Stellard75aadc22012-12-11 21:25:42 +000029SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
Vincent Lejeuneace6f732013-04-01 21:47:53 +000030 : AMDGPUMachineFunction(MF),
Tom Stellard96468902014-09-24 01:33:17 +000031 TIDReg(AMDGPU::NoRegister),
Matt Arsenault5b22dfa2015-11-05 05:27:10 +000032 HasSpilledSGPRs(false),
Tom Stellard42fb60e2015-01-14 15:42:31 +000033 HasSpilledVGPRs(false),
Tom Stellardc149dc02013-11-27 21:23:35 +000034 PSInputAddr(0),
Tom Stellard96468902014-09-24 01:33:17 +000035 NumUserSGPRs(0),
36 LDSWaveSpillSize(0) { }
Tom Stellardc5cf2f02014-08-21 20:40:54 +000037
38SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg(
39 MachineFunction *MF,
40 unsigned FrameIndex,
41 unsigned SubIdx) {
42 const MachineFrameInfo *FrameInfo = MF->getFrameInfo();
Eric Christopher0795a2e2015-02-19 01:10:55 +000043 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
44 MF->getSubtarget<AMDGPUSubtarget>().getRegisterInfo());
Tom Stellardc5cf2f02014-08-21 20:40:54 +000045 MachineRegisterInfo &MRI = MF->getRegInfo();
46 int64_t Offset = FrameInfo->getObjectOffset(FrameIndex);
47 Offset += SubIdx * 4;
48
49 unsigned LaneVGPRIdx = Offset / (64 * 4);
50 unsigned Lane = (Offset / 4) % 64;
51
52 struct SpilledReg Spill;
53
54 if (!LaneVGPRs.count(LaneVGPRIdx)) {
Tom Stellard42fb60e2015-01-14 15:42:31 +000055 unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
Tom Stellardc5cf2f02014-08-21 20:40:54 +000056 LaneVGPRs[LaneVGPRIdx] = LaneVGPR;
Tom Stellardc5cf2f02014-08-21 20:40:54 +000057
58 // Add this register as live-in to all blocks to avoid machine verifer
59 // complaining about use of an undefined physical register.
60 for (MachineFunction::iterator BI = MF->begin(), BE = MF->end();
61 BI != BE; ++BI) {
62 BI->addLiveIn(LaneVGPR);
63 }
64 }
65
66 Spill.VGPR = LaneVGPRs[LaneVGPRIdx];
67 Spill.Lane = Lane;
68 return Spill;
Tom Stellardc149dc02013-11-27 21:23:35 +000069}
Tom Stellard96468902014-09-24 01:33:17 +000070
71unsigned SIMachineFunctionInfo::getMaximumWorkGroupSize(
72 const MachineFunction &MF) const {
Eric Christopher0795a2e2015-02-19 01:10:55 +000073 const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
Tom Stellard96468902014-09-24 01:33:17 +000074 // FIXME: We should get this information from kernel attributes if it
75 // is available.
76 return getShaderType() == ShaderType::COMPUTE ? 256 : ST.getWavefrontSize();
77}