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gerrit-public.fairphone.software / toolchain / llvm-project / fdd4999b869347a37d076151823ad6f8772e4557 / . / llvm / test / CodeGen / WebAssembly / simd-bitcasts.ll
blob: f1437208c67c73573eb318a5d2da7a886e31db0c [file] [log] [blame]
Thomas Livelyfdd49992019-01-10 04:09:25 +0000[diff] [blame^]1; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
2; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
3; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
Thomas Lively80725802018-08-30 21:43:51 +0000[diff] [blame]4
5; Test that bitcasts between vector types are lowered to zero instructions
6
7target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
8target triple = "wasm32-unknown-unknown"
9
10; CHECK-LABEL: v16i8_to_v16i8:
11; NO-SIMD128-NOT: return $0
12; SIMD128: return $0
13define <16 x i8> @v16i8_to_v16i8(<16 x i8> %v) {
14 %res = bitcast <16 x i8> %v to <16 x i8>
15 ret <16 x i8> %res
16}
17
18; CHECK-LABEL: v16i8_to_v8i16:
19; NO-SIMD128-NOT: return $0
20; SIMD128: return $0
21define <8 x i16> @v16i8_to_v8i16(<16 x i8> %v) {
22 %res = bitcast <16 x i8> %v to <8 x i16>
23 ret <8 x i16> %res
24}
25
26; CHECK-LABEL: v16i8_to_v4i32:
27; NO-SIMD128-NOT: return $0
28; SIMD128: return $0
29define <4 x i32> @v16i8_to_v4i32(<16 x i8> %v) {
30 %res = bitcast <16 x i8> %v to <4 x i32>
31 ret <4 x i32> %res
32}
33
34; CHECK-LABEL: v16i8_to_v2i64:
35; NO-SIMD128-NOT: return $0
36; SIMD128-VM: v128.store
37; SIMD128-VM-NEXT: return{{$}}
38; SIMD128: return $0
39define <2 x i64> @v16i8_to_v2i64(<16 x i8> %v) {
40 %res = bitcast <16 x i8> %v to <2 x i64>
41 ret <2 x i64> %res
42}
43
44; CHECK-LABEL: v16i8_to_v4f32:
45; NO-SIMD128-NOT: return $0
46; SIMD128: return $0
47define <4 x float> @v16i8_to_v4f32(<16 x i8> %v) {
48 %res = bitcast <16 x i8> %v to <4 x float>
49 ret <4 x float> %res
50}
51
52; CHECK-LABEL: v16i8_to_v2f64:
53; NO-SIMD128-NOT: return $0
54; SIMD128-VM: v128.store
55; SIMD128-VM-NEXT: return{{$}}
56; SIMD128: return $0
57define <2 x double> @v16i8_to_v2f64(<16 x i8> %v) {
58 %res = bitcast <16 x i8> %v to <2 x double>
59 ret <2 x double> %res
60}
61
62; CHECK-LABEL: v8i16_to_v16i8:
63; NO-SIMD128-NOT: return $0
64; SIMD128: return $0
65define <16 x i8> @v8i16_to_v16i8(<8 x i16> %v) {
66 %res = bitcast <8 x i16> %v to <16 x i8>
67 ret <16 x i8> %res
68}
69
70; CHECK-LABEL: v8i16_to_v8i16:
71; NO-SIMD128-NOT: return $0
72; SIMD128: return $0
73define <8 x i16> @v8i16_to_v8i16(<8 x i16> %v) {
74 %res = bitcast <8 x i16> %v to <8 x i16>
75 ret <8 x i16> %res
76}
77
78; CHECK-LABEL: v8i16_to_v4i32:
79; NO-SIMD128-NOT: return $0
80; SIMD128: return $0
81define <4 x i32> @v8i16_to_v4i32(<8 x i16> %v) {
82 %res = bitcast <8 x i16> %v to <4 x i32>
83 ret <4 x i32> %res
84}
85
86; CHECK-LABEL: v8i16_to_v2i64:
87; NO-SIMD128-NOT: return $0
88; SIMD128-VM: v128.store
89; SIMD128-VM-NEXT: return{{$}}
90; SIMD128: return $0
91define <2 x i64> @v8i16_to_v2i64(<8 x i16> %v) {
92 %res = bitcast <8 x i16> %v to <2 x i64>
93 ret <2 x i64> %res
94}
95
96; CHECK-LABEL: v8i16_to_v4f32:
97; NO-SIMD128-NOT: return $0
98; SIMD128: return $0
99define <4 x float> @v8i16_to_v4f32(<8 x i16> %v) {
100 %res = bitcast <8 x i16> %v to <4 x float>
101 ret <4 x float> %res
102}
103
104; CHECK-LABEL: v8i16_to_v2f64:
105; NO-SIMD128-NOT: return $0
106; SIMD128-VM: v128.store
107; SIMD128-VM-NEXT: return{{$}}
108; SIMD128: return $0
109define <2 x double> @v8i16_to_v2f64(<8 x i16> %v) {
110 %res = bitcast <8 x i16> %v to <2 x double>
111 ret <2 x double> %res
112}
113
114; CHECK-LABEL: v4i32_to_v16i8:
115; NO-SIMD128-NOT: return $0
116; SIMD128: return $0
117define <16 x i8> @v4i32_to_v16i8(<4 x i32> %v) {
118 %res = bitcast <4 x i32> %v to <16 x i8>
119 ret <16 x i8> %res
120}
121
122; CHECK-LABEL: v4i32_to_v8i16:
123; NO-SIMD128-NOT: return $0
124; SIMD128: return $0
125define <8 x i16> @v4i32_to_v8i16(<4 x i32> %v) {
126 %res = bitcast <4 x i32> %v to <8 x i16>
127 ret <8 x i16> %res
128}
129
130; CHECK-LABEL: v4i32_to_v4i32:
131; NO-SIMD128-NOT: return $0
132; SIMD128: return $0
133define <4 x i32> @v4i32_to_v4i32(<4 x i32> %v) {
134 %res = bitcast <4 x i32> %v to <4 x i32>
135 ret <4 x i32> %res
136}
137
138; CHECK-LABEL: v4i32_to_v2i64:
139; NO-SIMD128-NOT: return $0
140; SIMD128-VM: v128.store
141; SIMD128-VM-NEXT: return{{$}}
142; SIMD128: return $0
143define <2 x i64> @v4i32_to_v2i64(<4 x i32> %v) {
144 %res = bitcast <4 x i32> %v to <2 x i64>
145 ret <2 x i64> %res
146}
147
148; CHECK-LABEL: v4i32_to_v4f32:
149; NO-SIMD128-NOT: return $0
150; SIMD128: return $0
151define <4 x float> @v4i32_to_v4f32(<4 x i32> %v) {
152 %res = bitcast <4 x i32> %v to <4 x float>
153 ret <4 x float> %res
154}
155
156; CHECK-LABEL: v4i32_to_v2f64:
157; NO-SIMD128-NOT: return $0
158; SIMD128-VM: v128.store
159; SIMD128-VM-NEXT: return{{$}}
160; SIMD128: return $0
161define <2 x double> @v4i32_to_v2f64(<4 x i32> %v) {
162 %res = bitcast <4 x i32> %v to <2 x double>
163 ret <2 x double> %res
164}
165
166; CHECK-LABEL: v2i64_to_v16i8:
167; NO-SIMD128-NOT: return $0
168; SIMD128-VM-NOT: return $0
169; SIMD128: return $0
170define <16 x i8> @v2i64_to_v16i8(<2 x i64> %v) {
171 %res = bitcast <2 x i64> %v to <16 x i8>
172 ret <16 x i8> %res
173}
174
175; CHECK-LABEL: v2i64_to_v8i16:
176; NO-SIMD128-NOT: return $0
177; SIMD128-VM-NOT: return $0
178; SIMD128: return $0
179define <8 x i16> @v2i64_to_v8i16(<2 x i64> %v) {
180 %res = bitcast <2 x i64> %v to <8 x i16>
181 ret <8 x i16> %res
182}
183
184; CHECK-LABEL: v2i64_to_v4i32:
185; NO-SIMD128-NOT: return $0
186; SIMD128-VM-NOT: return $0
187; SIMD128: return $0
188define <4 x i32> @v2i64_to_v4i32(<2 x i64> %v) {
189 %res = bitcast <2 x i64> %v to <4 x i32>
190 ret <4 x i32> %res
191}
192
193; CHECK-LABEL: v2i64_to_v2i64:
194; NO-SIMD128-NOT: return $0
195; SIMD128-VM-NOT: return $0
196; SIMD128: return $0
197define <2 x i64> @v2i64_to_v2i64(<2 x i64> %v) {
198 %res = bitcast <2 x i64> %v to <2 x i64>
199 ret <2 x i64> %res
200}
201
202; CHECK-LABEL: v2i64_to_v4f32:
203; NO-SIMD128-NOT: return $0
204; SIMD128-VM-NOT: return $0
205; SIMD128: return $0
206define <4 x float> @v2i64_to_v4f32(<2 x i64> %v) {
207 %res = bitcast <2 x i64> %v to <4 x float>
208 ret <4 x float> %res
209}
210
211; CHECK-LABEL: v2i64_to_v2f64:
212; NO-SIMD128-NOT: return $0
213; SIMD128-VM-NOT: return $0
214; SIMD128: return $0
215define <2 x double> @v2i64_to_v2f64(<2 x i64> %v) {
216 %res = bitcast <2 x i64> %v to <2 x double>
217 ret <2 x double> %res
218}
219
220; CHECK-LABEL: v4f32_to_v16i8:
221; NO-SIMD128-NOT: return $0
222; SIMD128: return $0
223define <16 x i8> @v4f32_to_v16i8(<4 x float> %v) {
224 %res = bitcast <4 x float> %v to <16 x i8>
225 ret <16 x i8> %res
226}
227
228; CHECK-LABEL: v4f32_to_v8i16:
229; NO-SIMD128-NOT: return $0
230; SIMD128: return $0
231define <8 x i16> @v4f32_to_v8i16(<4 x float> %v) {
232 %res = bitcast <4 x float> %v to <8 x i16>
233 ret <8 x i16> %res
234}
235
236; CHECK-LABEL: v4f32_to_v4i32:
237; NO-SIMD128-NOT: return $0
238; SIMD128: return $0
239define <4 x i32> @v4f32_to_v4i32(<4 x float> %v) {
240 %res = bitcast <4 x float> %v to <4 x i32>
241 ret <4 x i32> %res
242}
243
244; CHECK-LABEL: v4f32_to_v2i64:
245; NO-SIMD128-NOT: return $0
246; SIMD128-VM: v128.store
247; SIMD128-VM-NEXT: return{{$}}
248; SIMD128: return $0
249define <2 x i64> @v4f32_to_v2i64(<4 x float> %v) {
250 %res = bitcast <4 x float> %v to <2 x i64>
251 ret <2 x i64> %res
252}
253
254; CHECK-LABEL: v4f32_to_v4f32:
255; NO-SIMD128-NOT: return $0
256; SIMD128: return $0
257define <4 x float> @v4f32_to_v4f32(<4 x float> %v) {
258 %res = bitcast <4 x float> %v to <4 x float>
259 ret <4 x float> %res
260}
261
262; CHECK-LABEL: v4f32_to_v2f64:
263; NO-SIMD128-NOT: return $0
264; SIMD128-VM: v128.store
265; SIMD128-VM-NEXT: return{{$}}
266; SIMD128: return $0
267define <2 x double> @v4f32_to_v2f64(<4 x float> %v) {
268 %res = bitcast <4 x float> %v to <2 x double>
269 ret <2 x double> %res
270}
271
272; CHECK-LABEL: v2f64_to_v16i8:
273; NO-SIMD128-NOT: return $0
274; SIMD128-VM-NOT: return $0
275; SIMD128: return $0
276define <16 x i8> @v2f64_to_v16i8(<2 x double> %v) {
277 %res = bitcast <2 x double> %v to <16 x i8>
278 ret <16 x i8> %res
279}
280
281; CHECK-LABEL: v2f64_to_v8i16:
282; NO-SIMD128-NOT: return $0
283; SIMD128-VM-NOT: return $0
284; SIMD128: return $0
285define <8 x i16> @v2f64_to_v8i16(<2 x double> %v) {
286 %res = bitcast <2 x double> %v to <8 x i16>
287 ret <8 x i16> %res
288}
289
290; CHECK-LABEL: v2f64_to_v4i32:
291; NO-SIMD128-NOT: return $0
292; SIMD128-VM-NOT: return $0
293; SIMD128: return $0
294define <4 x i32> @v2f64_to_v4i32(<2 x double> %v) {
295 %res = bitcast <2 x double> %v to <4 x i32>
296 ret <4 x i32> %res
297}
298
299; CHECK-LABEL: v2f64_to_v2i64:
300; NO-SIMD128-NOT: return $0
301; SIMD128-VM-NOT: return $0
302; SIMD128: return $0
303define <2 x i64> @v2f64_to_v2i64(<2 x double> %v) {
304 %res = bitcast <2 x double> %v to <2 x i64>
305 ret <2 x i64> %res
306}
307
308; CHECK-LABEL: v2f64_to_v4f32:
309; NO-SIMD128-NOT: return $0
310; SIMD128-VM-NOT: return $0
311; SIMD128: return $0
312define <4 x float> @v2f64_to_v4f32(<2 x double> %v) {
313 %res = bitcast <2 x double> %v to <4 x float>
314 ret <4 x float> %res
315}
316
317; CHECK-LABEL: v2f64_to_v2f64:
318; NO-SIMD128-NOT: return $0
319; SIMD128-VM-NOT: return $0
320; SIMD128: return $0
321define <2 x double> @v2f64_to_v2f64(<2 x double> %v) {
322 %res = bitcast <2 x double> %v to <2 x double>
323 ret <2 x double> %res
324}