Bob Wilson | c3ff538 | 2010-12-15 22:14:01 +0000 | [diff] [blame] | 1 | @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s |
Owen Anderson | 6f9cd06 | 2010-10-29 19:51:11 +0000 | [diff] [blame] | 2 | |
Jim Grosbach | 610aa62 | 2011-10-04 20:42:35 +0000 | [diff] [blame] | 3 | |
Jim Grosbach | 32b83a4 | 2011-10-18 18:14:55 +0000 | [diff] [blame] | 4 | vmul.i8 d16, d16, d17 |
| 5 | vmul.i16 d16, d16, d17 |
| 6 | vmul.i32 d16, d16, d17 |
| 7 | vmul.f32 d16, d16, d17 |
| 8 | vmul.i8 q8, q8, q9 |
| 9 | vmul.i16 q8, q8, q9 |
| 10 | vmul.i32 q8, q8, q9 |
| 11 | vmul.f32 q8, q8, q9 |
| 12 | vmul.p8 d16, d16, d17 |
| 13 | vmul.p8 q8, q8, q9 |
| 14 | vmul.i16 d18, d8, d0[3] |
| 15 | |
| 16 | @ CHECK: vmul.i8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf2] |
| 17 | @ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0xb1,0x09,0x50,0xf2] |
| 18 | @ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0xb1,0x09,0x60,0xf2] |
| 19 | @ CHECK: vmul.f32 d16, d16, d17 @ encoding: [0xb1,0x0d,0x40,0xf3] |
| 20 | @ CHECK: vmul.i8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf2] |
| 21 | @ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0xf2,0x09,0x50,0xf2] |
| 22 | @ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0xf2,0x09,0x60,0xf2] |
| 23 | @ CHECK: vmul.f32 q8, q8, q9 @ encoding: [0xf2,0x0d,0x40,0xf3] |
| 24 | @ CHECK: vmul.p8 d16, d16, d17 @ encoding: [0xb1,0x09,0x40,0xf3] |
| 25 | @ CHECK: vmul.p8 q8, q8, q9 @ encoding: [0xf2,0x09,0x40,0xf3] |
| 26 | @ CHECK: vmul.i16 d18, d8, d0[3] @ encoding: [0x68,0x28,0xd8,0xf2] |
Jim Grosbach | 610aa62 | 2011-10-04 20:42:35 +0000 | [diff] [blame] | 27 | |
| 28 | |
Jim Grosbach | 32b83a4 | 2011-10-18 18:14:55 +0000 | [diff] [blame] | 29 | vqdmulh.s16 d16, d16, d17 |
| 30 | vqdmulh.s32 d16, d16, d17 |
| 31 | vqdmulh.s16 q8, q8, q9 |
| 32 | vqdmulh.s32 q8, q8, q9 |
| 33 | vqdmulh.s16 d11, d2, d3[0] |
Jim Grosbach | 610aa62 | 2011-10-04 20:42:35 +0000 | [diff] [blame] | 34 | |
Jim Grosbach | 32b83a4 | 2011-10-18 18:14:55 +0000 | [diff] [blame] | 35 | @ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf2] |
| 36 | @ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf2] |
| 37 | @ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf2] |
| 38 | @ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf2] |
| 39 | @ CHECK: vqdmulh.s16 d11, d2, d3[0] @ encoding: [0x43,0xbc,0x92,0xf2] |
Jim Grosbach | 610aa62 | 2011-10-04 20:42:35 +0000 | [diff] [blame] | 40 | |
| 41 | |
Jim Grosbach | 32b83a4 | 2011-10-18 18:14:55 +0000 | [diff] [blame] | 42 | vqrdmulh.s16 d16, d16, d17 |
| 43 | vqrdmulh.s32 d16, d16, d17 |
| 44 | vqrdmulh.s16 q8, q8, q9 |
| 45 | vqrdmulh.s32 q8, q8, q9 |
Jim Grosbach | 610aa62 | 2011-10-04 20:42:35 +0000 | [diff] [blame] | 46 | |
Jim Grosbach | 32b83a4 | 2011-10-18 18:14:55 +0000 | [diff] [blame] | 47 | @ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf3] |
| 48 | @ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf3] |
| 49 | @ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf3] |
| 50 | @ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf3] |
Jim Grosbach | 610aa62 | 2011-10-04 20:42:35 +0000 | [diff] [blame] | 51 | |
| 52 | |
Jim Grosbach | 32b83a4 | 2011-10-18 18:14:55 +0000 | [diff] [blame] | 53 | vmull.s8 q8, d16, d17 |
| 54 | vmull.s16 q8, d16, d17 |
| 55 | vmull.s32 q8, d16, d17 |
| 56 | vmull.u8 q8, d16, d17 |
| 57 | vmull.u16 q8, d16, d17 |
| 58 | vmull.u32 q8, d16, d17 |
| 59 | vmull.p8 q8, d16, d17 |
Jim Grosbach | 610aa62 | 2011-10-04 20:42:35 +0000 | [diff] [blame] | 60 | |
Jim Grosbach | 32b83a4 | 2011-10-18 18:14:55 +0000 | [diff] [blame] | 61 | @ CHECK: vmull.s8 q8, d16, d17 @ encoding: [0xa1,0x0c,0xc0,0xf2] |
| 62 | @ CHECK: vmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0c,0xd0,0xf2] |
| 63 | @ CHECK: vmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0c,0xe0,0xf2] |
| 64 | @ CHECK: vmull.u8 q8, d16, d17 @ encoding: [0xa1,0x0c,0xc0,0xf3] |
| 65 | @ CHECK: vmull.u16 q8, d16, d17 @ encoding: [0xa1,0x0c,0xd0,0xf3] |
| 66 | @ CHECK: vmull.u32 q8, d16, d17 @ encoding: [0xa1,0x0c,0xe0,0xf3] |
| 67 | @ CHECK: vmull.p8 q8, d16, d17 @ encoding: [0xa1,0x0e,0xc0,0xf2] |
Jim Grosbach | 610aa62 | 2011-10-04 20:42:35 +0000 | [diff] [blame] | 68 | |
| 69 | |
Jim Grosbach | 32b83a4 | 2011-10-18 18:14:55 +0000 | [diff] [blame] | 70 | vqdmull.s16 q8, d16, d17 |
| 71 | vqdmull.s32 q8, d16, d17 |
Jim Grosbach | 610aa62 | 2011-10-04 20:42:35 +0000 | [diff] [blame] | 72 | |
Jim Grosbach | 32b83a4 | 2011-10-18 18:14:55 +0000 | [diff] [blame] | 73 | @ CHECK: vqdmull.s16 q8, d16, d17 @ encoding: [0xa1,0x0d,0xd0,0xf2] |
| 74 | @ CHECK: vqdmull.s32 q8, d16, d17 @ encoding: [0xa1,0x0d,0xe0,0xf2] |
Jim Grosbach | fdf9e15 | 2011-12-05 20:29:59 +0000 | [diff] [blame^] | 75 | |
| 76 | |
| 77 | vmul.i16 d0, d4[2] |
| 78 | vmul.s16 d1, d7[3] |
| 79 | vmul.u16 d2, d1[1] |
| 80 | vmul.i32 d3, d2[0] |
| 81 | vmul.s32 d4, d3[1] |
| 82 | vmul.u32 d5, d4[0] |
| 83 | vmul.f32 d6, d5[1] |
| 84 | |
| 85 | vmul.i16 q0, d4[2] |
| 86 | vmul.s16 q1, d7[3] |
| 87 | vmul.u16 q2, d1[1] |
| 88 | vmul.i32 q3, d2[0] |
| 89 | vmul.s32 q4, d3[1] |
| 90 | vmul.u32 q5, d4[0] |
| 91 | vmul.f32 q6, d5[1] |
| 92 | |
| 93 | vmul.i16 d9, d0, d4[2] |
| 94 | vmul.s16 d8, d1, d7[3] |
| 95 | vmul.u16 d7, d2, d1[1] |
| 96 | vmul.i32 d6, d3, d2[0] |
| 97 | vmul.s32 d5, d4, d3[1] |
| 98 | vmul.u32 d4, d5, d4[0] |
| 99 | vmul.f32 d3, d6, d5[1] |
| 100 | |
| 101 | vmul.i16 q9, q0, d4[2] |
| 102 | vmul.s16 q8, q1, d7[3] |
| 103 | vmul.u16 q7, q2, d1[1] |
| 104 | vmul.i32 q6, q3, d2[0] |
| 105 | vmul.s32 q5, q4, d3[1] |
| 106 | vmul.u32 q4, q5, d4[0] |
| 107 | vmul.f32 q3, q6, d5[1] |
| 108 | |
| 109 | @ CHECK: vmul.i16 d0, d0, d4[2] @ encoding: [0x64,0x08,0x90,0xf2] |
| 110 | @ CHECK: vmul.i16 d1, d1, d7[3] @ encoding: [0x6f,0x18,0x91,0xf2] |
| 111 | @ CHECK: vmul.i16 d2, d2, d1[1] @ encoding: [0x49,0x28,0x92,0xf2] |
| 112 | @ CHECK: vmul.i32 d3, d3, d2[0] @ encoding: [0x42,0x38,0xa3,0xf2] |
| 113 | @ CHECK: vmul.i32 d4, d4, d3[1] @ encoding: [0x63,0x48,0xa4,0xf2] |
| 114 | @ CHECK: vmul.i32 d5, d5, d4[0] @ encoding: [0x44,0x58,0xa5,0xf2] |
| 115 | @ CHECK: vmul.f32 d6, d6, d5[1] @ encoding: [0x65,0x69,0xa6,0xf2] |
| 116 | |
| 117 | @ CHECK: vmul.i16 q0, q0, d4[2] @ encoding: [0x64,0x08,0x90,0xf3] |
| 118 | @ CHECK: vmul.i16 q1, q1, d7[3] @ encoding: [0x6f,0x28,0x92,0xf3] |
| 119 | @ CHECK: vmul.i16 q2, q2, d1[1] @ encoding: [0x49,0x48,0x94,0xf3] |
| 120 | @ CHECK: vmul.i32 q3, q3, d2[0] @ encoding: [0x42,0x68,0xa6,0xf3] |
| 121 | @ CHECK: vmul.i32 q4, q4, d3[1] @ encoding: [0x63,0x88,0xa8,0xf3] |
| 122 | @ CHECK: vmul.i32 q5, q5, d4[0] @ encoding: [0x44,0xa8,0xaa,0xf3] |
| 123 | @ CHECK: vmul.f32 q6, q6, d5[1] @ encoding: [0x65,0xc9,0xac,0xf3] |
| 124 | |
| 125 | @ CHECK: vmul.i16 d9, d0, d4[2] @ encoding: [0x64,0x98,0x90,0xf2] |
| 126 | @ CHECK: vmul.i16 d8, d1, d7[3] @ encoding: [0x6f,0x88,0x91,0xf2] |
| 127 | @ CHECK: vmul.i16 d7, d2, d1[1] @ encoding: [0x49,0x78,0x92,0xf2] |
| 128 | @ CHECK: vmul.i32 d6, d3, d2[0] @ encoding: [0x42,0x68,0xa3,0xf2] |
| 129 | @ CHECK: vmul.i32 d5, d4, d3[1] @ encoding: [0x63,0x58,0xa4,0xf2] |
| 130 | @ CHECK: vmul.i32 d4, d5, d4[0] @ encoding: [0x44,0x48,0xa5,0xf2] |
| 131 | @ CHECK: vmul.f32 d3, d6, d5[1] @ encoding: [0x65,0x39,0xa6,0xf2] |
| 132 | |
| 133 | @ CHECK: vmul.i16 q9, q0, d4[2] @ encoding: [0x64,0x28,0xd0,0xf3] |
| 134 | @ CHECK: vmul.i16 q8, q1, d7[3] @ encoding: [0x6f,0x08,0xd2,0xf3] |
| 135 | @ CHECK: vmul.i16 q7, q2, d1[1] @ encoding: [0x49,0xe8,0x94,0xf3] |
| 136 | @ CHECK: vmul.i32 q6, q3, d2[0] @ encoding: [0x42,0xc8,0xa6,0xf3] |
| 137 | @ CHECK: vmul.i32 q5, q4, d3[1] @ encoding: [0x63,0xa8,0xa8,0xf3] |
| 138 | @ CHECK: vmul.i32 q4, q5, d4[0] @ encoding: [0x44,0x88,0xaa,0xf3] |
| 139 | @ CHECK: vmul.f32 q3, q6, d5[1] @ encoding: [0x65,0x69,0xac,0xf3] |