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gerrit-public.fairphone.software / toolchain / llvm-project / fff860979d87b13de4ded80ae5958703ae712797 / . / llvm / test / CodeGen / PowerPC / fast-isel-conversion.ll
blob: 71611060ed7a99c1539444af8f420a2fc5fb8bbc [file] [log] [blame]
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]1; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]2; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s --check-prefix=ELF64LE
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]3; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 | FileCheck %s --check-prefix=PPC970
4
5;; Tests for 970 don't use -fast-isel-abort because we intentionally punt
6;; to SelectionDAG in some cases.
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]7
8; Test sitofp
9
10define void @sitofp_single_i64(i64 %a, float %b) nounwind ssp {
11entry:
12; ELF64: sitofp_single_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]13; ELF64LE: sitofp_single_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]14; PPC970: sitofp_single_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]15 %b.addr = alloca float, align 4
16 %conv = sitofp i64 %a to float
17; ELF64: std
18; ELF64: lfd
19; ELF64: fcfids
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]20; ELF64LE: std
21; ELF64LE: lfd
22; ELF64LE: fcfids
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]23; PPC970: std
24; PPC970: lfd
25; PPC970: fcfid
26; PPC970: frsp
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]27 store float %conv, float* %b.addr, align 4
28 ret void
29}
30
31define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp {
32entry:
33; ELF64: sitofp_single_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]34; ELF64LE: sitofp_single_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]35; PPC970: sitofp_single_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]36 %b.addr = alloca float, align 4
37 %conv = sitofp i32 %a to float
38; ELF64: std
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]39; stack offset used to load the float: 65524 = -16 + 4
40; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]41; ELF64: lfiwax
42; ELF64: fcfids
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]43; ELF64LE: std
44; stack offset used to load the float: 65520 = -16 + 0
45; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
46; ELF64LE: lfiwax
47; ELF64LE: fcfids
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]48; PPC970: std
49; PPC970: lfd
50; PPC970: fcfid
51; PPC970: frsp
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]52 store float %conv, float* %b.addr, align 4
53 ret void
54}
55
56define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp {
57entry:
58; ELF64: sitofp_single_i16
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]59; ELF64LE: sitofp_single_i16
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]60; PPC970: sitofp_single_i16
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]61 %b.addr = alloca float, align 4
62 %conv = sitofp i16 %a to float
63; ELF64: extsh
64; ELF64: std
65; ELF64: lfd
66; ELF64: fcfids
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]67; ELF64LE: extsh
68; ELF64LE: std
69; ELF64LE: lfd
70; ELF64LE: fcfids
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]71; PPC970: extsh
72; PPC970: std
73; PPC970: lfd
74; PPC970: fcfid
75; PPC970: frsp
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]76 store float %conv, float* %b.addr, align 4
77 ret void
78}
79
80define void @sitofp_single_i8(i8 %a) nounwind ssp {
81entry:
82; ELF64: sitofp_single_i8
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]83; ELF64LE: sitofp_single_i8
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]84; PPC970: sitofp_single_i8
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]85 %b.addr = alloca float, align 4
86 %conv = sitofp i8 %a to float
87; ELF64: extsb
88; ELF64: std
89; ELF64: lfd
90; ELF64: fcfids
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]91; ELF64LE: extsb
92; ELF64LE: std
93; ELF64LE: lfd
94; ELF64LE: fcfids
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]95; PPC970: extsb
96; PPC970: std
97; PPC970: lfd
98; PPC970: fcfid
99; PPC970: frsp
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]100 store float %conv, float* %b.addr, align 4
101 ret void
102}
103
104define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp {
105entry:
106; ELF64: sitofp_double_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]107; ELF64LE: sitofp_double_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]108; PPC970: sitofp_double_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]109 %b.addr = alloca double, align 8
110 %conv = sitofp i32 %a to double
111; ELF64: std
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]112; stack offset used to load the float: 65524 = -16 + 4
113; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]114; ELF64: lfiwax
115; ELF64: fcfid
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]116; ELF64LE: std
117; stack offset used to load the float: 65520 = -16 + 0
118; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
119; ELF64LE: lfiwax
120; ELF64LE: fcfid
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]121; PPC970: std
122; PPC970: lfd
123; PPC970: fcfid
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]124 store double %conv, double* %b.addr, align 8
125 ret void
126}
127
128define void @sitofp_double_i64(i64 %a, double %b) nounwind ssp {
129entry:
130; ELF64: sitofp_double_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]131; ELF64LE: sitofp_double_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]132; PPC970: sitofp_double_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]133 %b.addr = alloca double, align 8
134 %conv = sitofp i64 %a to double
135; ELF64: std
136; ELF64: lfd
137; ELF64: fcfid
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]138; ELF64LE: std
139; ELF64LE: lfd
140; ELF64LE: fcfid
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]141; PPC970: std
142; PPC970: lfd
143; PPC970: fcfid
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]144 store double %conv, double* %b.addr, align 8
145 ret void
146}
147
148define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp {
149entry:
150; ELF64: sitofp_double_i16
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]151; ELF64LE: sitofp_double_i16
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]152; PPC970: sitofp_double_i16
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]153 %b.addr = alloca double, align 8
154 %conv = sitofp i16 %a to double
155; ELF64: extsh
156; ELF64: std
157; ELF64: lfd
158; ELF64: fcfid
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]159; ELF64LE: extsh
160; ELF64LE: std
161; ELF64LE: lfd
162; ELF64LE: fcfid
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]163; PPC970: extsh
164; PPC970: std
165; PPC970: lfd
166; PPC970: fcfid
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]167 store double %conv, double* %b.addr, align 8
168 ret void
169}
170
171define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp {
172entry:
173; ELF64: sitofp_double_i8
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]174; ELF64LE: sitofp_double_i8
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]175; PPC970: sitofp_double_i8
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]176 %b.addr = alloca double, align 8
177 %conv = sitofp i8 %a to double
178; ELF64: extsb
179; ELF64: std
180; ELF64: lfd
181; ELF64: fcfid
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]182; ELF64LE: extsb
183; ELF64LE: std
184; ELF64LE: lfd
185; ELF64LE: fcfid
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]186; PPC970: extsb
187; PPC970: std
188; PPC970: lfd
189; PPC970: fcfid
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]190 store double %conv, double* %b.addr, align 8
191 ret void
192}
193
194; Test uitofp
195
196define void @uitofp_single_i64(i64 %a, float %b) nounwind ssp {
197entry:
198; ELF64: uitofp_single_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]199; ELF64LE: uitofp_single_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]200; PPC970: uitofp_single_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]201 %b.addr = alloca float, align 4
202 %conv = uitofp i64 %a to float
203; ELF64: std
204; ELF64: lfd
205; ELF64: fcfidus
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]206; ELF64LE: std
207; ELF64LE: lfd
208; ELF64LE: fcfidus
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]209; PPC970-NOT: fcfidus
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]210 store float %conv, float* %b.addr, align 4
211 ret void
212}
213
214define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp {
215entry:
216; ELF64: uitofp_single_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]217; ELF64LE: uitofp_single_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]218; PPC970: uitofp_single_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]219 %b.addr = alloca float, align 4
220 %conv = uitofp i32 %a to float
221; ELF64: std
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]222; stack offset used to load the float: 65524 = -16 + 4
223; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]224; ELF64: lfiwzx
225; ELF64: fcfidus
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]226; ELF64LE: std
227; stack offset used to load the float: 65520 = -16 + 0
228; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
229; ELF64LE: lfiwzx
230; ELF64LE: fcfidus
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]231; PPC970-NOT: lfiwzx
232; PPC970-NOT: fcfidus
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]233 store float %conv, float* %b.addr, align 4
234 ret void
235}
236
237define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp {
238entry:
239; ELF64: uitofp_single_i16
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]240; ELF64LE: uitofp_single_i16
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]241; PPC970: uitofp_single_i16
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]242 %b.addr = alloca float, align 4
243 %conv = uitofp i16 %a to float
244; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
245; ELF64: std
246; ELF64: lfd
247; ELF64: fcfidus
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]248; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
249; ELF64LE: std
250; ELF64LE: lfd
251; ELF64LE: fcfidus
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]252; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
253; PPC970: std
254; PPC970: lfd
255; PPC970: fcfid
256; PPC970: frsp
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]257 store float %conv, float* %b.addr, align 4
258 ret void
259}
260
261define void @uitofp_single_i8(i8 %a) nounwind ssp {
262entry:
263; ELF64: uitofp_single_i8
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]264; ELF64LE: uitofp_single_i8
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]265; PPC970: uitofp_single_i8
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]266 %b.addr = alloca float, align 4
267 %conv = uitofp i8 %a to float
268; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
269; ELF64: std
270; ELF64: lfd
271; ELF64: fcfidus
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]272; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
273; ELF64LE: std
274; ELF64LE: lfd
275; ELF64LE: fcfidus
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]276; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
277; PPC970: std
278; PPC970: lfd
279; PPC970: fcfid
280; PPC970: frsp
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]281 store float %conv, float* %b.addr, align 4
282 ret void
283}
284
285define void @uitofp_double_i64(i64 %a, double %b) nounwind ssp {
286entry:
287; ELF64: uitofp_double_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]288; ELF64LE: uitofp_double_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]289; PPC970: uitofp_double_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]290 %b.addr = alloca double, align 8
291 %conv = uitofp i64 %a to double
292; ELF64: std
293; ELF64: lfd
294; ELF64: fcfidu
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]295; ELF64LE: std
296; ELF64LE: lfd
297; ELF64LE: fcfidu
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]298; PPC970-NOT: fcfidu
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]299 store double %conv, double* %b.addr, align 8
300 ret void
301}
302
303define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp {
304entry:
305; ELF64: uitofp_double_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]306; ELF64LE: uitofp_double_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]307; PPC970: uitofp_double_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]308 %b.addr = alloca double, align 8
309 %conv = uitofp i32 %a to double
310; ELF64: std
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]311; stack offset used to load the float: 65524 = -16 + 4
312; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]313; ELF64: lfiwzx
314; ELF64: fcfidu
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]315; ELF64LE: std
316; stack offset used to load the float: 65520 = -16 + 0
317; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
318; ELF64LE: lfiwzx
319; ELF64LE: fcfidu
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]320; PPC970-NOT: lfiwzx
321; PPC970-NOT: fcfidu
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]322 store double %conv, double* %b.addr, align 8
323 ret void
324}
325
326define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp {
327entry:
328; ELF64: uitofp_double_i16
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]329; ELF64LE: uitofp_double_i16
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]330; PPC970: uitofp_double_i16
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]331 %b.addr = alloca double, align 8
332 %conv = uitofp i16 %a to double
333; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
334; ELF64: std
335; ELF64: lfd
336; ELF64: fcfidu
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]337; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
338; ELF64LE: std
339; ELF64LE: lfd
340; ELF64LE: fcfidu
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]341; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 16, 31
342; PPC970: std
343; PPC970: lfd
344; PPC970: fcfid
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]345 store double %conv, double* %b.addr, align 8
346 ret void
347}
348
349define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp {
350entry:
351; ELF64: uitofp_double_i8
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]352; ELF64LE: uitofp_double_i8
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]353; PPC970: uitofp_double_i8
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]354 %b.addr = alloca double, align 8
355 %conv = uitofp i8 %a to double
356; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
357; ELF64: std
358; ELF64: lfd
359; ELF64: fcfidu
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]360; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
361; ELF64LE: std
362; ELF64LE: lfd
363; ELF64LE: fcfidu
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]364; PPC970: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31
365; PPC970: std
366; PPC970: lfd
367; PPC970: fcfid
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]368 store double %conv, double* %b.addr, align 8
369 ret void
370}
371
372; Test fptosi
373
374define void @fptosi_float_i32(float %a) nounwind ssp {
375entry:
376; ELF64: fptosi_float_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]377; ELF64LE: fptosi_float_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]378; PPC970: fptosi_float_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]379 %b.addr = alloca i32, align 4
380 %conv = fptosi float %a to i32
381; ELF64: fctiwz
382; ELF64: stfd
383; ELF64: lwa
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]384; ELF64LE: fctiwz
385; ELF64LE: stfd
386; ELF64LE: lwa
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]387; PPC970: fctiwz
388; PPC970: stfd
389; PPC970: lwa
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]390 store i32 %conv, i32* %b.addr, align 4
391 ret void
392}
393
394define void @fptosi_float_i64(float %a) nounwind ssp {
395entry:
396; ELF64: fptosi_float_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]397; ELF64LE: fptosi_float_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]398; PPC970: fptosi_float_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]399 %b.addr = alloca i64, align 4
400 %conv = fptosi float %a to i64
401; ELF64: fctidz
402; ELF64: stfd
403; ELF64: ld
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]404; ELF64LE: fctidz
405; ELF64LE: stfd
406; ELF64LE: ld
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]407; PPC970: fctidz
408; PPC970: stfd
409; PPC970: ld
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]410 store i64 %conv, i64* %b.addr, align 4
411 ret void
412}
413
414define void @fptosi_double_i32(double %a) nounwind ssp {
415entry:
416; ELF64: fptosi_double_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]417; ELF64LE: fptosi_double_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]418; PPC970: fptosi_double_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]419 %b.addr = alloca i32, align 8
420 %conv = fptosi double %a to i32
421; ELF64: fctiwz
422; ELF64: stfd
423; ELF64: lwa
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]424; ELF64LE: fctiwz
425; ELF64LE: stfd
426; ELF64LE: lwa
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]427; PPC970: fctiwz
428; PPC970: stfd
429; PPC970: lwa
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]430 store i32 %conv, i32* %b.addr, align 8
431 ret void
432}
433
434define void @fptosi_double_i64(double %a) nounwind ssp {
435entry:
436; ELF64: fptosi_double_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]437; ELF64LE: fptosi_double_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]438; PPC970: fptosi_double_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]439 %b.addr = alloca i64, align 8
440 %conv = fptosi double %a to i64
441; ELF64: fctidz
442; ELF64: stfd
443; ELF64: ld
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]444; ELF64LE: fctidz
445; ELF64LE: stfd
446; ELF64LE: ld
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]447; PPC970: fctidz
448; PPC970: stfd
449; PPC970: ld
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]450 store i64 %conv, i64* %b.addr, align 8
451 ret void
452}
453
454; Test fptoui
455
456define void @fptoui_float_i32(float %a) nounwind ssp {
457entry:
458; ELF64: fptoui_float_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]459; ELF64LE: fptoui_float_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]460; PPC970: fptoui_float_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]461 %b.addr = alloca i32, align 4
462 %conv = fptoui float %a to i32
463; ELF64: fctiwuz
464; ELF64: stfd
465; ELF64: lwz
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]466; ELF64LE: fctiwuz
467; ELF64LE: stfd
468; ELF64LE: lwz
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]469; PPC970: fctidz
470; PPC970: stfd
471; PPC970: lwz
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]472 store i32 %conv, i32* %b.addr, align 4
473 ret void
474}
475
476define void @fptoui_float_i64(float %a) nounwind ssp {
477entry:
478; ELF64: fptoui_float_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]479; ELF64LE: fptoui_float_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]480; PPC970: fptoui_float_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]481 %b.addr = alloca i64, align 4
482 %conv = fptoui float %a to i64
483; ELF64: fctiduz
484; ELF64: stfd
485; ELF64: ld
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]486; ELF64LE: fctiduz
487; ELF64LE: stfd
488; ELF64LE: ld
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]489; PPC970-NOT: fctiduz
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]490 store i64 %conv, i64* %b.addr, align 4
491 ret void
492}
493
494define void @fptoui_double_i32(double %a) nounwind ssp {
495entry:
496; ELF64: fptoui_double_i32
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]497; ELF64LE: fptoui_double_i32
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]498; PPC970: fptoui_double_i32
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]499 %b.addr = alloca i32, align 8
500 %conv = fptoui double %a to i32
501; ELF64: fctiwuz
502; ELF64: stfd
503; ELF64: lwz
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]504; ELF64LE: fctiwuz
505; ELF64LE: stfd
506; ELF64LE: lwz
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]507; PPC970: fctidz
508; PPC970: stfd
509; PPC970: lwz
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]510 store i32 %conv, i32* %b.addr, align 8
511 ret void
512}
513
514define void @fptoui_double_i64(double %a) nounwind ssp {
515entry:
516; ELF64: fptoui_double_i64
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]517; ELF64LE: fptoui_double_i64
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]518; PPC970: fptoui_double_i64
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]519 %b.addr = alloca i64, align 8
520 %conv = fptoui double %a to i64
521; ELF64: fctiduz
522; ELF64: stfd
523; ELF64: ld
Samuel Antao1194b8f2014-10-09 20:42:56 +0000[diff] [blame]524; ELF64LE: fctiduz
525; ELF64LE: stfd
526; ELF64LE: ld
Bill Schmidt83973ef2014-06-24 20:05:18 +0000[diff] [blame]527; PPC970-NOT: fctiduz
Bill Schmidt8d86fe72013-08-30 15:18:11 +0000[diff] [blame]528 store i64 %conv, i64* %b.addr, align 8
529 ret void
530}