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gerrit-public.fairphone.software / toolchain / llvm-project / 81fe1fbf4abd00b24e078a80cb15a2d2c1343f11 / llvm / lib / Target / AMDGPU / AMDGPU.h
  1. 4c4d2fe [AMDGPU] Add new Mode Register pass by Tim Corringham · 7 years ago
  2. 3d9afa2 [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3) by Valery Pykhtin · 7 years ago
  3. c660386 Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic" by David Stuttard · 7 years ago
  4. de02e4b Add support for TFE/LWE in image intrinsics by David Stuttard · 7 years ago
  5. cac749a [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST by Ron Lieberman · 7 years ago
  6. 8ba740a Allow subclassing ExternalAA by Matt Arsenault · 7 years ago
  7. 11ef798 [AMDGPU] Add a pass to promote bitcast calls by Scott Linder · 7 years ago
  8. 6641657 [AMDGPU] Add an AMDGPU specific atomic optimizer. by Neil Henning · 7 years ago
  9. 2e35c1e Remove unnecessary semicolon to silence -Wpedantic warning. NFCI. by Simon Pilgrim · 7 years ago
  10. 0da6350 AMDGPU: Remove remnants of old address space mapping by Matt Arsenault · 7 years ago
  11. 7bd9dcf AMDGPU: bump AS.MAX_COMMON_ADDRESS to 6 since 32-bit addr space by Samuel Pitoiset · 7 years ago
  12. 30b5ed3 Revert "AMDGPU: bump AS.MAX_COMMON_ADDRESS to 6 since 32-bit addr space" by Vitaly Buka · 7 years ago
  13. c95ef77 AMDGPU: bump AS.MAX_COMMON_ADDRESS to 6 since 32-bit addr space by Samuel Pitoiset · 7 years ago
  14. 8c4a352 AMDGPU: Add pass to lower kernel arguments to loads by Matt Arsenault · 7 years ago
  15. 739174c [AMDGPU] Construct memory clauses before RA by Stanislav Mekhanoshin · 7 years ago
  16. 1c53842 [AMDGPU] Add perf hints to functions by Stanislav Mekhanoshin · 7 years ago
  17. 44b30b4 AMDGPU: Remove #include "MCTargetDesc/AMDGPUMCTargetDesc.h" from common headers by Tom Stellard · 7 years ago
  18. 372d796 AMDGPU: Add pass to optimize reqd_work_group_size by Matt Arsenault · 7 years ago
  19. 432aaea AMDGPU: Rename OpenCL lowering pass to be R600 specific. by Matt Arsenault · 7 years ago
  20. 4a0f2c5 [AMDGPU][Waitcnt] Remove the old waitcnt pass by Mark Searles · 7 years ago
  21. 0124b54 [AMDGPU] Change constant addr space to 4 by Yaxun Liu · 8 years ago
  22. 923712b Reapply "AMDGPU: Add 32-bit constant address space" by Matt Arsenault · 8 years ago
  23. f4e3f3e Revert "AMDGPU: Add 32-bit constant address space" by Rafael Espindola · 8 years ago
  24. 871c30e AMDGPU: Add 32-bit constant address space by Marek Olsak · 8 years ago
  25. f9ab3dd [AMDGPU] Clean up symbols in the global namespace. by Benjamin Kramer · 8 years ago
  26. de4b88d [AMDGPU] Lower enqueued blocks and generate runtime metadata by Yaxun Liu · 8 years ago
  27. 1d8cf2b [AMDGPU] Set fast-math flags on functions given the options by Stanislav Mekhanoshin · 8 years ago
  28. 5670e6d [AMDGPU] Port of HSAIL inliner by Stanislav Mekhanoshin · 8 years ago
  29. 7f37794 [AMDGPU] Ported and adopted AMDLibCalls pass by Stanislav Mekhanoshin · 8 years ago
  30. 2028769 AMDGPU: Move R600 parts of AMDGPUISelDAGToDAG into their own class by Tom Stellard · 8 years ago
  31. 3db4568 AMDGPU: Remove FixControlFlowLiveIntervals pass by Matt Arsenault · 8 years ago
  32. 92638ab [AMDGPU] Add support for Whole Wavefront Mode by Connor Abbott · 8 years ago
  33. 7016f13 AMDGPU: Add analysis pass for function argument info by Matt Arsenault · 8 years ago
  34. a2f57be AMDGPU/R600: Initialize more passes by Tom Stellard · 8 years ago
  35. 37e7f95 [AMDGPU] Collapse adjacent SI_END_CF by Stanislav Mekhanoshin · 8 years ago
  36. c06574f AMDGPU: Add pass to replace out arguments by Matt Arsenault · 8 years ago
  37. e9a5a77 AMDGPU: Implement memory model by Konstantin Zhuravlyov · 8 years ago
  38. 6b93046 AMDGPU: Annotate call graph with used features by Matt Arsenault · 8 years ago
  39. 7c52590 AMDGPU: Remove SITypeRewriter by Matt Arsenault · 8 years ago
  40. 746e065 AMDGPU: Register AMDGPUAlwaysInline by Matt Arsenault · 8 years ago
  41. 8b61764 [LegacyPassManager] Remove TargetMachine constructors by Francis Visoiu Mistrih · 8 years ago
  42. a06bfe0 Re-submit AMDGPUMachineCFGStructurizer. by Jan Sjodin · 8 years ago
  43. 0e28982 Revert 303091. by Jan Sjodin · 8 years ago
  44. e9d2ddc Add AMDGPUMachineCFGStructurizer. by Jan Sjodin · 8 years ago
  45. c90347d [AMDGPU] Generate range metadata for workitem id by Stanislav Mekhanoshin · 8 years ago
  46. acb089e [AMDGPU] Add a new pass to insert waitcnts. Leave under an option for testing. by Kannan Narayanan · 8 years ago
  47. 678e111 AMDGPU: Fix crash when disassembling VOP3 mac by Matt Arsenault · 8 years ago
  48. 76ae47c [AMDGPU] Temporarily change constant address space from 4 to 2 by Yaxun Liu · 8 years ago
  49. 89653df [AMDGPU] Add GlobalOpt parameter to Always Inliner pass by Stanislav Mekhanoshin · 9 years ago
  50. 1a14bfa [AMDGPU] Get address space mapping by target triple environment by Yaxun Liu · 9 years ago
  51. b8f8dbc AMDGPU: Unify divergent function exits. by Matt Arsenault · 9 years ago
  52. f60ad58 [ADMGPU] SDWA peephole optimization pass. by Sam Kolton · 9 years ago
  53. 8e45acf [AMDGPU] Add address space based alias analysis pass by Stanislav Mekhanoshin · 9 years ago
  54. e823d92 AMDGPU: Merge initial gfx9 support by Matt Arsenault · 9 years ago
  55. 0699ef3 AMDGPU: Add pass to expand memcpy/memmove/memset by Matt Arsenault · 9 years ago
  56. f6c1feb [AMDGPU] Turn AMDGPUUnifyMetadata back into module pass by Stanislav Mekhanoshin · 9 years ago
  57. 22a56f2 [AMDGPU] Add VGPR copies post regalloc fix pass by Stanislav Mekhanoshin · 9 years ago
  58. 50ea93a [AMDGPU] Add amdgpu-unify-metadata pass by Stanislav Mekhanoshin · 9 years ago
  59. f42454b Move the global variables representing each Target behind accessor function by Mehdi Amini · 9 years ago
  60. 60a8373 [AMDGPU] Pass optimization level to SelectionDAGISel by Konstantin Zhuravlyov · 9 years ago
  61. e674075 AMDGPU: Partially fix control flow at -O0 by Matt Arsenault · 9 years ago
  62. 78fc9da AMDGPU: Split SILowerControlFlow into two pieces by Matt Arsenault · 9 years ago
  63. 2ffe8fd AMDGPU: Prune includes by Matt Arsenault · 9 years ago
  64. a1fe17c AMDGPU: Change fdiv lowering based on !fpmath metadata by Matt Arsenault · 9 years ago
  65. ca7f570 AMDGPU/R600: Delete/rename intrinsics no longer used by mesa by Matt Arsenault · 9 years ago
  66. 86de486 AMDGPU: Add stub custom CodeGenPrepare pass by Matt Arsenault · 9 years ago
  67. c3a01ec AMDGPU: Properly initialize SIShrinkInstructions by Matt Arsenault · 9 years ago
  68. ec30eb5 AMDGPU: Remove unused address space by Matt Arsenault · 9 years ago
  69. 81f1b30 AMDGPU/EG,CM: Add instruction to read from constant AS (VTX2) by Jan Vesely · 9 years ago
  70. a791932 [AMDGPU][NFC] Rename SIInsertNops -> SIDebuggerInsertNops by Konstantin Zhuravlyov · 9 years ago
  71. 723b73b AMDGPU: Remove SIFixSGPRLiveRanges pass by Nicolai Haehnle · 9 years ago
  72. df3a20c AMDGPU: Add a shader calling convention by Nicolai Haehnle · 9 years ago
  73. 213e87f AMDGPU: Add SIWholeQuadMode pass by Nicolai Haehnle · 10 years ago
  74. 6b6a2c3 AMDGPU: R600 code splitting cleanup by Matt Arsenault · 10 years ago
  75. cc7067a6 AMDGPU: Insert two S_NOP instructions for every high level source statement. by Tom Stellard · 10 years ago
  76. bc4497b AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions by Tom Stellard · 10 years ago
  77. 55d49cf AMDGPU: Initialize SILowerControlFlow by Matt Arsenault · 10 years ago
  78. 6e1967e AMDGPU/SI: Correctly initialize SIInsertWaits pass by Tom Stellard · 10 years ago
  79. e013246 AMDGPU: Fix emitting invalid workitem intrinsics for HSA by Matt Arsenault · 10 years ago
  80. 77a1777 Correctly initialize SIAnnotateControlFlow by Tom Stellard · 10 years ago
  81. 81efb6b Fix struct/class mismatch for MachineSchedContext by Hans Wennborg · 10 years ago
  82. 02c3291 AMDGPU/SI: Add SI Machine Scheduler by Nicolai Haehnle · 10 years ago
  83. a6f24c6 AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions by Tom Stellard · 10 years ago
  84. c93fc11 AMDGPU/SI: Emit constant arrays in the .text section by Tom Stellard · 10 years ago
  85. 0e3d389 AMDGPU: Remove SIPrepareScratchRegs by Matt Arsenault · 10 years ago
  86. 3931948 AMDGPU: Add pass to detect used kernel features by Matt Arsenault · 10 years ago
  87. 782c03b AMDGPU: Initialize SIFixSGPRCopies so -print-after works by Matt Arsenault · 10 years ago
  88. fd25395 AMDGPU: Add pass to lower OpenCL image and sampler arguments. by Tom Stellard · 10 years ago
  89. 45bb48e R600 -> AMDGPU rename by Tom Stellard · 10 years ago[Renamed from llvm/lib/Target/R600/AMDGPU.h]
  90. 218a959 Fix clang-cl self-host -Wc++11-narrowing bug by Reid Kleckner · 10 years ago
  91. 73e06fa R600/SI: Reimplement isLegalAddressingMode by Matt Arsenault · 10 years ago
  92. 28d13a4 R600/SI: add pass to mark CF live ranges as non-spillable by Tom Stellard · 10 years ago
  93. d8b3e9a [PM] Remove a bunch of stale TTI creation method declarations. I nuked by Chandler Carruth · 11 years ago
  94. 95292bb R600/SI: Use external symbols for scratch buffer by Tom Stellard · 11 years ago
  95. 42fb60e R600/SI: Spill VGPRs to scratch space for compute shaders by Tom Stellard · 11 years ago
  96. 49f8bfd R600/SI: Add a stub GCNTargetMachine by Tom Stellard · 11 years ago
  97. 6596ba7 R600/SI: Add SIFoldOperands pass by Tom Stellard · 11 years ago
  98. 5cbb53c Reapply: R600: Make sure to inline all internal functions by Tom Stellard · 11 years ago
  99. 9abe268 Revert "R600: Make sure to inline all internal functions" by Reid Kleckner · 11 years ago
  100. aa73831 R600: Make sure to inline all internal functions by Tom Stellard · 11 years ago