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gerrit-public.fairphone.software / toolchain / llvm-project / abc0662f04df16a28cd57b6a76c255136b46ff6b / llvm / lib / CodeGen / SelectionDAG / LegalizeVectorOps.cpp
  1. 1ed771f getVectorElementType().getSizeInBits() -> getScalarSizeInBits() ; NFCI by Sanjay Patel · 9 years ago
  2. b1f0a0f getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCI by Sanjay Patel · 9 years ago
  3. bd6fca1 getScalarType().getSizeInBits() -> getScalarSizeInBits() ; NFCI by Sanjay Patel · 9 years ago
  4. cd1d5aa Replace a few more "fall through" comments with LLVM_FALLTHROUGH by Justin Bogner · 9 years ago
  5. 9c37581 [SelectionDAG] Get rid of bool parameters in SelectionDAG::getLoad, getStore, and friends. by Justin Lebar · 9 years ago
  6. 2bd8b4b [CodeGen,Target] Remove the version of DAG.getVectorShuffle that takes a pointer to a mask array. Convert all callers to use the ArrayRef version. No functional change intended. by Craig Topper · 9 years ago
  7. 89b89650 [SelectionDAG] Attempt to split BITREVERSE vector legalization into BSWAP and BITREVERSE stages by Simon Pilgrim · 9 years ago
  8. 1f5ad70 [SelectionDAG] BITREVERSE vector legalization of bit operations (REAPPLIED) by Simon Pilgrim · 10 years ago
  9. 1a14f0d Revert r268504 by Simon Pilgrim · 10 years ago
  10. b97c062 [SelectionDAG] BITREVERSE vector legalization of bit operations by Simon Pilgrim · 10 years ago
  11. 52cb5ec [SelectionDAG] Teach LegalizeVectorOps to directly Expand CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to CTTZ/CTLZ directly if those ops are Legal/Custom instead of deferring it to LegalizeOps. by Craig Topper · 10 years ago
  12. 46ba316 LegalizeDAG: Don't replace vector store with integer if not legal by Matt Arsenault · 10 years ago
  13. a4b1b6e LegalizeDAG: Don't replace vector load with integer unless legal by Matt Arsenault · 10 years ago
  14. 61eb49e [X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG by Simon Pilgrim · 10 years ago
  15. 93cff7f [CodeGen] Document and use getConstant's splat-building feature. NFC. by Ahmed Bougacha · 10 years ago
  16. f8dfb47 [CodeGen] Prefer "if (SDValue R = ...)" to "if (R.getNode())". NFCI. by Ahmed Bougacha · 10 years ago
  17. 4b1808d [SelectionDAG] Teach LegalizeVectorOps to not unroll CTLZ_ZERO_UNDEF and CTTZ_ZERO_UNDEF if the non-ZERO_UNDEF form is legal or custom. Will be used to simplify X86 code in a follow on commit. by Craig Topper · 10 years ago
  18. d079285 AMDGPU: Use generic bitreverse intrinsic by Matt Arsenault · 10 years ago
  19. cd8664c Revert r248483, r242546, r242545, and r242409 - absdiff intrinsics by Hal Finkel · 10 years ago
  20. 33e61ec AVX-512: Fixed masked load / store instruction selection for KNL. by Elena Demikhovsky · 10 years ago
  21. 4675c43 Fix some places where we were assuming that memory type had been legalized by Eric Christopher · 10 years ago
  22. 891c097 Do not use "else" when both branches return (NFC) by Mehdi Amini · 10 years ago
  23. c736863 Two switch blocks in VectorLegalizer::LegalizeOp already have a by Artyom Skrobov · 10 years ago
  24. b844fa7 Combining DIV+REM->DIVREM doesn't belong in LegalizeDAG; move it over into DAGCombiner. by Artyom Skrobov · 10 years ago
  25. e400a7d SelectionDAG: Remove implicit ilist iterator conversions, NFC by Duncan P. N. Exon Smith · 10 years ago
  26. 13f1dfd Codegen: Fix llvm.*absdiff semantic. by Mohammad Shahid · 10 years ago
  27. a260701 propagate fast-math-flags on DAG nodes by Sanjay Patel · 10 years ago
  28. 01cdecc Add new ISD nodes: ISD::FMINNAN and ISD::FMAXNAN by James Molloy · 10 years ago
  29. 7395a81 [Codegen] Add intrinsics 'absdiff' and corresponding SDNodes for absolute difference operation by James Molloy · 10 years ago
  30. 9639d65 Make TargetLowering::getShiftAmountTy() taking DataLayout as an argument by Mehdi Amini · 10 years ago
  31. 44ede33 Make TargetLowering::getPointerTy() taking DataLayout as an argument by Mehdi Amini · 10 years ago
  32. 8ac7a9d Redirect DataLayout from TargetMachine to Module in SelectionDAG by Mehdi Amini · 10 years ago
  33. 8fc121d Convert a bunch of loops to foreach. NFC. by Pete Cooper · 10 years ago
  34. f00654e Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) by Alexander Kornienko · 10 years ago
  35. 70bc5f1 Fixed/added namespace ending comments using clang-tidy. NFC by Alexander Kornienko · 10 years ago
  36. 7e9776b Add SDNodes for umin, umax, smin and smax. by James Molloy · 10 years ago
  37. 1b60ed7 Masked gather and scatter intrinsics - enabled codegen for KNL. by Elena Demikhovsky · 11 years ago
  38. 842a51b Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes" by Sergey Dmitrouk · 11 years ago
  39. 48e93f7 Revert "[DebugInfo] Add debug locations to constant SD nodes" by Daniel Jasper · 11 years ago
  40. adb4c69 [DebugInfo] Add debug locations to constant SD nodes by Sergey Dmitrouk · 11 years ago
  41. f176566 fix typo and 80-col; NFC by Sanjay Patel · 11 years ago
  42. cec7013 [SDAG] Handle LowerOperation returning its input consistently by Hal Finkel · 11 years ago
  43. f5b9570 [SDAG] Use correct alignments on expanded vector trunc-store/ext-loads by Hal Finkel · 11 years ago
  44. 271e9f2 [SDAG] Don't try to use FP_EXTEND/FP_ROUND for int<->fp promotions by Hal Finkel · 11 years ago
  45. cd63c5f Fixes a bug in vector load legalization that confused bits and bytes. by Michael Kuperstein · 11 years ago
  46. 2b6917b [SelectionDAG] Allow targets to specify legality of extloads' result by Ahmed Bougacha · 11 years ago
  47. 7c93690 Add minnum / maxnum codegen by Matt Arsenault · 11 years ago
  48. 89d1542 Teach the AArch64 backend about v4f16 and v8f16 by Oliver Stannard · 11 years ago
  49. 67474e3 Make sure no loads resulting from load->switch DAGCombine are marked invariant by Louis Gerbarg · 11 years ago
  50. 80b8694 [x86] Make vector legalization of extloads work more like the "normal" by Chandler Carruth · 11 years ago
  51. cc39b67 AA metadata refactoring (introduce AAMDNodes) by Hal Finkel · 11 years ago
  52. 0b666e0 [x86,SDAG] Introduce any- and sign-extend-vector-inreg nodes analogous by Chandler Carruth · 11 years ago
  53. cbd44c5 Make it possible for ints/floats to return different values from getBooleanContents() by Daniel Sanders · 11 years ago
  54. afe4b25 [x86] Add a ZERO_EXTEND_VECTOR_INREG DAG node and use it when widening by Chandler Carruth · 11 years ago
  55. c1bedac [cleanup] Hoist an if-else chain on ISD opcodes (really designed for by Chandler Carruth · 11 years ago
  56. 722289f [cleanup] Remove dead 'break;' statements that I meant to nuke in by Chandler Carruth · 11 years ago
  57. 2746c28 [cleanup] Hoist the promotion dispatch logic into the promote function by Chandler Carruth · 11 years ago
  58. 1cfa895 [cleanup] Nuke the 'VectorOp' bit of the promote method names. by Chandler Carruth · 11 years ago
  59. 68adf15 [x86] Clean up and modernize the doxygen and API comments for the vector by Chandler Carruth · 11 years ago
  60. f3ad235 SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the bswap not. by Benjamin Kramer · 11 years ago
  61. 8c0b4d0 Convert more SelectionDAG functions to use ArrayRef. by Craig Topper · 12 years ago
  62. 48d114b Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>. by Craig Topper · 12 years ago
  63. 24381f1 [VectorLegalizer/X86] Don't unvectorize fp_to_uint for v8f32->v8i16 by Adam Nemet · 12 years ago
  64. b6d0bd4 [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. by Benjamin Kramer · 12 years ago
  65. 5c968d9 Expand vector bswap in LegalizeVectorOps by Hal Finkel · 12 years ago
  66. 39c1ce4 Keep TBAA info when rewriting SelectionDAG loads and stores by Richard Sandiford · 12 years ago
  67. bc08ddb Remove pointless assertion after r190376 by Matt Arsenault · 12 years ago
  68. d232222 Don't use getSetCCResultType for creating a vselect by Matt Arsenault · 12 years ago
  69. 838e234 SelectionDAG: Remove unnecessary uses of TargetLowering::getPointerTy() by Tom Stellard · 12 years ago
  70. 1b2c2d8 SelectionDAG: Make sure stores are always added to the LegalizedNodes list by Tom Stellard · 12 years ago
  71. 0c5c01aa Add a llvm.copysign intrinsic by Hal Finkel · 12 years ago
  72. 171817e Add ISD::FROUND for libm round() by Hal Finkel · 12 years ago
  73. d42c594 TargetLowering: Add getVectorIdxTy() function v2 by Tom Stellard · 12 years ago
  74. cfe7f35 Remove trailing whitespace from SelectionDAG/*.cpp by Stephen Lin · 12 years ago
  75. d2f0332 Introduce getSelect usage and use more getSelectCC by Matt Arsenault · 12 years ago
  76. 351d53c Remove double semicolons. by Benjamin Kramer · 12 years ago
  77. ef9de2a Track IR ordering of SelectionDAG nodes 2/4. by Andrew Trick · 12 years ago
  78. 75865923 Add LLVMContext argument to getSetCCResultType by Matt Arsenault · 12 years ago
  79. a5733dc Fix vselect when getSetCCResultType returns a different type from the operands by Matt Arsenault · 12 years ago
  80. b7f90bd SelectionDAG compile time improvement. by Nadav Rotem · 13 years ago
  81. 7fb3966 Fix PR15267 by Michael Liao · 13 years ago
  82. 0959bb7 This patch aims to reduce compile time in LegalizeTypes by using SmallDenseMap, by Preston Gurd · 13 years ago
  83. 5ea0349 When lowering an inreg sext first shift left, then right arithmetically. by Benjamin Kramer · 13 years ago
  84. dbe5c72 PPC: Implement efficient lowering of sign_extend_inreg. by Nadav Rotem · 13 years ago
  85. fd41b5b Change TargetLowering::getTypeToPromoteTo to take and return MVTs, by Patrik Hagglund · 13 years ago
  86. d7cdcf8 Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs. by Patrik Hagglund · 13 years ago
  87. e98b7a0 Revert EVT->MVT changes, r169836-169851, due to buildbot failures. by Patrik Hagglund · 13 years ago
  88. ffb60f7 Change TargetLowering::getTypeToPromoteTo to take and return MVTs, by Patrik Hagglund · 13 years ago
  89. 7ffcd22 Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs. by Patrik Hagglund · 13 years ago
  90. 3083494 Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete Couperus. by Eli Friedman · 13 years ago
  91. e6385e6 Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missing by Eli Friedman · 13 years ago
  92. 10f6b88 Fix a typo. by Nadav Rotem · 13 years ago
  93. 500d691 Generate better select code by allowing the target to use scalar select, and not sign-extend. by Nadav Rotem · 13 years ago
  94. 2455e9c Only legalise a VSELECT in to bitwise operations if the vector mask bool is zeros or all ones. A vector bool with just ones isn't suitable for masking with. by Pete Cooper · 13 years ago
  95. ea973bd by Nadav Rotem · 13 years ago
  96. 2da13f9 Add FMA to switch statement in VectorLegalizer::LegalizeOp so that it can be expanded when it isn't legal. by Craig Topper · 13 years ago
  97. e0c10d8 'Promote' vector [su]int_to_fp should widen elements. by Jim Grosbach · 13 years ago
  98. 02ef0c3 When emulating vselect using OR/AND/XOR make sure to bitcast the result back to the original type. by Nadav Rotem · 14 years ago
  99. ee4dab5 Convert assert(0) to llvm_unreachable by Craig Topper · 14 years ago
  100. 637cc6a Initial CodeGen support for CTTZ/CTLZ where a zero input produces an by Chandler Carruth · 14 years ago