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gerrit-public.fairphone.software / toolchain / llvm-project / b3f967d411358dcf54a8085df1d9097f5ab8b6d2 / llvm / lib / Target / AMDGPU / AMDGPUTargetMachine.cpp
  1. b3f967d [AMDGPU] Add the adjusted FP as a livein register. by Michael Liao · 6 years ago
  2. 58426a3 AMDGPU: Serialize mode from MachineFunctionInfo by Matt Arsenault · 6 years ago
  3. e7e23e3 AMDGPU: Make AMDGPUPerfHintAnalysis an SCC pass by Matt Arsenault · 6 years ago
  4. 5b0922f AMDGPU: Add pass to lower SGPR spills by Matt Arsenault · 6 years ago
  5. 80177ca [AMDGPU] Enable serializing of argument info. by Michael Liao · 6 years ago
  6. 2ce560f [AMDGPU] LCSSA pass added in preISel. Uniform values defined in the divergent loop and used outside by Alexander Timofeev · 6 years ago
  7. 9cac4e6 Rename ExpandISelPseudo->FinalizeISel, delay register reservation by Matt Arsenault · 6 years ago
  8. 3138278 [AMDGPU] Propagate function attributes thru bitcasts by Stanislav Mekhanoshin · 6 years ago
  9. a9191c8 [AMDGPU] gfx1010 wavefrontsize intrinsic folding by Stanislav Mekhanoshin · 6 years ago
  10. ad04e7a [AMDGPU] Pass to propagate ABI attributes from kernels to the functions by Stanislav Mekhanoshin · 6 years ago
  11. 4b0b261 Revert CMake: Make most target symbols hidden by default by Tom Stellard · 6 years ago
  12. 3745713 CMake: Make most target symbols hidden by default by Tom Stellard · 6 years ago
  13. 8ce2ee9 [AMDGPU] Create a TargetInfo header. NFC by Richard Trieu · 6 years ago
  14. 3b7925f [AMDGPU] gfx1010 GCNRegBankReassign pass by Stanislav Mekhanoshin · 7 years ago
  15. c29d491 [AMDGPU] gfx1010 GCNNSAReassign pass by Stanislav Mekhanoshin · 7 years ago
  16. d189680 [GlobalISel] Introduce a CSEConfigBase class to allow targets to define their own CSE configs. by Amara Emerson · 7 years ago
  17. 3db93ac Reapply [ValueTracking] Support min/max selects in computeConstantRange() by Nikita Popov · 7 years ago
  18. c8f78f8 [AMDGPU] Add MachineDCE pass after RenameIndependentSubregs by Stanislav Mekhanoshin · 7 years ago
  19. 0a30f33 [AMDGPU] Pre-allocate WWM registers to reduce VGPR pressure. by Neil Henning · 7 years ago
  20. 4d47ac3 AMDGPU: Add additional MIR tests for exec mask optimizations by Matt Arsenault · 7 years ago
  21. cf55a65 CodeGen: Refactor regallocator command line and target selection by Matt Arsenault · 7 years ago
  22. 523dab0 [AMDGPU] Add an experimental buffer fat pointer address space. by Neil Henning · 7 years ago
  23. e0c1f9e AMDGPU: Partially fix default device for HSA by Matt Arsenault · 7 years ago
  24. bc6d07c MIR: Allow targets to serialize MachineFunctionInfo by Matt Arsenault · 7 years ago
  25. c56d2af AMDGPU: Handle "uniform-work-group-size" attribute (fix for RADV) by Aakanksha Patil · 7 years ago
  26. 09a09ef AMDGPU: Fix typo by Matt Arsenault · 7 years ago
  27. 5d567dc AMDGPU: Enable function calls by default by Matt Arsenault · 7 years ago
  28. aa6fb4c AMDGPU: Remove debugger related subtarget features by Matt Arsenault · 7 years ago
  29. ded96df [AMDGPU] Enable DPP combiner pass by default. by Valery Pykhtin · 7 years ago
  30. 2946cd7 Update the file headers across all of the LLVM projects in the monorepo by Chandler Carruth · 7 years ago
  31. f77079f [AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try by David Stuttard · 7 years ago
  32. bc56876 Revert r348971: [AMDGPU] Support for "uniform-work-group-size" attribute by Aakanksha Patil · 7 years ago
  33. 729309c [AMDGPU] Support for "uniform-work-group-size" attribute by Aakanksha Patil · 7 years ago
  34. 4c4d2fe [AMDGPU] Add new Mode Register pass by Tim Corringham · 7 years ago
  35. ca29c27 [Targets] Add errors for tiny and kernel codemodel on targets that don't support them by David Green · 7 years ago
  36. f479fbb [AMDGPU] Partial revert of rL348371: Turn on the DPP combiner by default by Valery Pykhtin · 7 years ago
  37. 5b4db77 [AMDGPU]: Turn on the DPP combiner by default by Valery Pykhtin · 7 years ago
  38. 3d9afa2 [AMDGPU] Combine DPP mov with use instructions (VOP1/2/3) by Valery Pykhtin · 7 years ago
  39. c660386 Revert r347871 "Fix: Add support for TFE/LWE in image intrinsic" by David Stuttard · 7 years ago
  40. de02e4b Add support for TFE/LWE in image intrinsics by David Stuttard · 7 years ago
  41. 105fc1a AMDGPU: Don't optimize exec masks at -O0 by Matt Arsenault · 7 years ago
  42. cac749a [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST by Ron Lieberman · 7 years ago
  43. 8ba740a Allow subclassing ExternalAA by Matt Arsenault · 7 years ago
  44. 814abb5 AMDGPU: Rewrite SILowerI1Copies to always stay on SALU by Nicolai Haehnle · 7 years ago
  45. 11ef798 [AMDGPU] Add a pass to promote bitcast calls by Scott Linder · 7 years ago
  46. 6641657 [AMDGPU] Add an AMDGPU specific atomic optimizer. by Neil Henning · 7 years ago
  47. 635d479 AMDGPU: Always run AMDGPUAlwaysInline by Matt Arsenault · 7 years ago
  48. ab41193 AMDGPU: Expand atomicrmw nand in IR by Matt Arsenault · 7 years ago
  49. b4f2d1c [AMDGPU] restore r342722 which was reverted with r342743 by Sameer Sahasrabuddhe · 7 years ago
  50. 0807e94 revert changes from r342722 by Sameer Sahasrabuddhe · 7 years ago
  51. 2de7653 [AMDGPU] lower-switch in preISel as a workaround for legacy DA by Sameer Sahasrabuddhe · 7 years ago
  52. 988df63 AMDGPU: Stop forcing internalize at -O0 by Matt Arsenault · 7 years ago
  53. 0da6350 AMDGPU: Remove remnants of old address space mapping by Matt Arsenault · 7 years ago
  54. 72da47d run post-RA hazard recognizer pass late by Mark Searles · 7 years ago
  55. 5bfbae5 AMDGPU: Refactor Subtarget classes by Tom Stellard · 7 years ago
  56. a680199 Reapply "AMDGPU: Force inlining if LDS global address is used" by Matt Arsenault · 7 years ago
  57. 688e752 Revert "AMDGPU: Force inlining if LDS global address is used" by Vlad Tsyrklevich · 7 years ago
  58. 40cb6ca AMDGPU: Force inlining if LDS global address is used by Matt Arsenault · 7 years ago
  59. 20d4795 [AMDGPU] Enable LICM in the BE pipeline by Stanislav Mekhanoshin · 7 years ago
  60. 8c4a352 AMDGPU: Add pass to lower kernel arguments to loads by Matt Arsenault · 7 years ago
  61. 739174c [AMDGPU] Construct memory clauses before RA by Stanislav Mekhanoshin · 7 years ago
  62. c762431 AMDGPU: Split AMDGPUTTI into GCNTTI and R600TTI by Tom Stellard · 7 years ago
  63. 2e4d338 AMDGPU: Fix typo in option description by Matt Arsenault · 7 years ago
  64. 32efedc [AMDGPU][Waitcnt] Remove obsolete waitcnt option by Mark Searles · 7 years ago
  65. 372d796 AMDGPU: Add pass to optimize reqd_work_group_size by Matt Arsenault · 7 years ago
  66. 432aaea AMDGPU: Rename OpenCL lowering pass to be R600 specific. by Matt Arsenault · 7 years ago
  67. 4a0f2c5 [AMDGPU][Waitcnt] Remove the old waitcnt pass by Mark Searles · 7 years ago
  68. 5f8f34e4 Remove \brief commands from doxygen comments. by Adrian Prantl · 8 years ago
  69. e753c52 AMDGPU: Initialize GlobalISel passes by Tom Stellard · 8 years ago
  70. 95329f8 AMDGPU: Set natural stack alignment in DataLayout by Matt Arsenault · 8 years ago
  71. 6054e65 Move TargetLoweringObjectFile from CodeGen to Target to fix layering by David Blaikie · 8 years ago
  72. 0124b54 [AMDGPU] Change constant addr space to 4 by Yaxun Liu · 8 years ago
  73. 923712b Reapply "AMDGPU: Add 32-bit constant address space" by Matt Arsenault · 8 years ago
  74. f4e3f3e Revert "AMDGPU: Add 32-bit constant address space" by Rafael Espindola · 8 years ago
  75. 871c30e AMDGPU: Add 32-bit constant address space by Marek Olsak · 8 years ago
  76. 24c92ee [AMDGPU] Suppress redundant waitcnt instrs. by Mark Searles · 8 years ago
  77. 2a22c5d [AMDGPU] Switch to the new addr space mapping by default by Yaxun Liu · 8 years ago
  78. c8e9245 [NFC] fix trivial typos in comments and documents by Hiroshi Inoue · 8 years ago
  79. 4a7c8e7 Split MachineLICM into EarlyMachineLICM and MachineLICM; NFC by Matthias Braun · 8 years ago
  80. 26d11ca (Re-landing) Expose a TargetMachine::getTargetTransformInfo function by Sanjoy Das · 8 years ago
  81. 747d111 Revert "Expose a TargetMachine::getTargetTransformInfo function" by Sanjoy Das · 8 years ago
  82. 0c3de35 Expose a TargetMachine::getTargetTransformInfo function by Sanjoy Das · 8 years ago
  83. f2fe972 AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental) by Valery Pykhtin · 8 years ago
  84. b3bde2e Fix a bunch more layering of CodeGen headers that are in Target by David Blaikie · 8 years ago
  85. cc56a8b [AMDGPU] Change alloca addr space of r600 to 5 for amdgiz environment by Yaxun Liu · 8 years ago
  86. f9ab3dd [AMDGPU] Clean up symbols in the global namespace. by Benjamin Kramer · 8 years ago
  87. bb8507e Revert "TargetMachine: Merge TargetMachine and LLVMTargetMachine" by Matthias Braun · 8 years ago
  88. 3a9c114 TargetMachine: Merge TargetMachine and LLVMTargetMachine by Matthias Braun · 8 years ago
  89. cc85223 AMDGPU: Fix incorrect selection of pseudo-branches by Matt Arsenault · 8 years ago
  90. de4b88d [AMDGPU] Lower enqueued blocks and generate runtime metadata by Yaxun Liu · 8 years ago
  91. 1d8cf2b [AMDGPU] Set fast-math flags on functions given the options by Stanislav Mekhanoshin · 8 years ago
  92. 2e3bf37 [AMDGPU] Fixed memory leak with inliner replaced by Stanislav Mekhanoshin · 8 years ago
  93. 5641820 [AMDGPU] Fix regression in test clang/test/CodeGen/backend-unsupported-error.ll by Stanislav Mekhanoshin · 8 years ago
  94. 5670e6d [AMDGPU] Port of HSAIL inliner by Stanislav Mekhanoshin · 8 years ago
  95. e745d99 AMDGPU: Run internalize symbols at -O0 by Matt Arsenault · 8 years ago
  96. 7f37794 [AMDGPU] Ported and adopted AMDLibCalls pass by Stanislav Mekhanoshin · 8 years ago
  97. 2028769 AMDGPU: Move R600 parts of AMDGPUISelDAGToDAG into their own class by Tom Stellard · 8 years ago
  98. 9d288e6 AMDGPU: Remove redundant opt level check by Matt Arsenault · 8 years ago
  99. 3db4568 AMDGPU: Remove FixControlFlowLiveIntervals pass by Matt Arsenault · 8 years ago
  100. 8728c5f AMDGPU: Cleanup subtarget features by Matt Arsenault · 8 years ago