| /* Copyright (c) 2013, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| /include/ "skeleton64.dtsi" |
| |
| / { |
| model = "Qualcomm APQ 8084"; |
| compatible = "qcom,apq8084"; |
| interrupt-parent = <&intc>; |
| soc: soc { }; |
| }; |
| |
| /include/ "msm-gdsc.dtsi" |
| /include/ "apq8084-ion.dtsi" |
| /include/ "apq8084-iommu.dtsi" |
| /include/ "apq8084-smp2p.dtsi" |
| /include/ "apq8084-coresight.dtsi" |
| /include/ "apq8084-mdss.dtsi" |
| /include/ "apq8084-gpu.dtsi" |
| |
| &soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| |
| intc: interrupt-controller@f9000000 { |
| compatible = "qcom,msm-qgic2"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| reg = <0xF9000000 0x1000>, |
| <0xF9002000 0x1000>; |
| }; |
| |
| msmgpio: gpio@fd510000 { |
| compatible = "qcom,msm-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| reg = <0xfd510000 0x4000>; |
| ngpio = <146>; |
| interrupts = <0 208 0>; |
| qcom,direct-connect-irqs = <8>; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupts = <1 2 0 1 3 0>; |
| clock-frequency = <19200000>; |
| }; |
| |
| serial@f991f000 { |
| compatible = "qcom,msm-lsuart-v14"; |
| reg = <0xf991f000 0x1000>; |
| interrupts = <0 109 0>; |
| status = "disabled"; |
| }; |
| |
| qcom,cache_erp { |
| compatible = "qcom,cache_erp"; |
| interrupts = <1 9 0>, <0 2 0>; |
| interrupt-names = "l1_irq", "l2_irq"; |
| }; |
| |
| qcom,cache_dump { |
| compatible = "qcom,cache_dump"; |
| qcom,l1-dump-size = <0x100000>; |
| qcom,l2-dump-size = <0x500000>; |
| }; |
| |
| rpm_bus: qcom,rpm-smd { |
| compatible = "qcom,rpm-smd"; |
| rpm-channel-name = "rpm_requests"; |
| rpm-channel-type = <15>; /* SMD_APPS_RPM */ |
| rpm-standalone; |
| }; |
| |
| qcom,msm-imem@fe805000 { |
| compatible = "qcom,msm-imem"; |
| reg = <0xfe805000 0x1000>; /* Address and size of IMEM */ |
| }; |
| |
| qcom,msm-rtb { |
| compatible = "qcom,msm-rtb"; |
| qcom,memory-reservation-type = "EBI1"; |
| qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ |
| }; |
| |
| sdcc1: qcom,sdcc@f9824000 { |
| cell-index = <1>; /* SDC1 eMMC slot */ |
| compatible = "qcom,msm-sdcc"; |
| reg = <0xf9824000 0x800>; |
| reg-names = "core_mem"; |
| interrupts = <0 123 0>; |
| interrupt-names = "core_irq"; |
| |
| qcom,bus-width = <8>; |
| status = "disabled"; |
| }; |
| |
| sdcc2: qcom,sdcc@f98a4000 { |
| cell-index = <2>; /* SDC2 SD card slot */ |
| compatible = "qcom,msm-sdcc"; |
| reg = <0xf98a4000 0x800>; |
| reg-names = "core_mem"; |
| interrupts = <0 125 0>; |
| interrupt-names = "core_irq"; |
| |
| |
| qcom,bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| qcom,sps@f9980000 { |
| compatible = "qcom,msm_sps"; |
| reg = <0xf9984000 0x15000>, |
| <0xf9999000 0xb000>; |
| interrupts = <0 94 0>; |
| qcom,pipe-attr-ee; |
| }; |
| |
| spmi_bus: qcom,spmi@fc4c0000 { |
| cell-index = <0>; |
| compatible = "qcom,spmi-pmic-arb"; |
| reg-names = "core", "intr", "cnfg"; |
| reg = <0xfc4cf000 0x1000>, |
| <0Xfc4cb000 0x1000>, |
| <0Xfc4ca000 0x1000>; |
| /* 190,ee0_krait_hlos_spmi_periph_irq */ |
| /* 187,channel_0_krait_hlos_trans_done_irq */ |
| interrupts = <0 190 0>, <0 187 0>; |
| qcom,not-wakeup; |
| qcom,pmic-arb-ee = <0>; |
| qcom,pmic-arb-channel = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| }; |
| |
| i2c_0: i2c@f9925000 { /* BLSP1 QUP3 */ |
| cell-index = <0>; |
| compatible = "qcom,i2c-qup"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg-names = "qup_phys_addr"; |
| reg = <0xf9925000 0x1000>; |
| interrupt-names = "qup_err_intr"; |
| interrupts = <0 97 0>; |
| qcom,i2c-bus-freq = <100000>; |
| qcom,i2c-src-freq = <50000000>; |
| qcom,sda-gpio = <&msmgpio 10 0>; |
| qcom,scl-gpio = <&msmgpio 11 0>; |
| }; |
| |
| qcom,usbbam@f9304000 { |
| compatible = "qcom,usb-bam-msm"; |
| reg = <0xf9304000 0x5000>, |
| <0xf92f880c 0x4>; |
| reg-names = "ssusb", "qscratch_ram1_reg"; |
| interrupts = <0 132 0>; |
| interrupt-names = "ssusb"; |
| qcom,usb-bam-num-pipes = <16>; |
| qcom,usb-bam-fifo-baseaddr = <0x00000000 0xf9200000>; |
| qcom,ignore-core-reset-ack; |
| qcom,disable-clk-gating; |
| |
| qcom,pipe0 { |
| label = "ssusb-qdss-in-0"; |
| qcom,usb-bam-mem-type = <1>; |
| qcom,bam-type = <0>; |
| qcom,dir = <1>; |
| qcom,pipe-num = <0>; |
| qcom,peer-bam = <1>; |
| qcom,src-bam-physical-address = <0xfc37C000>; |
| qcom,src-bam-pipe-index = <0>; |
| qcom,dst-bam-physical-address = <0xf9304000>; |
| qcom,dst-bam-pipe-index = <2>; |
| qcom,data-fifo-offset = <0xf0000>; |
| qcom,data-fifo-size = <0x1800>; |
| qcom,descriptor-fifo-offset = <0xf4000>; |
| qcom,descriptor-fifo-size = <0x1400>; |
| qcom,reset-bam-on-connect; |
| }; |
| }; |
| |
| usb3: qcom,ssusb@f9200000 { |
| compatible = "qcom,dwc-usb3-msm"; |
| reg = <0xf9200000 0xfc000>, |
| <0xfd4ab000 0x4>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| interrupts = <0 133 0>; |
| interrupt-names = "hs_phy_irq"; |
| ssusb_vdd_dig-supply = <&pma8084_s1>; |
| SSUSB_1p8-supply = <&pma8084_l6>; |
| hsusb_vdd_dig-supply = <&pma8084_s1>; |
| HSUSB_1p8-supply = <&pma8084_l6>; |
| HSUSB_3p3-supply = <&pma8084_l24>; |
| qcom,dwc-usb3-msm-dbm-eps = <4>; |
| qcom,vdd-voltage-level = <0 900000 1050000>; |
| |
| dwc3@f9200000 { |
| compatible = "synopsys,dwc3"; |
| reg = <0xf9200000 0xfc000>; |
| interrupt-parent = <&intc>; |
| interrupts = <0 131 0>, <0 179 0>; |
| interrupt-names = "irq", "otg_irq"; |
| tx-fifo-resize; |
| }; |
| }; |
| |
| android_usb { |
| compatible = "qcom,android-usb"; |
| }; |
| |
| tsens: tsens@fc4a8000 { |
| compatible = "qcom,msm-tsens"; |
| reg = <0xfc4a8000 0x2000>, |
| <0xfc4bc000 0x1000>; |
| reg-names = "tsens_physical", "tsens_eeprom_physical"; |
| interrupts = <0 184 0>; |
| qcom,sensors = <11>; |
| qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200 |
| 3200 3200>; |
| qcom,calib-mode = "fuse_map1"; |
| }; |
| |
| qcom,ocmem@fdd00000 { |
| compatible = "qcom,msm-ocmem"; |
| reg = <0xfdd00000 0x2000>, |
| <0xfdd02000 0x2000>, |
| <0xfe039000 0x400>, |
| <0xfec00000 0x200000>; |
| reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical"; |
| interrupts = <0 76 0 0 77 0>; |
| interrupt-names = "ocmem_irq", "dm_irq"; |
| qcom,ocmem-num-regions = <0x4>; |
| qcom,ocmem-num-macros = <0x20>; |
| qcom,resource-type = <0x706d636f>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xfec00000 0x200000>; |
| |
| partition@0 { |
| reg = <0x0 0x180000>; |
| qcom,ocmem-part-name = "graphics"; |
| qcom,ocmem-part-min = <0x80000>; |
| }; |
| |
| partition@80000 { |
| reg = <0x180000 0x80000>; |
| qcom,ocmem-part-name = "lp_audio"; |
| qcom,ocmem-part-min = <0x80000>; |
| }; |
| |
| partition@100000 { |
| reg = <0x180000 0x80000>; |
| qcom,ocmem-part-name = "video"; |
| qcom,ocmem-part-min = <0x55000>; |
| }; |
| |
| }; |
| |
| memory_hole: qcom,msm-mem-hole { |
| compatible = "qcom,msm-mem-hole"; |
| qcom,memblock-remove = <0x0d200000 0x02c00000>; /* Address and Size of Hole */ |
| }; |
| |
| qcom,ipc-spinlock@fd484000 { |
| compatible = "qcom,ipc-spinlock-sfpb"; |
| reg = <0xfd484000 0x400>; |
| qcom,num-locks = <8>; |
| }; |
| |
| qcom,smem@fa00000 { |
| compatible = "qcom,smem"; |
| reg = <0xfa00000 0x200000>, |
| <0xf9011000 0x1000>, |
| <0xfc428000 0x4000>; |
| reg-names = "smem", "irq-reg-base", "aux-mem1"; |
| |
| qcom,smd-adsp { |
| compatible = "qcom,smd"; |
| qcom,smd-edge = <1>; |
| qcom,smd-irq-offset = <0x8>; |
| qcom,smd-irq-bitmask = <0x100>; |
| qcom,pil-string = "adsp"; |
| interrupts = <0 156 1>; |
| }; |
| |
| qcom,smsm-adsp { |
| compatible = "qcom,smsm"; |
| qcom,smsm-edge = <1>; |
| qcom,smsm-irq-offset = <0x8>; |
| qcom,smsm-irq-bitmask = <0x200>; |
| interrupts = <0 157 1>; |
| }; |
| |
| qcom,smd-rpm { |
| compatible = "qcom,smd"; |
| qcom,smd-edge = <15>; |
| qcom,smd-irq-offset = <0x8>; |
| qcom,smd-irq-bitmask = <0x1>; |
| interrupts = <0 168 1>; |
| qcom,irq-no-suspend; |
| }; |
| }; |
| |
| qcom,venus@fdce0000 { |
| compatible = "qcom,pil-venus"; |
| reg = <0xfdce0000 0x4000>, |
| <0xfdc80000 0x400>; |
| reg-names = "wrapper_base", "vbif_base"; |
| vdd-supply = <&gdsc_venus>; |
| |
| qcom,firmware-name = "venus"; |
| }; |
| |
| ufs1: ufshc@0xfc598000 { |
| compatible = "jedec,ufs-1.1"; |
| reg = <0xfc598000 0x800>; |
| interrupts = <0 28 0>; |
| status = "disabled"; |
| }; |
| |
| qcom,wdt@f9017000 { |
| compatible = "qcom,msm-watchdog"; |
| reg = <0xf9017000 0x1000>; |
| interrupts = <0 3 0>, <0 4 0>; |
| qcom,bark-time = <11000>; |
| qcom,pet-time = <10000>; |
| qcom,ipi-ping; |
| }; |
| |
| qcom,msm-rng@f9bff000{ |
| compatible = "qcom,msm-rng"; |
| reg = <0xf9bff000 0x200>; |
| qcom,msm-rng-iface-clk; |
| }; |
| }; |
| |
| &gdsc_venus { |
| status = "ok"; |
| }; |
| |
| &gdsc_venus_core0 { |
| status = "ok"; |
| }; |
| |
| &gdsc_venus_core1 { |
| status = "ok"; |
| }; |
| |
| &gdsc_vpu { |
| status = "ok"; |
| }; |
| |
| &gdsc_mdss { |
| status = "ok"; |
| }; |
| |
| &gdsc_jpeg { |
| status = "ok"; |
| }; |
| |
| &gdsc_vfe { |
| status = "ok"; |
| }; |
| |
| &gdsc_oxili_gx { |
| status = "ok"; |
| }; |
| |
| &gdsc_oxili_cx { |
| status = "ok"; |
| }; |
| |
| &gdsc_usb_hsic { |
| status = "ok"; |
| }; |
| |
| &gdsc_pcie_0{ |
| status = "ok"; |
| }; |
| |
| &gdsc_pcie_1{ |
| status = "ok"; |
| }; |
| |
| &gdsc_usb30{ |
| status = "ok"; |
| }; |
| |
| &gdsc_usb30_sec{ |
| status = "ok"; |
| }; |
| |
| /include/ "msm-pma8084.dtsi" |
| /include/ "apq8084-regulator.dtsi" |
| |
| &pma8084_vadc { |
| chan@b0 { |
| label = "apq_therm"; |
| reg = <0xb0>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <0>; |
| qcom,calibration-type = "ratiometric"; |
| qcom,scale-function = <2>; |
| qcom,hw-settle-time = <2>; |
| qcom,fast-avg-setup = <0>; |
| }; |
| |
| chan@b3 { |
| label = "quiet_therm"; |
| reg = <0xb3>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <0>; |
| qcom,calibration-type = "ratiometric"; |
| qcom,scale-function = <2>; |
| qcom,hw-settle-time = <2>; |
| qcom,fast-avg-setup = <0>; |
| }; |
| }; |
| |
| &pma8084_adc_tm { |
| chan@8 { |
| label = "die_temp"; |
| reg = <8>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <0>; |
| qcom,calibration-type = "absolute"; |
| qcom,scale-function = <3>; |
| qcom,hw-settle-time = <0>; |
| qcom,fast-avg-setup = <3>; |
| qcom,btm-channel-number = <0x48>; |
| }; |
| |
| chan@b0 { |
| label = "apq_therm"; |
| reg = <0xb0>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <0>; |
| qcom,calibration-type = "ratiometric"; |
| qcom,scale-function = <2>; |
| qcom,hw-settle-time = <2>; |
| qcom,fast-avg-setup = <3>; |
| qcom,btm-channel-number = <0x68>; |
| qcom,thermal-node; |
| }; |
| |
| chan@b3 { |
| label = "quiet_therm"; |
| reg = <0xb3>; |
| qcom,decimation = <0>; |
| qcom,pre-div-channel-scaling = <0>; |
| qcom,calibration-type = "ratiometric"; |
| qcom,scale-function = <2>; |
| qcom,hw-settle-time = <2>; |
| qcom,fast-avg-setup = <3>; |
| qcom,btm-channel-number = <0x70>; |
| qcom,thermal-node; |
| }; |
| }; |