blob: 8eed58ef820f10c304e038638cfd6d2beb314554 [file] [log] [blame]
Stepan Moskovchenko632d4162013-01-24 16:00:08 -08001/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
Stepan Moskovchenko920a1012013-04-26 14:34:14 -070013/include/ "skeleton64.dtsi"
Stepan Moskovchenko632d4162013-01-24 16:00:08 -080014
15/ {
Stepan Moskovchenkoe90cd652013-04-18 12:54:47 -070016 model = "Qualcomm APQ 8084";
17 compatible = "qcom,apq8084";
Stepan Moskovchenko632d4162013-01-24 16:00:08 -080018 interrupt-parent = <&intc>;
Stepan Moskovchenko7d8cdcaa2013-04-25 17:10:55 -070019 soc: soc { };
20};
21
Tianyi Gou81f5a712013-06-21 11:18:54 -070022/include/ "msm-gdsc.dtsi"
Stepan Moskovchenko7d8cdcaa2013-04-25 17:10:55 -070023/include/ "apq8084-ion.dtsi"
Olav Haugan04b4c9d2013-04-06 10:30:49 -070024/include/ "apq8084-iommu.dtsi"
Jeff Hugo94686722013-05-17 17:37:33 -060025/include/ "apq8084-smp2p.dtsi"
Pushkar Joshi3acc46f2013-06-14 16:39:40 -070026/include/ "apq8084-coresight.dtsi"
Shalabh Jain51a0bf62013-05-28 17:32:15 -070027/include/ "apq8084-mdss.dtsi"
liu zhong190bb212013-04-19 19:29:51 -070028/include/ "apq8084-gpu.dtsi"
Stepan Moskovchenko7d8cdcaa2013-04-25 17:10:55 -070029
30&soc {
31 #address-cells = <1>;
32 #size-cells = <1>;
Stepan Moskovchenko920a1012013-04-26 14:34:14 -070033 ranges = <0 0 0 0xffffffff>;
Stepan Moskovchenko632d4162013-01-24 16:00:08 -080034
35 intc: interrupt-controller@f9000000 {
36 compatible = "qcom,msm-qgic2";
37 interrupt-controller;
38 #interrupt-cells = <3>;
39 reg = <0xF9000000 0x1000>,
40 <0xF9002000 0x1000>;
41 };
42
43 msmgpio: gpio@fd510000 {
44 compatible = "qcom,msm-gpio";
45 gpio-controller;
46 #gpio-cells = <2>;
47 interrupt-controller;
48 #interrupt-cells = <2>;
49 reg = <0xfd510000 0x4000>;
50 ngpio = <146>;
51 interrupts = <0 208 0>;
52 qcom,direct-connect-irqs = <8>;
53 };
54
55 timer {
56 compatible = "arm,armv7-timer";
57 interrupts = <1 2 0 1 3 0>;
58 clock-frequency = <19200000>;
59 };
60
61 serial@f991f000 {
62 compatible = "qcom,msm-lsuart-v14";
63 reg = <0xf991f000 0x1000>;
64 interrupts = <0 109 0>;
65 status = "disabled";
66 };
67
68 qcom,cache_erp {
69 compatible = "qcom,cache_erp";
70 interrupts = <1 9 0>, <0 2 0>;
71 interrupt-names = "l1_irq", "l2_irq";
72 };
73
74 qcom,cache_dump {
75 compatible = "qcom,cache_dump";
76 qcom,l1-dump-size = <0x100000>;
77 qcom,l2-dump-size = <0x500000>;
Stepan Moskovchenko632d4162013-01-24 16:00:08 -080078 };
79
80 rpm_bus: qcom,rpm-smd {
81 compatible = "qcom,rpm-smd";
82 rpm-channel-name = "rpm_requests";
83 rpm-channel-type = <15>; /* SMD_APPS_RPM */
84 rpm-standalone;
85 };
86
Stepan Moskovchenkob8dd6a92013-03-18 18:53:34 -070087 qcom,msm-imem@fe805000 {
88 compatible = "qcom,msm-imem";
89 reg = <0xfe805000 0x1000>; /* Address and size of IMEM */
Laura Abbott2fd1fc62013-03-05 14:30:47 -080090 };
91
92 qcom,msm-rtb {
93 compatible = "qcom,msm-rtb";
94 qcom,memory-reservation-type = "EBI1";
95 qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */
96 };
Stepan Moskovchenkob8dd6a92013-03-18 18:53:34 -070097
Venkat Gopalakrishnand7ba4e32013-03-29 19:51:19 -070098 sdcc1: qcom,sdcc@f9824000 {
99 cell-index = <1>; /* SDC1 eMMC slot */
100 compatible = "qcom,msm-sdcc";
101 reg = <0xf9824000 0x800>;
102 reg-names = "core_mem";
103 interrupts = <0 123 0>;
104 interrupt-names = "core_irq";
105
106 qcom,bus-width = <8>;
107 status = "disabled";
108 };
109
110 sdcc2: qcom,sdcc@f98a4000 {
111 cell-index = <2>; /* SDC2 SD card slot */
112 compatible = "qcom,msm-sdcc";
113 reg = <0xf98a4000 0x800>;
114 reg-names = "core_mem";
115 interrupts = <0 125 0>;
116 interrupt-names = "core_irq";
117
118
119 qcom,bus-width = <4>;
120 status = "disabled";
121 };
Kenneth Heitke72e12c02013-04-22 17:30:58 -0600122
Yan He43173652013-06-05 17:52:41 -0700123 qcom,sps@f9980000 {
124 compatible = "qcom,msm_sps";
125 reg = <0xf9984000 0x15000>,
126 <0xf9999000 0xb000>;
127 interrupts = <0 94 0>;
128 qcom,pipe-attr-ee;
129 };
130
Kenneth Heitke72e12c02013-04-22 17:30:58 -0600131 spmi_bus: qcom,spmi@fc4c0000 {
132 cell-index = <0>;
133 compatible = "qcom,spmi-pmic-arb";
134 reg-names = "core", "intr", "cnfg";
135 reg = <0xfc4cf000 0x1000>,
136 <0Xfc4cb000 0x1000>,
137 <0Xfc4ca000 0x1000>;
138 /* 190,ee0_krait_hlos_spmi_periph_irq */
139 /* 187,channel_0_krait_hlos_trans_done_irq */
140 interrupts = <0 190 0>, <0 187 0>;
141 qcom,not-wakeup;
142 qcom,pmic-arb-ee = <0>;
143 qcom,pmic-arb-channel = <0>;
144 #address-cells = <1>;
145 #size-cells = <0>;
146 interrupt-controller;
147 #interrupt-cells = <3>;
148 };
Hemant Kumar303c9412013-04-19 12:33:31 -0700149
Gilad Avidovc3bbe602013-05-16 17:17:13 -0600150 i2c_0: i2c@f9925000 { /* BLSP1 QUP3 */
151 cell-index = <0>;
152 compatible = "qcom,i2c-qup";
153 #address-cells = <1>;
154 #size-cells = <0>;
155 reg-names = "qup_phys_addr";
156 reg = <0xf9925000 0x1000>;
157 interrupt-names = "qup_err_intr";
158 interrupts = <0 97 0>;
159 qcom,i2c-bus-freq = <100000>;
160 qcom,i2c-src-freq = <50000000>;
161 qcom,sda-gpio = <&msmgpio 10 0>;
162 qcom,scl-gpio = <&msmgpio 11 0>;
163 };
164
Hemant Kumar48d4c9d2013-07-02 19:13:23 -0700165 qcom,usbbam@f9304000 {
166 compatible = "qcom,usb-bam-msm";
167 reg = <0xf9304000 0x5000>,
168 <0xf92f880c 0x4>;
169 reg-names = "ssusb", "qscratch_ram1_reg";
170 interrupts = <0 132 0>;
171 interrupt-names = "ssusb";
172 qcom,usb-bam-num-pipes = <16>;
173 qcom,usb-bam-fifo-baseaddr = <0x00000000 0xf9200000>;
174 qcom,ignore-core-reset-ack;
175 qcom,disable-clk-gating;
176
177 qcom,pipe0 {
178 label = "ssusb-qdss-in-0";
179 qcom,usb-bam-mem-type = <1>;
180 qcom,bam-type = <0>;
181 qcom,dir = <1>;
182 qcom,pipe-num = <0>;
183 qcom,peer-bam = <1>;
184 qcom,src-bam-physical-address = <0xfc37C000>;
185 qcom,src-bam-pipe-index = <0>;
186 qcom,dst-bam-physical-address = <0xf9304000>;
187 qcom,dst-bam-pipe-index = <2>;
188 qcom,data-fifo-offset = <0xf0000>;
189 qcom,data-fifo-size = <0x1800>;
190 qcom,descriptor-fifo-offset = <0xf4000>;
191 qcom,descriptor-fifo-size = <0x1400>;
192 qcom,reset-bam-on-connect;
193 };
194 };
195
Hemant Kumar303c9412013-04-19 12:33:31 -0700196 usb3: qcom,ssusb@f9200000 {
197 compatible = "qcom,dwc-usb3-msm";
198 reg = <0xf9200000 0xfc000>,
199 <0xfd4ab000 0x4>;
200 #address-cells = <1>;
201 #size-cells = <1>;
202 ranges;
203 interrupts = <0 133 0>;
204 interrupt-names = "hs_phy_irq";
205 ssusb_vdd_dig-supply = <&pma8084_s1>;
206 SSUSB_1p8-supply = <&pma8084_l6>;
207 hsusb_vdd_dig-supply = <&pma8084_s1>;
208 HSUSB_1p8-supply = <&pma8084_l6>;
209 HSUSB_3p3-supply = <&pma8084_l24>;
210 qcom,dwc-usb3-msm-dbm-eps = <4>;
211 qcom,vdd-voltage-level = <0 900000 1050000>;
212
213 dwc3@f9200000 {
214 compatible = "synopsys,dwc3";
215 reg = <0xf9200000 0xfc000>;
216 interrupt-parent = <&intc>;
217 interrupts = <0 131 0>, <0 179 0>;
218 interrupt-names = "irq", "otg_irq";
219 tx-fifo-resize;
220 };
221 };
222
223 android_usb {
224 compatible = "qcom,android-usb";
225 };
Neeti Desai3db510c2013-04-29 14:31:31 -0700226
Siddartha Mohanadoss6ee10912013-05-16 08:07:08 -0700227 tsens: tsens@fc4a8000 {
228 compatible = "qcom,msm-tsens";
229 reg = <0xfc4a8000 0x2000>,
Siddartha Mohanadoss6ddc1922013-07-08 17:40:11 -0700230 <0xfc4bc000 0x1000>;
Siddartha Mohanadoss6ee10912013-05-16 08:07:08 -0700231 reg-names = "tsens_physical", "tsens_eeprom_physical";
232 interrupts = <0 184 0>;
233 qcom,sensors = <11>;
234 qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 3200
235 3200 3200>;
236 qcom,calib-mode = "fuse_map1";
237 };
238
Neeti Desai3db510c2013-04-29 14:31:31 -0700239 qcom,ocmem@fdd00000 {
240 compatible = "qcom,msm-ocmem";
241 reg = <0xfdd00000 0x2000>,
242 <0xfdd02000 0x2000>,
243 <0xfe039000 0x400>,
244 <0xfec00000 0x200000>;
245 reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
246 interrupts = <0 76 0 0 77 0>;
247 interrupt-names = "ocmem_irq", "dm_irq";
248 qcom,ocmem-num-regions = <0x4>;
249 qcom,ocmem-num-macros = <0x20>;
250 qcom,resource-type = <0x706d636f>;
251 #address-cells = <1>;
252 #size-cells = <1>;
253 ranges = <0x0 0xfec00000 0x200000>;
254
255 partition@0 {
256 reg = <0x0 0x180000>;
257 qcom,ocmem-part-name = "graphics";
258 qcom,ocmem-part-min = <0x80000>;
259 };
260
261 partition@80000 {
262 reg = <0x180000 0x80000>;
263 qcom,ocmem-part-name = "lp_audio";
264 qcom,ocmem-part-min = <0x80000>;
265 };
266
267 partition@100000 {
268 reg = <0x180000 0x80000>;
269 qcom,ocmem-part-name = "video";
270 qcom,ocmem-part-min = <0x55000>;
271 };
272
273 };
Laura Abbott8fadcbc2013-05-17 17:44:16 -0700274
275 memory_hole: qcom,msm-mem-hole {
276 compatible = "qcom,msm-mem-hole";
Laura Abbott15133472013-07-02 14:30:43 -0700277 qcom,memblock-remove = <0x0d200000 0x02c00000>; /* Address and Size of Hole */
Laura Abbott8fadcbc2013-05-17 17:44:16 -0700278 };
Jeff Hugo762c2cd2013-05-17 13:25:36 -0600279
280 qcom,ipc-spinlock@fd484000 {
281 compatible = "qcom,ipc-spinlock-sfpb";
282 reg = <0xfd484000 0x400>;
283 qcom,num-locks = <8>;
284 };
Jeff Hugoa1d67b32013-05-17 17:26:34 -0600285
286 qcom,smem@fa00000 {
287 compatible = "qcom,smem";
288 reg = <0xfa00000 0x200000>,
289 <0xf9011000 0x1000>,
290 <0xfc428000 0x4000>;
291 reg-names = "smem", "irq-reg-base", "aux-mem1";
292
293 qcom,smd-adsp {
294 compatible = "qcom,smd";
295 qcom,smd-edge = <1>;
296 qcom,smd-irq-offset = <0x8>;
297 qcom,smd-irq-bitmask = <0x100>;
298 qcom,pil-string = "adsp";
299 interrupts = <0 156 1>;
300 };
301
302 qcom,smsm-adsp {
303 compatible = "qcom,smsm";
304 qcom,smsm-edge = <1>;
305 qcom,smsm-irq-offset = <0x8>;
306 qcom,smsm-irq-bitmask = <0x200>;
307 interrupts = <0 157 1>;
308 };
309
310 qcom,smd-rpm {
311 compatible = "qcom,smd";
312 qcom,smd-edge = <15>;
313 qcom,smd-irq-offset = <0x8>;
314 qcom,smd-irq-bitmask = <0x1>;
315 interrupts = <0 168 1>;
316 qcom,irq-no-suspend;
317 };
318 };
Tianyi Gou81f5a712013-06-21 11:18:54 -0700319
320 qcom,venus@fdce0000 {
321 compatible = "qcom,pil-venus";
322 reg = <0xfdce0000 0x4000>,
323 <0xfdc80000 0x400>;
324 reg-names = "wrapper_base", "vbif_base";
325 vdd-supply = <&gdsc_venus>;
326
327 qcom,firmware-name = "venus";
328 };
Sujit Reddy Thumma363a8152013-05-10 10:29:18 +0530329
330 ufs1: ufshc@0xfc598000 {
331 compatible = "jedec,ufs-1.1";
332 reg = <0xfc598000 0x800>;
333 interrupts = <0 28 0>;
334 status = "disabled";
335 };
Pushkar Joshi1520c362013-07-17 10:11:33 -0700336
337 qcom,wdt@f9017000 {
338 compatible = "qcom,msm-watchdog";
339 reg = <0xf9017000 0x1000>;
340 interrupts = <0 3 0>, <0 4 0>;
341 qcom,bark-time = <11000>;
342 qcom,pet-time = <10000>;
343 qcom,ipi-ping;
344 };
Hariprasad Dhalinarasimha680c31f2013-07-05 11:59:40 -0700345
346 qcom,msm-rng@f9bff000{
347 compatible = "qcom,msm-rng";
348 reg = <0xf9bff000 0x200>;
349 qcom,msm-rng-iface-clk;
350 };
Stepan Moskovchenko632d4162013-01-24 16:00:08 -0800351};
David Collinsce8b1162013-04-23 09:01:57 -0700352
Tianyi Gouea04f0c2013-05-31 16:45:46 -0700353&gdsc_venus {
354 status = "ok";
355};
356
357&gdsc_venus_core0 {
358 status = "ok";
359};
360
361&gdsc_venus_core1 {
362 status = "ok";
363};
364
365&gdsc_vpu {
366 status = "ok";
367};
368
369&gdsc_mdss {
370 status = "ok";
371};
372
373&gdsc_jpeg {
374 status = "ok";
375};
376
377&gdsc_vfe {
378 status = "ok";
379};
380
381&gdsc_oxili_gx {
382 status = "ok";
383};
384
385&gdsc_oxili_cx {
386 status = "ok";
387};
388
389&gdsc_usb_hsic {
390 status = "ok";
391};
392
393&gdsc_pcie_0{
394 status = "ok";
395};
396
397&gdsc_pcie_1{
398 status = "ok";
399};
400
401&gdsc_usb30{
402 status = "ok";
403};
404
405&gdsc_usb30_sec{
406 status = "ok";
407};
408
David Collinsce8b1162013-04-23 09:01:57 -0700409/include/ "msm-pma8084.dtsi"
David Collinsb8e4fe52013-04-23 09:04:30 -0700410/include/ "apq8084-regulator.dtsi"
Siddartha Mohanadoss6298e992013-05-16 08:38:36 -0700411
412&pma8084_vadc {
413 chan@b0 {
414 label = "apq_therm";
415 reg = <0xb0>;
416 qcom,decimation = <0>;
417 qcom,pre-div-channel-scaling = <0>;
418 qcom,calibration-type = "ratiometric";
419 qcom,scale-function = <2>;
420 qcom,hw-settle-time = <2>;
421 qcom,fast-avg-setup = <0>;
422 };
423
424 chan@b3 {
425 label = "quiet_therm";
426 reg = <0xb3>;
427 qcom,decimation = <0>;
428 qcom,pre-div-channel-scaling = <0>;
429 qcom,calibration-type = "ratiometric";
430 qcom,scale-function = <2>;
431 qcom,hw-settle-time = <2>;
432 qcom,fast-avg-setup = <0>;
433 };
434};
435
436&pma8084_adc_tm {
437 chan@8 {
438 label = "die_temp";
439 reg = <8>;
440 qcom,decimation = <0>;
441 qcom,pre-div-channel-scaling = <0>;
442 qcom,calibration-type = "absolute";
443 qcom,scale-function = <3>;
444 qcom,hw-settle-time = <0>;
445 qcom,fast-avg-setup = <3>;
446 qcom,btm-channel-number = <0x48>;
447 };
448
449 chan@b0 {
450 label = "apq_therm";
451 reg = <0xb0>;
452 qcom,decimation = <0>;
453 qcom,pre-div-channel-scaling = <0>;
454 qcom,calibration-type = "ratiometric";
455 qcom,scale-function = <2>;
456 qcom,hw-settle-time = <2>;
457 qcom,fast-avg-setup = <3>;
458 qcom,btm-channel-number = <0x68>;
459 qcom,thermal-node;
460 };
461
462 chan@b3 {
463 label = "quiet_therm";
464 reg = <0xb3>;
465 qcom,decimation = <0>;
466 qcom,pre-div-channel-scaling = <0>;
467 qcom,calibration-type = "ratiometric";
468 qcom,scale-function = <2>;
469 qcom,hw-settle-time = <2>;
470 qcom,fast-avg-setup = <3>;
471 qcom,btm-channel-number = <0x70>;
472 qcom,thermal-node;
473 };
474};