Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 34 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 35 | #include <linux/pci.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 36 | |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 37 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
| 38 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 39 | static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); |
| 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
| 41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 42 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
| 43 | int write); |
| 44 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 45 | uint64_t offset, |
| 46 | uint64_t size); |
| 47 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 48 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 49 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
| 50 | unsigned alignment); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 51 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 52 | static int i915_gem_evict_something(struct drm_device *dev, int min_size); |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 53 | static int i915_gem_evict_from_inactive_list(struct drm_device *dev); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 54 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 55 | struct drm_i915_gem_pwrite *args, |
| 56 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 57 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 58 | static LIST_HEAD(shrink_list); |
| 59 | static DEFINE_SPINLOCK(shrink_list_lock); |
| 60 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 61 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
| 62 | unsigned long end) |
| 63 | { |
| 64 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 65 | |
| 66 | if (start >= end || |
| 67 | (start & (PAGE_SIZE - 1)) != 0 || |
| 68 | (end & (PAGE_SIZE - 1)) != 0) { |
| 69 | return -EINVAL; |
| 70 | } |
| 71 | |
| 72 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
| 73 | end - start); |
| 74 | |
| 75 | dev->gtt_total = (uint32_t) (end - start); |
| 76 | |
| 77 | return 0; |
| 78 | } |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 79 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 80 | int |
| 81 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 82 | struct drm_file *file_priv) |
| 83 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 84 | struct drm_i915_gem_init *args = data; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 85 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 86 | |
| 87 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 88 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 89 | mutex_unlock(&dev->struct_mutex); |
| 90 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 91 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 92 | } |
| 93 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 94 | int |
| 95 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 96 | struct drm_file *file_priv) |
| 97 | { |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 98 | struct drm_i915_gem_get_aperture *args = data; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 99 | |
| 100 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 101 | return -ENODEV; |
| 102 | |
| 103 | args->aper_size = dev->gtt_total; |
Keith Packard | 2678d9d | 2008-11-20 22:54:54 -0800 | [diff] [blame] | 104 | args->aper_available_size = (args->aper_size - |
| 105 | atomic_read(&dev->pin_memory)); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 106 | |
| 107 | return 0; |
| 108 | } |
| 109 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 110 | |
| 111 | /** |
| 112 | * Creates a new mm object and returns a handle to it. |
| 113 | */ |
| 114 | int |
| 115 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 116 | struct drm_file *file_priv) |
| 117 | { |
| 118 | struct drm_i915_gem_create *args = data; |
| 119 | struct drm_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 120 | int ret; |
| 121 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 122 | |
| 123 | args->size = roundup(args->size, PAGE_SIZE); |
| 124 | |
| 125 | /* Allocate the new object */ |
| 126 | obj = drm_gem_object_alloc(dev, args->size); |
| 127 | if (obj == NULL) |
| 128 | return -ENOMEM; |
| 129 | |
| 130 | ret = drm_gem_handle_create(file_priv, obj, &handle); |
| 131 | mutex_lock(&dev->struct_mutex); |
| 132 | drm_gem_object_handle_unreference(obj); |
| 133 | mutex_unlock(&dev->struct_mutex); |
| 134 | |
| 135 | if (ret) |
| 136 | return ret; |
| 137 | |
| 138 | args->handle = handle; |
| 139 | |
| 140 | return 0; |
| 141 | } |
| 142 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 143 | static inline int |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 144 | fast_shmem_read(struct page **pages, |
| 145 | loff_t page_base, int page_offset, |
| 146 | char __user *data, |
| 147 | int length) |
| 148 | { |
| 149 | char __iomem *vaddr; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 150 | int unwritten; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 151 | |
| 152 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); |
| 153 | if (vaddr == NULL) |
| 154 | return -ENOMEM; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 155 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 156 | kunmap_atomic(vaddr, KM_USER0); |
| 157 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 158 | if (unwritten) |
| 159 | return -EFAULT; |
| 160 | |
| 161 | return 0; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 162 | } |
| 163 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 164 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
| 165 | { |
| 166 | drm_i915_private_t *dev_priv = obj->dev->dev_private; |
| 167 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 168 | |
| 169 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 170 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 171 | } |
| 172 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 173 | static inline int |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 174 | slow_shmem_copy(struct page *dst_page, |
| 175 | int dst_offset, |
| 176 | struct page *src_page, |
| 177 | int src_offset, |
| 178 | int length) |
| 179 | { |
| 180 | char *dst_vaddr, *src_vaddr; |
| 181 | |
| 182 | dst_vaddr = kmap_atomic(dst_page, KM_USER0); |
| 183 | if (dst_vaddr == NULL) |
| 184 | return -ENOMEM; |
| 185 | |
| 186 | src_vaddr = kmap_atomic(src_page, KM_USER1); |
| 187 | if (src_vaddr == NULL) { |
| 188 | kunmap_atomic(dst_vaddr, KM_USER0); |
| 189 | return -ENOMEM; |
| 190 | } |
| 191 | |
| 192 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
| 193 | |
| 194 | kunmap_atomic(src_vaddr, KM_USER1); |
| 195 | kunmap_atomic(dst_vaddr, KM_USER0); |
| 196 | |
| 197 | return 0; |
| 198 | } |
| 199 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 200 | static inline int |
| 201 | slow_shmem_bit17_copy(struct page *gpu_page, |
| 202 | int gpu_offset, |
| 203 | struct page *cpu_page, |
| 204 | int cpu_offset, |
| 205 | int length, |
| 206 | int is_read) |
| 207 | { |
| 208 | char *gpu_vaddr, *cpu_vaddr; |
| 209 | |
| 210 | /* Use the unswizzled path if this page isn't affected. */ |
| 211 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
| 212 | if (is_read) |
| 213 | return slow_shmem_copy(cpu_page, cpu_offset, |
| 214 | gpu_page, gpu_offset, length); |
| 215 | else |
| 216 | return slow_shmem_copy(gpu_page, gpu_offset, |
| 217 | cpu_page, cpu_offset, length); |
| 218 | } |
| 219 | |
| 220 | gpu_vaddr = kmap_atomic(gpu_page, KM_USER0); |
| 221 | if (gpu_vaddr == NULL) |
| 222 | return -ENOMEM; |
| 223 | |
| 224 | cpu_vaddr = kmap_atomic(cpu_page, KM_USER1); |
| 225 | if (cpu_vaddr == NULL) { |
| 226 | kunmap_atomic(gpu_vaddr, KM_USER0); |
| 227 | return -ENOMEM; |
| 228 | } |
| 229 | |
| 230 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
| 231 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
| 232 | */ |
| 233 | while (length > 0) { |
| 234 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 235 | int this_length = min(cacheline_end - gpu_offset, length); |
| 236 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 237 | |
| 238 | if (is_read) { |
| 239 | memcpy(cpu_vaddr + cpu_offset, |
| 240 | gpu_vaddr + swizzled_gpu_offset, |
| 241 | this_length); |
| 242 | } else { |
| 243 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
| 244 | cpu_vaddr + cpu_offset, |
| 245 | this_length); |
| 246 | } |
| 247 | cpu_offset += this_length; |
| 248 | gpu_offset += this_length; |
| 249 | length -= this_length; |
| 250 | } |
| 251 | |
| 252 | kunmap_atomic(cpu_vaddr, KM_USER1); |
| 253 | kunmap_atomic(gpu_vaddr, KM_USER0); |
| 254 | |
| 255 | return 0; |
| 256 | } |
| 257 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 258 | /** |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 259 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
| 260 | * from the backing pages of the object to the user's address space. On a |
| 261 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
| 262 | */ |
| 263 | static int |
| 264 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 265 | struct drm_i915_gem_pread *args, |
| 266 | struct drm_file *file_priv) |
| 267 | { |
| 268 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 269 | ssize_t remain; |
| 270 | loff_t offset, page_base; |
| 271 | char __user *user_data; |
| 272 | int page_offset, page_length; |
| 273 | int ret; |
| 274 | |
| 275 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 276 | remain = args->size; |
| 277 | |
| 278 | mutex_lock(&dev->struct_mutex); |
| 279 | |
| 280 | ret = i915_gem_object_get_pages(obj); |
| 281 | if (ret != 0) |
| 282 | goto fail_unlock; |
| 283 | |
| 284 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, |
| 285 | args->size); |
| 286 | if (ret != 0) |
| 287 | goto fail_put_pages; |
| 288 | |
| 289 | obj_priv = obj->driver_private; |
| 290 | offset = args->offset; |
| 291 | |
| 292 | while (remain > 0) { |
| 293 | /* Operation in this page |
| 294 | * |
| 295 | * page_base = page offset within aperture |
| 296 | * page_offset = offset within page |
| 297 | * page_length = bytes to copy for this page |
| 298 | */ |
| 299 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 300 | page_offset = offset & (PAGE_SIZE-1); |
| 301 | page_length = remain; |
| 302 | if ((page_offset + remain) > PAGE_SIZE) |
| 303 | page_length = PAGE_SIZE - page_offset; |
| 304 | |
| 305 | ret = fast_shmem_read(obj_priv->pages, |
| 306 | page_base, page_offset, |
| 307 | user_data, page_length); |
| 308 | if (ret) |
| 309 | goto fail_put_pages; |
| 310 | |
| 311 | remain -= page_length; |
| 312 | user_data += page_length; |
| 313 | offset += page_length; |
| 314 | } |
| 315 | |
| 316 | fail_put_pages: |
| 317 | i915_gem_object_put_pages(obj); |
| 318 | fail_unlock: |
| 319 | mutex_unlock(&dev->struct_mutex); |
| 320 | |
| 321 | return ret; |
| 322 | } |
| 323 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 324 | static inline gfp_t |
| 325 | i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj) |
| 326 | { |
| 327 | return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping); |
| 328 | } |
| 329 | |
| 330 | static inline void |
| 331 | i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp) |
| 332 | { |
| 333 | mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp); |
| 334 | } |
| 335 | |
| 336 | static int |
| 337 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) |
| 338 | { |
| 339 | int ret; |
| 340 | |
| 341 | ret = i915_gem_object_get_pages(obj); |
| 342 | |
| 343 | /* If we've insufficient memory to map in the pages, attempt |
| 344 | * to make some space by throwing out some old buffers. |
| 345 | */ |
| 346 | if (ret == -ENOMEM) { |
| 347 | struct drm_device *dev = obj->dev; |
| 348 | gfp_t gfp; |
| 349 | |
| 350 | ret = i915_gem_evict_something(dev, obj->size); |
| 351 | if (ret) |
| 352 | return ret; |
| 353 | |
| 354 | gfp = i915_gem_object_get_page_gfp_mask(obj); |
| 355 | i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY); |
| 356 | ret = i915_gem_object_get_pages(obj); |
| 357 | i915_gem_object_set_page_gfp_mask (obj, gfp); |
| 358 | } |
| 359 | |
| 360 | return ret; |
| 361 | } |
| 362 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 363 | /** |
| 364 | * This is the fallback shmem pread path, which allocates temporary storage |
| 365 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
| 366 | * can copy out of the object's backing pages while holding the struct mutex |
| 367 | * and not take page faults. |
| 368 | */ |
| 369 | static int |
| 370 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 371 | struct drm_i915_gem_pread *args, |
| 372 | struct drm_file *file_priv) |
| 373 | { |
| 374 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 375 | struct mm_struct *mm = current->mm; |
| 376 | struct page **user_pages; |
| 377 | ssize_t remain; |
| 378 | loff_t offset, pinned_pages, i; |
| 379 | loff_t first_data_page, last_data_page, num_pages; |
| 380 | int shmem_page_index, shmem_page_offset; |
| 381 | int data_page_index, data_page_offset; |
| 382 | int page_length; |
| 383 | int ret; |
| 384 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 385 | int do_bit17_swizzling; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 386 | |
| 387 | remain = args->size; |
| 388 | |
| 389 | /* Pin the user pages containing the data. We can't fault while |
| 390 | * holding the struct mutex, yet we want to hold it while |
| 391 | * dereferencing the user data. |
| 392 | */ |
| 393 | first_data_page = data_ptr / PAGE_SIZE; |
| 394 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 395 | num_pages = last_data_page - first_data_page + 1; |
| 396 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 397 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 398 | if (user_pages == NULL) |
| 399 | return -ENOMEM; |
| 400 | |
| 401 | down_read(&mm->mmap_sem); |
| 402 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
Eric Anholt | e5e9ecd | 2009-04-07 16:01:22 -0700 | [diff] [blame] | 403 | num_pages, 1, 0, user_pages, NULL); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 404 | up_read(&mm->mmap_sem); |
| 405 | if (pinned_pages < num_pages) { |
| 406 | ret = -EFAULT; |
| 407 | goto fail_put_user_pages; |
| 408 | } |
| 409 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 410 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 411 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 412 | mutex_lock(&dev->struct_mutex); |
| 413 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 414 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 415 | if (ret) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 416 | goto fail_unlock; |
| 417 | |
| 418 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, |
| 419 | args->size); |
| 420 | if (ret != 0) |
| 421 | goto fail_put_pages; |
| 422 | |
| 423 | obj_priv = obj->driver_private; |
| 424 | offset = args->offset; |
| 425 | |
| 426 | while (remain > 0) { |
| 427 | /* Operation in this page |
| 428 | * |
| 429 | * shmem_page_index = page number within shmem file |
| 430 | * shmem_page_offset = offset within page in shmem file |
| 431 | * data_page_index = page number in get_user_pages return |
| 432 | * data_page_offset = offset with data_page_index page. |
| 433 | * page_length = bytes to copy for this page |
| 434 | */ |
| 435 | shmem_page_index = offset / PAGE_SIZE; |
| 436 | shmem_page_offset = offset & ~PAGE_MASK; |
| 437 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 438 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 439 | |
| 440 | page_length = remain; |
| 441 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 442 | page_length = PAGE_SIZE - shmem_page_offset; |
| 443 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 444 | page_length = PAGE_SIZE - data_page_offset; |
| 445 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 446 | if (do_bit17_swizzling) { |
| 447 | ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
| 448 | shmem_page_offset, |
| 449 | user_pages[data_page_index], |
| 450 | data_page_offset, |
| 451 | page_length, |
| 452 | 1); |
| 453 | } else { |
| 454 | ret = slow_shmem_copy(user_pages[data_page_index], |
| 455 | data_page_offset, |
| 456 | obj_priv->pages[shmem_page_index], |
| 457 | shmem_page_offset, |
| 458 | page_length); |
| 459 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 460 | if (ret) |
| 461 | goto fail_put_pages; |
| 462 | |
| 463 | remain -= page_length; |
| 464 | data_ptr += page_length; |
| 465 | offset += page_length; |
| 466 | } |
| 467 | |
| 468 | fail_put_pages: |
| 469 | i915_gem_object_put_pages(obj); |
| 470 | fail_unlock: |
| 471 | mutex_unlock(&dev->struct_mutex); |
| 472 | fail_put_user_pages: |
| 473 | for (i = 0; i < pinned_pages; i++) { |
| 474 | SetPageDirty(user_pages[i]); |
| 475 | page_cache_release(user_pages[i]); |
| 476 | } |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 477 | drm_free_large(user_pages); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 478 | |
| 479 | return ret; |
| 480 | } |
| 481 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 482 | /** |
| 483 | * Reads data from the object referenced by handle. |
| 484 | * |
| 485 | * On error, the contents of *data are undefined. |
| 486 | */ |
| 487 | int |
| 488 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 489 | struct drm_file *file_priv) |
| 490 | { |
| 491 | struct drm_i915_gem_pread *args = data; |
| 492 | struct drm_gem_object *obj; |
| 493 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 494 | int ret; |
| 495 | |
| 496 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 497 | if (obj == NULL) |
| 498 | return -EBADF; |
| 499 | obj_priv = obj->driver_private; |
| 500 | |
| 501 | /* Bounds check source. |
| 502 | * |
| 503 | * XXX: This could use review for overflow issues... |
| 504 | */ |
| 505 | if (args->offset > obj->size || args->size > obj->size || |
| 506 | args->offset + args->size > obj->size) { |
| 507 | drm_gem_object_unreference(obj); |
| 508 | return -EINVAL; |
| 509 | } |
| 510 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 511 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 512 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 513 | } else { |
| 514 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
| 515 | if (ret != 0) |
| 516 | ret = i915_gem_shmem_pread_slow(dev, obj, args, |
| 517 | file_priv); |
| 518 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 519 | |
| 520 | drm_gem_object_unreference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 521 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 522 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 523 | } |
| 524 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 525 | /* This is the fast write path which cannot handle |
| 526 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 527 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 528 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 529 | static inline int |
| 530 | fast_user_write(struct io_mapping *mapping, |
| 531 | loff_t page_base, int page_offset, |
| 532 | char __user *user_data, |
| 533 | int length) |
| 534 | { |
| 535 | char *vaddr_atomic; |
| 536 | unsigned long unwritten; |
| 537 | |
| 538 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
| 539 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 540 | user_data, length); |
| 541 | io_mapping_unmap_atomic(vaddr_atomic); |
| 542 | if (unwritten) |
| 543 | return -EFAULT; |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 544 | return 0; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 545 | } |
| 546 | |
| 547 | /* Here's the write path which can sleep for |
| 548 | * page faults |
| 549 | */ |
| 550 | |
| 551 | static inline int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 552 | slow_kernel_write(struct io_mapping *mapping, |
| 553 | loff_t gtt_base, int gtt_offset, |
| 554 | struct page *user_page, int user_offset, |
| 555 | int length) |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 556 | { |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 557 | char *src_vaddr, *dst_vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 558 | unsigned long unwritten; |
| 559 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 560 | dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base); |
| 561 | src_vaddr = kmap_atomic(user_page, KM_USER1); |
| 562 | unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset, |
| 563 | src_vaddr + user_offset, |
| 564 | length); |
| 565 | kunmap_atomic(src_vaddr, KM_USER1); |
| 566 | io_mapping_unmap_atomic(dst_vaddr); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 567 | if (unwritten) |
| 568 | return -EFAULT; |
| 569 | return 0; |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 570 | } |
| 571 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 572 | static inline int |
| 573 | fast_shmem_write(struct page **pages, |
| 574 | loff_t page_base, int page_offset, |
| 575 | char __user *data, |
| 576 | int length) |
| 577 | { |
| 578 | char __iomem *vaddr; |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 579 | unsigned long unwritten; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 580 | |
| 581 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); |
| 582 | if (vaddr == NULL) |
| 583 | return -ENOMEM; |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 584 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 585 | kunmap_atomic(vaddr, KM_USER0); |
| 586 | |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 587 | if (unwritten) |
| 588 | return -EFAULT; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 589 | return 0; |
| 590 | } |
| 591 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 592 | /** |
| 593 | * This is the fast pwrite path, where we copy the data directly from the |
| 594 | * user into the GTT, uncached. |
| 595 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 596 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 597 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 598 | struct drm_i915_gem_pwrite *args, |
| 599 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 600 | { |
| 601 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 602 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 603 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 604 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 605 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 606 | int page_offset, page_length; |
| 607 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 608 | |
| 609 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 610 | remain = args->size; |
| 611 | if (!access_ok(VERIFY_READ, user_data, remain)) |
| 612 | return -EFAULT; |
| 613 | |
| 614 | |
| 615 | mutex_lock(&dev->struct_mutex); |
| 616 | ret = i915_gem_object_pin(obj, 0); |
| 617 | if (ret) { |
| 618 | mutex_unlock(&dev->struct_mutex); |
| 619 | return ret; |
| 620 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 621 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 622 | if (ret) |
| 623 | goto fail; |
| 624 | |
| 625 | obj_priv = obj->driver_private; |
| 626 | offset = obj_priv->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 627 | |
| 628 | while (remain > 0) { |
| 629 | /* Operation in this page |
| 630 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 631 | * page_base = page offset within aperture |
| 632 | * page_offset = offset within page |
| 633 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 634 | */ |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 635 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 636 | page_offset = offset & (PAGE_SIZE-1); |
| 637 | page_length = remain; |
| 638 | if ((page_offset + remain) > PAGE_SIZE) |
| 639 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 640 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 641 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, |
| 642 | page_offset, user_data, page_length); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 643 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 644 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 645 | * source page isn't available. Return the error and we'll |
| 646 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 647 | */ |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 648 | if (ret) |
| 649 | goto fail; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 650 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 651 | remain -= page_length; |
| 652 | user_data += page_length; |
| 653 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 654 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 655 | |
| 656 | fail: |
| 657 | i915_gem_object_unpin(obj); |
| 658 | mutex_unlock(&dev->struct_mutex); |
| 659 | |
| 660 | return ret; |
| 661 | } |
| 662 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 663 | /** |
| 664 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin |
| 665 | * the memory and maps it using kmap_atomic for copying. |
| 666 | * |
| 667 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU |
| 668 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). |
| 669 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 670 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 671 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 672 | struct drm_i915_gem_pwrite *args, |
| 673 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 674 | { |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 675 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 676 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 677 | ssize_t remain; |
| 678 | loff_t gtt_page_base, offset; |
| 679 | loff_t first_data_page, last_data_page, num_pages; |
| 680 | loff_t pinned_pages, i; |
| 681 | struct page **user_pages; |
| 682 | struct mm_struct *mm = current->mm; |
| 683 | int gtt_page_offset, data_page_offset, data_page_index, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 684 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 685 | uint64_t data_ptr = args->data_ptr; |
| 686 | |
| 687 | remain = args->size; |
| 688 | |
| 689 | /* Pin the user pages containing the data. We can't fault while |
| 690 | * holding the struct mutex, and all of the pwrite implementations |
| 691 | * want to hold it while dereferencing the user data. |
| 692 | */ |
| 693 | first_data_page = data_ptr / PAGE_SIZE; |
| 694 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 695 | num_pages = last_data_page - first_data_page + 1; |
| 696 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 697 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 698 | if (user_pages == NULL) |
| 699 | return -ENOMEM; |
| 700 | |
| 701 | down_read(&mm->mmap_sem); |
| 702 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 703 | num_pages, 0, 0, user_pages, NULL); |
| 704 | up_read(&mm->mmap_sem); |
| 705 | if (pinned_pages < num_pages) { |
| 706 | ret = -EFAULT; |
| 707 | goto out_unpin_pages; |
| 708 | } |
| 709 | |
| 710 | mutex_lock(&dev->struct_mutex); |
| 711 | ret = i915_gem_object_pin(obj, 0); |
| 712 | if (ret) |
| 713 | goto out_unlock; |
| 714 | |
| 715 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 716 | if (ret) |
| 717 | goto out_unpin_object; |
| 718 | |
| 719 | obj_priv = obj->driver_private; |
| 720 | offset = obj_priv->gtt_offset + args->offset; |
| 721 | |
| 722 | while (remain > 0) { |
| 723 | /* Operation in this page |
| 724 | * |
| 725 | * gtt_page_base = page offset within aperture |
| 726 | * gtt_page_offset = offset within page in aperture |
| 727 | * data_page_index = page number in get_user_pages return |
| 728 | * data_page_offset = offset with data_page_index page. |
| 729 | * page_length = bytes to copy for this page |
| 730 | */ |
| 731 | gtt_page_base = offset & PAGE_MASK; |
| 732 | gtt_page_offset = offset & ~PAGE_MASK; |
| 733 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 734 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 735 | |
| 736 | page_length = remain; |
| 737 | if ((gtt_page_offset + page_length) > PAGE_SIZE) |
| 738 | page_length = PAGE_SIZE - gtt_page_offset; |
| 739 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 740 | page_length = PAGE_SIZE - data_page_offset; |
| 741 | |
| 742 | ret = slow_kernel_write(dev_priv->mm.gtt_mapping, |
| 743 | gtt_page_base, gtt_page_offset, |
| 744 | user_pages[data_page_index], |
| 745 | data_page_offset, |
| 746 | page_length); |
| 747 | |
| 748 | /* If we get a fault while copying data, then (presumably) our |
| 749 | * source page isn't available. Return the error and we'll |
| 750 | * retry in the slow path. |
| 751 | */ |
| 752 | if (ret) |
| 753 | goto out_unpin_object; |
| 754 | |
| 755 | remain -= page_length; |
| 756 | offset += page_length; |
| 757 | data_ptr += page_length; |
| 758 | } |
| 759 | |
| 760 | out_unpin_object: |
| 761 | i915_gem_object_unpin(obj); |
| 762 | out_unlock: |
| 763 | mutex_unlock(&dev->struct_mutex); |
| 764 | out_unpin_pages: |
| 765 | for (i = 0; i < pinned_pages; i++) |
| 766 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 767 | drm_free_large(user_pages); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 768 | |
| 769 | return ret; |
| 770 | } |
| 771 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 772 | /** |
| 773 | * This is the fast shmem pwrite path, which attempts to directly |
| 774 | * copy_from_user into the kmapped pages backing the object. |
| 775 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 776 | static int |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 777 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 778 | struct drm_i915_gem_pwrite *args, |
| 779 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 780 | { |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 781 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 782 | ssize_t remain; |
| 783 | loff_t offset, page_base; |
| 784 | char __user *user_data; |
| 785 | int page_offset, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 786 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 787 | |
| 788 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 789 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 790 | |
| 791 | mutex_lock(&dev->struct_mutex); |
| 792 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 793 | ret = i915_gem_object_get_pages(obj); |
| 794 | if (ret != 0) |
| 795 | goto fail_unlock; |
| 796 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 797 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 798 | if (ret != 0) |
| 799 | goto fail_put_pages; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 800 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 801 | obj_priv = obj->driver_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 802 | offset = args->offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 803 | obj_priv->dirty = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 804 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 805 | while (remain > 0) { |
| 806 | /* Operation in this page |
| 807 | * |
| 808 | * page_base = page offset within aperture |
| 809 | * page_offset = offset within page |
| 810 | * page_length = bytes to copy for this page |
| 811 | */ |
| 812 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 813 | page_offset = offset & (PAGE_SIZE-1); |
| 814 | page_length = remain; |
| 815 | if ((page_offset + remain) > PAGE_SIZE) |
| 816 | page_length = PAGE_SIZE - page_offset; |
| 817 | |
| 818 | ret = fast_shmem_write(obj_priv->pages, |
| 819 | page_base, page_offset, |
| 820 | user_data, page_length); |
| 821 | if (ret) |
| 822 | goto fail_put_pages; |
| 823 | |
| 824 | remain -= page_length; |
| 825 | user_data += page_length; |
| 826 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 827 | } |
| 828 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 829 | fail_put_pages: |
| 830 | i915_gem_object_put_pages(obj); |
| 831 | fail_unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 832 | mutex_unlock(&dev->struct_mutex); |
| 833 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 834 | return ret; |
| 835 | } |
| 836 | |
| 837 | /** |
| 838 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin |
| 839 | * the memory and maps it using kmap_atomic for copying. |
| 840 | * |
| 841 | * This avoids taking mmap_sem for faulting on the user's address while the |
| 842 | * struct_mutex is held. |
| 843 | */ |
| 844 | static int |
| 845 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 846 | struct drm_i915_gem_pwrite *args, |
| 847 | struct drm_file *file_priv) |
| 848 | { |
| 849 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 850 | struct mm_struct *mm = current->mm; |
| 851 | struct page **user_pages; |
| 852 | ssize_t remain; |
| 853 | loff_t offset, pinned_pages, i; |
| 854 | loff_t first_data_page, last_data_page, num_pages; |
| 855 | int shmem_page_index, shmem_page_offset; |
| 856 | int data_page_index, data_page_offset; |
| 857 | int page_length; |
| 858 | int ret; |
| 859 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 860 | int do_bit17_swizzling; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 861 | |
| 862 | remain = args->size; |
| 863 | |
| 864 | /* Pin the user pages containing the data. We can't fault while |
| 865 | * holding the struct mutex, and all of the pwrite implementations |
| 866 | * want to hold it while dereferencing the user data. |
| 867 | */ |
| 868 | first_data_page = data_ptr / PAGE_SIZE; |
| 869 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 870 | num_pages = last_data_page - first_data_page + 1; |
| 871 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 872 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 873 | if (user_pages == NULL) |
| 874 | return -ENOMEM; |
| 875 | |
| 876 | down_read(&mm->mmap_sem); |
| 877 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 878 | num_pages, 0, 0, user_pages, NULL); |
| 879 | up_read(&mm->mmap_sem); |
| 880 | if (pinned_pages < num_pages) { |
| 881 | ret = -EFAULT; |
| 882 | goto fail_put_user_pages; |
| 883 | } |
| 884 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 885 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 886 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 887 | mutex_lock(&dev->struct_mutex); |
| 888 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 889 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 890 | if (ret) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 891 | goto fail_unlock; |
| 892 | |
| 893 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 894 | if (ret != 0) |
| 895 | goto fail_put_pages; |
| 896 | |
| 897 | obj_priv = obj->driver_private; |
| 898 | offset = args->offset; |
| 899 | obj_priv->dirty = 1; |
| 900 | |
| 901 | while (remain > 0) { |
| 902 | /* Operation in this page |
| 903 | * |
| 904 | * shmem_page_index = page number within shmem file |
| 905 | * shmem_page_offset = offset within page in shmem file |
| 906 | * data_page_index = page number in get_user_pages return |
| 907 | * data_page_offset = offset with data_page_index page. |
| 908 | * page_length = bytes to copy for this page |
| 909 | */ |
| 910 | shmem_page_index = offset / PAGE_SIZE; |
| 911 | shmem_page_offset = offset & ~PAGE_MASK; |
| 912 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 913 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 914 | |
| 915 | page_length = remain; |
| 916 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 917 | page_length = PAGE_SIZE - shmem_page_offset; |
| 918 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 919 | page_length = PAGE_SIZE - data_page_offset; |
| 920 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 921 | if (do_bit17_swizzling) { |
| 922 | ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
| 923 | shmem_page_offset, |
| 924 | user_pages[data_page_index], |
| 925 | data_page_offset, |
| 926 | page_length, |
| 927 | 0); |
| 928 | } else { |
| 929 | ret = slow_shmem_copy(obj_priv->pages[shmem_page_index], |
| 930 | shmem_page_offset, |
| 931 | user_pages[data_page_index], |
| 932 | data_page_offset, |
| 933 | page_length); |
| 934 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 935 | if (ret) |
| 936 | goto fail_put_pages; |
| 937 | |
| 938 | remain -= page_length; |
| 939 | data_ptr += page_length; |
| 940 | offset += page_length; |
| 941 | } |
| 942 | |
| 943 | fail_put_pages: |
| 944 | i915_gem_object_put_pages(obj); |
| 945 | fail_unlock: |
| 946 | mutex_unlock(&dev->struct_mutex); |
| 947 | fail_put_user_pages: |
| 948 | for (i = 0; i < pinned_pages; i++) |
| 949 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 950 | drm_free_large(user_pages); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 951 | |
| 952 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 953 | } |
| 954 | |
| 955 | /** |
| 956 | * Writes data to the object referenced by handle. |
| 957 | * |
| 958 | * On error, the contents of the buffer that were to be modified are undefined. |
| 959 | */ |
| 960 | int |
| 961 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 962 | struct drm_file *file_priv) |
| 963 | { |
| 964 | struct drm_i915_gem_pwrite *args = data; |
| 965 | struct drm_gem_object *obj; |
| 966 | struct drm_i915_gem_object *obj_priv; |
| 967 | int ret = 0; |
| 968 | |
| 969 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 970 | if (obj == NULL) |
| 971 | return -EBADF; |
| 972 | obj_priv = obj->driver_private; |
| 973 | |
| 974 | /* Bounds check destination. |
| 975 | * |
| 976 | * XXX: This could use review for overflow issues... |
| 977 | */ |
| 978 | if (args->offset > obj->size || args->size > obj->size || |
| 979 | args->offset + args->size > obj->size) { |
| 980 | drm_gem_object_unreference(obj); |
| 981 | return -EINVAL; |
| 982 | } |
| 983 | |
| 984 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 985 | * it would end up going through the fenced access, and we'll get |
| 986 | * different detiling behavior between reading and writing. |
| 987 | * pread/pwrite currently are reading and writing from the CPU |
| 988 | * perspective, requiring manual detiling by the client. |
| 989 | */ |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 990 | if (obj_priv->phys_obj) |
| 991 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); |
| 992 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 993 | dev->gtt_total != 0) { |
| 994 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); |
| 995 | if (ret == -EFAULT) { |
| 996 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, |
| 997 | file_priv); |
| 998 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 999 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
| 1000 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1001 | } else { |
| 1002 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); |
| 1003 | if (ret == -EFAULT) { |
| 1004 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, |
| 1005 | file_priv); |
| 1006 | } |
| 1007 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1008 | |
| 1009 | #if WATCH_PWRITE |
| 1010 | if (ret) |
| 1011 | DRM_INFO("pwrite failed %d\n", ret); |
| 1012 | #endif |
| 1013 | |
| 1014 | drm_gem_object_unreference(obj); |
| 1015 | |
| 1016 | return ret; |
| 1017 | } |
| 1018 | |
| 1019 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1020 | * Called when user space prepares to use an object with the CPU, either |
| 1021 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1022 | */ |
| 1023 | int |
| 1024 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1025 | struct drm_file *file_priv) |
| 1026 | { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1027 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1028 | struct drm_i915_gem_set_domain *args = data; |
| 1029 | struct drm_gem_object *obj; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1030 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1031 | uint32_t read_domains = args->read_domains; |
| 1032 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1033 | int ret; |
| 1034 | |
| 1035 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1036 | return -ENODEV; |
| 1037 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1038 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1039 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1040 | return -EINVAL; |
| 1041 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1042 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1043 | return -EINVAL; |
| 1044 | |
| 1045 | /* Having something in the write domain implies it's in the read |
| 1046 | * domain, and only that read domain. Enforce that in the request. |
| 1047 | */ |
| 1048 | if (write_domain != 0 && read_domains != write_domain) |
| 1049 | return -EINVAL; |
| 1050 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1051 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1052 | if (obj == NULL) |
| 1053 | return -EBADF; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1054 | obj_priv = obj->driver_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1055 | |
| 1056 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1057 | |
| 1058 | intel_mark_busy(dev, obj); |
| 1059 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1060 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 1061 | DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1062 | obj, obj->size, read_domains, write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1063 | #endif |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1064 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1065 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1066 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1067 | /* Update the LRU on the fence for the CPU access that's |
| 1068 | * about to occur. |
| 1069 | */ |
| 1070 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
| 1071 | list_move_tail(&obj_priv->fence_list, |
| 1072 | &dev_priv->mm.fence_list); |
| 1073 | } |
| 1074 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1075 | /* Silently promote "you're not bound, there was nothing to do" |
| 1076 | * to success, since the client was just asking us to |
| 1077 | * make sure everything was done. |
| 1078 | */ |
| 1079 | if (ret == -EINVAL) |
| 1080 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1081 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1082 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1083 | } |
| 1084 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1085 | drm_gem_object_unreference(obj); |
| 1086 | mutex_unlock(&dev->struct_mutex); |
| 1087 | return ret; |
| 1088 | } |
| 1089 | |
| 1090 | /** |
| 1091 | * Called when user space has done writes to this buffer |
| 1092 | */ |
| 1093 | int |
| 1094 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1095 | struct drm_file *file_priv) |
| 1096 | { |
| 1097 | struct drm_i915_gem_sw_finish *args = data; |
| 1098 | struct drm_gem_object *obj; |
| 1099 | struct drm_i915_gem_object *obj_priv; |
| 1100 | int ret = 0; |
| 1101 | |
| 1102 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1103 | return -ENODEV; |
| 1104 | |
| 1105 | mutex_lock(&dev->struct_mutex); |
| 1106 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1107 | if (obj == NULL) { |
| 1108 | mutex_unlock(&dev->struct_mutex); |
| 1109 | return -EBADF; |
| 1110 | } |
| 1111 | |
| 1112 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 1113 | DRM_INFO("%s: sw_finish %d (%p %zd)\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1114 | __func__, args->handle, obj, obj->size); |
| 1115 | #endif |
| 1116 | obj_priv = obj->driver_private; |
| 1117 | |
| 1118 | /* Pinned buffers may be scanout, so flush the cache */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1119 | if (obj_priv->pin_count) |
| 1120 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1121 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1122 | drm_gem_object_unreference(obj); |
| 1123 | mutex_unlock(&dev->struct_mutex); |
| 1124 | return ret; |
| 1125 | } |
| 1126 | |
| 1127 | /** |
| 1128 | * Maps the contents of an object, returning the address it is mapped |
| 1129 | * into. |
| 1130 | * |
| 1131 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1132 | * imply a ref on the object itself. |
| 1133 | */ |
| 1134 | int |
| 1135 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1136 | struct drm_file *file_priv) |
| 1137 | { |
| 1138 | struct drm_i915_gem_mmap *args = data; |
| 1139 | struct drm_gem_object *obj; |
| 1140 | loff_t offset; |
| 1141 | unsigned long addr; |
| 1142 | |
| 1143 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1144 | return -ENODEV; |
| 1145 | |
| 1146 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1147 | if (obj == NULL) |
| 1148 | return -EBADF; |
| 1149 | |
| 1150 | offset = args->offset; |
| 1151 | |
| 1152 | down_write(¤t->mm->mmap_sem); |
| 1153 | addr = do_mmap(obj->filp, 0, args->size, |
| 1154 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1155 | args->offset); |
| 1156 | up_write(¤t->mm->mmap_sem); |
| 1157 | mutex_lock(&dev->struct_mutex); |
| 1158 | drm_gem_object_unreference(obj); |
| 1159 | mutex_unlock(&dev->struct_mutex); |
| 1160 | if (IS_ERR((void *)addr)) |
| 1161 | return addr; |
| 1162 | |
| 1163 | args->addr_ptr = (uint64_t) addr; |
| 1164 | |
| 1165 | return 0; |
| 1166 | } |
| 1167 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1168 | /** |
| 1169 | * i915_gem_fault - fault a page into the GTT |
| 1170 | * vma: VMA in question |
| 1171 | * vmf: fault info |
| 1172 | * |
| 1173 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1174 | * from userspace. The fault handler takes care of binding the object to |
| 1175 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1176 | * only if needed based on whether the old reg is still valid or the object |
| 1177 | * is tiled) and inserting a new PTE into the faulting process. |
| 1178 | * |
| 1179 | * Note that the faulting process may involve evicting existing objects |
| 1180 | * from the GTT and/or fence registers to make room. So performance may |
| 1181 | * suffer if the GTT working set is large or there are few fence registers |
| 1182 | * left. |
| 1183 | */ |
| 1184 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1185 | { |
| 1186 | struct drm_gem_object *obj = vma->vm_private_data; |
| 1187 | struct drm_device *dev = obj->dev; |
| 1188 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1189 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1190 | pgoff_t page_offset; |
| 1191 | unsigned long pfn; |
| 1192 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1193 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1194 | |
| 1195 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1196 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1197 | PAGE_SHIFT; |
| 1198 | |
| 1199 | /* Now bind it into the GTT if needed */ |
| 1200 | mutex_lock(&dev->struct_mutex); |
| 1201 | if (!obj_priv->gtt_space) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1202 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1203 | if (ret) { |
| 1204 | mutex_unlock(&dev->struct_mutex); |
| 1205 | return VM_FAULT_SIGBUS; |
| 1206 | } |
Chris Wilson | 4960aac | 2009-09-14 16:50:25 +0100 | [diff] [blame] | 1207 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
Kristian Høgsberg | 07f4f3e | 2009-05-27 14:37:28 -0400 | [diff] [blame] | 1208 | |
| 1209 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1210 | if (ret) { |
| 1211 | mutex_unlock(&dev->struct_mutex); |
| 1212 | return VM_FAULT_SIGBUS; |
| 1213 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1214 | } |
| 1215 | |
| 1216 | /* Need a new fence register? */ |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1217 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 1218 | ret = i915_gem_object_get_fence_reg(obj); |
Chris Wilson | 7d8d58b | 2009-02-04 14:15:10 +0000 | [diff] [blame] | 1219 | if (ret) { |
| 1220 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1221 | return VM_FAULT_SIGBUS; |
Chris Wilson | 7d8d58b | 2009-02-04 14:15:10 +0000 | [diff] [blame] | 1222 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1223 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1224 | |
| 1225 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
| 1226 | page_offset; |
| 1227 | |
| 1228 | /* Finally, remap it using the new GTT offset */ |
| 1229 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
| 1230 | |
| 1231 | mutex_unlock(&dev->struct_mutex); |
| 1232 | |
| 1233 | switch (ret) { |
| 1234 | case -ENOMEM: |
| 1235 | case -EAGAIN: |
| 1236 | return VM_FAULT_OOM; |
| 1237 | case -EFAULT: |
Jesse Barnes | 959b887 | 2009-03-20 14:16:33 -0700 | [diff] [blame] | 1238 | case -EINVAL: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1239 | return VM_FAULT_SIGBUS; |
| 1240 | default: |
| 1241 | return VM_FAULT_NOPAGE; |
| 1242 | } |
| 1243 | } |
| 1244 | |
| 1245 | /** |
| 1246 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 1247 | * @obj: obj in question |
| 1248 | * |
| 1249 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 1250 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 1251 | * up the object based on the offset and sets up the various memory mapping |
| 1252 | * structures. |
| 1253 | * |
| 1254 | * This routine allocates and attaches a fake offset for @obj. |
| 1255 | */ |
| 1256 | static int |
| 1257 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) |
| 1258 | { |
| 1259 | struct drm_device *dev = obj->dev; |
| 1260 | struct drm_gem_mm *mm = dev->mm_private; |
| 1261 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1262 | struct drm_map_list *list; |
Benjamin Herrenschmidt | f77d390 | 2009-02-02 16:55:46 +1100 | [diff] [blame] | 1263 | struct drm_local_map *map; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1264 | int ret = 0; |
| 1265 | |
| 1266 | /* Set the object up for mmap'ing */ |
| 1267 | list = &obj->map_list; |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1268 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1269 | if (!list->map) |
| 1270 | return -ENOMEM; |
| 1271 | |
| 1272 | map = list->map; |
| 1273 | map->type = _DRM_GEM; |
| 1274 | map->size = obj->size; |
| 1275 | map->handle = obj; |
| 1276 | |
| 1277 | /* Get a DRM GEM mmap offset allocated... */ |
| 1278 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
| 1279 | obj->size / PAGE_SIZE, 0, 0); |
| 1280 | if (!list->file_offset_node) { |
| 1281 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); |
| 1282 | ret = -ENOMEM; |
| 1283 | goto out_free_list; |
| 1284 | } |
| 1285 | |
| 1286 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
| 1287 | obj->size / PAGE_SIZE, 0); |
| 1288 | if (!list->file_offset_node) { |
| 1289 | ret = -ENOMEM; |
| 1290 | goto out_free_list; |
| 1291 | } |
| 1292 | |
| 1293 | list->hash.key = list->file_offset_node->start; |
| 1294 | if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) { |
| 1295 | DRM_ERROR("failed to add to map hash\n"); |
| 1296 | goto out_free_mm; |
| 1297 | } |
| 1298 | |
| 1299 | /* By now we should be all set, any drm_mmap request on the offset |
| 1300 | * below will get to our mmap & fault handler */ |
| 1301 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; |
| 1302 | |
| 1303 | return 0; |
| 1304 | |
| 1305 | out_free_mm: |
| 1306 | drm_mm_put_block(list->file_offset_node); |
| 1307 | out_free_list: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1308 | kfree(list->map); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1309 | |
| 1310 | return ret; |
| 1311 | } |
| 1312 | |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1313 | /** |
| 1314 | * i915_gem_release_mmap - remove physical page mappings |
| 1315 | * @obj: obj in question |
| 1316 | * |
| 1317 | * Preserve the reservation of the mmaping with the DRM core code, but |
| 1318 | * relinquish ownership of the pages back to the system. |
| 1319 | * |
| 1320 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1321 | * object through the GTT and then lose the fence register due to |
| 1322 | * resource pressure. Similarly if the object has been moved out of the |
| 1323 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1324 | * mapping will then trigger a page fault on the next user access, allowing |
| 1325 | * fixup by i915_gem_fault(). |
| 1326 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1327 | void |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1328 | i915_gem_release_mmap(struct drm_gem_object *obj) |
| 1329 | { |
| 1330 | struct drm_device *dev = obj->dev; |
| 1331 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1332 | |
| 1333 | if (dev->dev_mapping) |
| 1334 | unmap_mapping_range(dev->dev_mapping, |
| 1335 | obj_priv->mmap_offset, obj->size, 1); |
| 1336 | } |
| 1337 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1338 | static void |
| 1339 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) |
| 1340 | { |
| 1341 | struct drm_device *dev = obj->dev; |
| 1342 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1343 | struct drm_gem_mm *mm = dev->mm_private; |
| 1344 | struct drm_map_list *list; |
| 1345 | |
| 1346 | list = &obj->map_list; |
| 1347 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
| 1348 | |
| 1349 | if (list->file_offset_node) { |
| 1350 | drm_mm_put_block(list->file_offset_node); |
| 1351 | list->file_offset_node = NULL; |
| 1352 | } |
| 1353 | |
| 1354 | if (list->map) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1355 | kfree(list->map); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1356 | list->map = NULL; |
| 1357 | } |
| 1358 | |
| 1359 | obj_priv->mmap_offset = 0; |
| 1360 | } |
| 1361 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1362 | /** |
| 1363 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1364 | * @obj: object to check |
| 1365 | * |
| 1366 | * Return the required GTT alignment for an object, taking into account |
| 1367 | * potential fence register mapping if needed. |
| 1368 | */ |
| 1369 | static uint32_t |
| 1370 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) |
| 1371 | { |
| 1372 | struct drm_device *dev = obj->dev; |
| 1373 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1374 | int start, i; |
| 1375 | |
| 1376 | /* |
| 1377 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1378 | * if a fence register is needed for the object. |
| 1379 | */ |
| 1380 | if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE) |
| 1381 | return 4096; |
| 1382 | |
| 1383 | /* |
| 1384 | * Previous chips need to be aligned to the size of the smallest |
| 1385 | * fence register that can contain the object. |
| 1386 | */ |
| 1387 | if (IS_I9XX(dev)) |
| 1388 | start = 1024*1024; |
| 1389 | else |
| 1390 | start = 512*1024; |
| 1391 | |
| 1392 | for (i = start; i < obj->size; i <<= 1) |
| 1393 | ; |
| 1394 | |
| 1395 | return i; |
| 1396 | } |
| 1397 | |
| 1398 | /** |
| 1399 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1400 | * @dev: DRM device |
| 1401 | * @data: GTT mapping ioctl data |
| 1402 | * @file_priv: GEM object info |
| 1403 | * |
| 1404 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1405 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1406 | * up so we can get faults in the handler above. |
| 1407 | * |
| 1408 | * The fault handler will take care of binding the object into the GTT |
| 1409 | * (since it may have been evicted to make room for something), allocating |
| 1410 | * a fence register, and mapping the appropriate aperture address into |
| 1411 | * userspace. |
| 1412 | */ |
| 1413 | int |
| 1414 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1415 | struct drm_file *file_priv) |
| 1416 | { |
| 1417 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1418 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1419 | struct drm_gem_object *obj; |
| 1420 | struct drm_i915_gem_object *obj_priv; |
| 1421 | int ret; |
| 1422 | |
| 1423 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1424 | return -ENODEV; |
| 1425 | |
| 1426 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1427 | if (obj == NULL) |
| 1428 | return -EBADF; |
| 1429 | |
| 1430 | mutex_lock(&dev->struct_mutex); |
| 1431 | |
| 1432 | obj_priv = obj->driver_private; |
| 1433 | |
| 1434 | if (!obj_priv->mmap_offset) { |
| 1435 | ret = i915_gem_create_mmap_offset(obj); |
Chris Wilson | 13af106 | 2009-02-11 14:26:31 +0000 | [diff] [blame] | 1436 | if (ret) { |
| 1437 | drm_gem_object_unreference(obj); |
| 1438 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1439 | return ret; |
Chris Wilson | 13af106 | 2009-02-11 14:26:31 +0000 | [diff] [blame] | 1440 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1441 | } |
| 1442 | |
| 1443 | args->offset = obj_priv->mmap_offset; |
| 1444 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1445 | /* |
| 1446 | * Pull it into the GTT so that we have a page list (makes the |
| 1447 | * initial fault faster and any subsequent flushing possible). |
| 1448 | */ |
| 1449 | if (!obj_priv->agp_mem) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1450 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1451 | if (ret) { |
| 1452 | drm_gem_object_unreference(obj); |
| 1453 | mutex_unlock(&dev->struct_mutex); |
| 1454 | return ret; |
| 1455 | } |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 1456 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1457 | } |
| 1458 | |
| 1459 | drm_gem_object_unreference(obj); |
| 1460 | mutex_unlock(&dev->struct_mutex); |
| 1461 | |
| 1462 | return 0; |
| 1463 | } |
| 1464 | |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 1465 | void |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1466 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1467 | { |
| 1468 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1469 | int page_count = obj->size / PAGE_SIZE; |
| 1470 | int i; |
| 1471 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1472 | BUG_ON(obj_priv->pages_refcount == 0); |
| 1473 | |
| 1474 | if (--obj_priv->pages_refcount != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1475 | return; |
| 1476 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1477 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1478 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1479 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1480 | if (obj_priv->madv == I915_MADV_DONTNEED) |
Chris Wilson | 13a05fd | 2009-09-20 23:03:19 +0100 | [diff] [blame] | 1481 | obj_priv->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1482 | |
| 1483 | for (i = 0; i < page_count; i++) { |
| 1484 | if (obj_priv->pages[i] == NULL) |
| 1485 | break; |
| 1486 | |
| 1487 | if (obj_priv->dirty) |
| 1488 | set_page_dirty(obj_priv->pages[i]); |
| 1489 | |
| 1490 | if (obj_priv->madv == I915_MADV_WILLNEED) |
Chris Wilson | 13a05fd | 2009-09-20 23:03:19 +0100 | [diff] [blame] | 1491 | mark_page_accessed(obj_priv->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1492 | |
| 1493 | page_cache_release(obj_priv->pages[i]); |
| 1494 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1495 | obj_priv->dirty = 0; |
| 1496 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 1497 | drm_free_large(obj_priv->pages); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1498 | obj_priv->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1499 | } |
| 1500 | |
| 1501 | static void |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1502 | i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1503 | { |
| 1504 | struct drm_device *dev = obj->dev; |
| 1505 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1506 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1507 | |
| 1508 | /* Add a reference if we're newly entering the active list. */ |
| 1509 | if (!obj_priv->active) { |
| 1510 | drm_gem_object_reference(obj); |
| 1511 | obj_priv->active = 1; |
| 1512 | } |
| 1513 | /* Move from whatever list we were on to the tail of execution. */ |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1514 | spin_lock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1515 | list_move_tail(&obj_priv->list, |
| 1516 | &dev_priv->mm.active_list); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1517 | spin_unlock(&dev_priv->mm.active_list_lock); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1518 | obj_priv->last_rendering_seqno = seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1519 | } |
| 1520 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1521 | static void |
| 1522 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) |
| 1523 | { |
| 1524 | struct drm_device *dev = obj->dev; |
| 1525 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1526 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1527 | |
| 1528 | BUG_ON(!obj_priv->active); |
| 1529 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); |
| 1530 | obj_priv->last_rendering_seqno = 0; |
| 1531 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1532 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1533 | /* Immediately discard the backing storage */ |
| 1534 | static void |
| 1535 | i915_gem_object_truncate(struct drm_gem_object *obj) |
| 1536 | { |
| 1537 | struct inode *inode; |
| 1538 | |
| 1539 | inode = obj->filp->f_path.dentry->d_inode; |
| 1540 | if (inode->i_op->truncate) |
| 1541 | inode->i_op->truncate (inode); |
| 1542 | } |
| 1543 | |
| 1544 | static inline int |
| 1545 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) |
| 1546 | { |
| 1547 | return obj_priv->madv == I915_MADV_DONTNEED; |
| 1548 | } |
| 1549 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1550 | static void |
| 1551 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) |
| 1552 | { |
| 1553 | struct drm_device *dev = obj->dev; |
| 1554 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1555 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1556 | |
| 1557 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 1558 | if (obj_priv->pin_count != 0) |
| 1559 | list_del_init(&obj_priv->list); |
| 1560 | else |
| 1561 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
| 1562 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1563 | obj_priv->last_rendering_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1564 | if (obj_priv->active) { |
| 1565 | obj_priv->active = 0; |
| 1566 | drm_gem_object_unreference(obj); |
| 1567 | } |
| 1568 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 1569 | } |
| 1570 | |
| 1571 | /** |
| 1572 | * Creates a new sequence number, emitting a write of it to the status page |
| 1573 | * plus an interrupt, which will trigger i915_user_interrupt_handler. |
| 1574 | * |
| 1575 | * Must be called with struct_lock held. |
| 1576 | * |
| 1577 | * Returned sequence numbers are nonzero on success. |
| 1578 | */ |
| 1579 | static uint32_t |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1580 | i915_add_request(struct drm_device *dev, struct drm_file *file_priv, |
| 1581 | uint32_t flush_domains) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1582 | { |
| 1583 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1584 | struct drm_i915_file_private *i915_file_priv = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1585 | struct drm_i915_gem_request *request; |
| 1586 | uint32_t seqno; |
| 1587 | int was_empty; |
| 1588 | RING_LOCALS; |
| 1589 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1590 | if (file_priv != NULL) |
| 1591 | i915_file_priv = file_priv->driver_priv; |
| 1592 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1593 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1594 | if (request == NULL) |
| 1595 | return 0; |
| 1596 | |
| 1597 | /* Grab the seqno we're going to make this request be, and bump the |
| 1598 | * next (skipping 0 so it can be the reserved no-seqno value). |
| 1599 | */ |
| 1600 | seqno = dev_priv->mm.next_gem_seqno; |
| 1601 | dev_priv->mm.next_gem_seqno++; |
| 1602 | if (dev_priv->mm.next_gem_seqno == 0) |
| 1603 | dev_priv->mm.next_gem_seqno++; |
| 1604 | |
| 1605 | BEGIN_LP_RING(4); |
| 1606 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 1607 | OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 1608 | OUT_RING(seqno); |
| 1609 | |
| 1610 | OUT_RING(MI_USER_INTERRUPT); |
| 1611 | ADVANCE_LP_RING(); |
| 1612 | |
| 1613 | DRM_DEBUG("%d\n", seqno); |
| 1614 | |
| 1615 | request->seqno = seqno; |
| 1616 | request->emitted_jiffies = jiffies; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1617 | was_empty = list_empty(&dev_priv->mm.request_list); |
| 1618 | list_add_tail(&request->list, &dev_priv->mm.request_list); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1619 | if (i915_file_priv) { |
| 1620 | list_add_tail(&request->client_list, |
| 1621 | &i915_file_priv->mm.request_list); |
| 1622 | } else { |
| 1623 | INIT_LIST_HEAD(&request->client_list); |
| 1624 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1625 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1626 | /* Associate any objects on the flushing list matching the write |
| 1627 | * domain we're flushing with our flush. |
| 1628 | */ |
| 1629 | if (flush_domains != 0) { |
| 1630 | struct drm_i915_gem_object *obj_priv, *next; |
| 1631 | |
| 1632 | list_for_each_entry_safe(obj_priv, next, |
| 1633 | &dev_priv->mm.flushing_list, list) { |
| 1634 | struct drm_gem_object *obj = obj_priv->obj; |
| 1635 | |
| 1636 | if ((obj->write_domain & flush_domains) == |
| 1637 | obj->write_domain) { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1638 | uint32_t old_write_domain = obj->write_domain; |
| 1639 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1640 | obj->write_domain = 0; |
| 1641 | i915_gem_object_move_to_active(obj, seqno); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1642 | |
| 1643 | trace_i915_gem_object_change_domain(obj, |
| 1644 | obj->read_domains, |
| 1645 | old_write_domain); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1646 | } |
| 1647 | } |
| 1648 | |
| 1649 | } |
| 1650 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1651 | if (!dev_priv->mm.suspended) { |
| 1652 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); |
| 1653 | if (was_empty) |
| 1654 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1655 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1656 | return seqno; |
| 1657 | } |
| 1658 | |
| 1659 | /** |
| 1660 | * Command execution barrier |
| 1661 | * |
| 1662 | * Ensures that all commands in the ring are finished |
| 1663 | * before signalling the CPU |
| 1664 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 1665 | static uint32_t |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1666 | i915_retire_commands(struct drm_device *dev) |
| 1667 | { |
| 1668 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1669 | uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
| 1670 | uint32_t flush_domains = 0; |
| 1671 | RING_LOCALS; |
| 1672 | |
| 1673 | /* The sampler always gets flushed on i965 (sigh) */ |
| 1674 | if (IS_I965G(dev)) |
| 1675 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
| 1676 | BEGIN_LP_RING(2); |
| 1677 | OUT_RING(cmd); |
| 1678 | OUT_RING(0); /* noop */ |
| 1679 | ADVANCE_LP_RING(); |
| 1680 | return flush_domains; |
| 1681 | } |
| 1682 | |
| 1683 | /** |
| 1684 | * Moves buffers associated only with the given active seqno from the active |
| 1685 | * to inactive list, potentially freeing them. |
| 1686 | */ |
| 1687 | static void |
| 1688 | i915_gem_retire_request(struct drm_device *dev, |
| 1689 | struct drm_i915_gem_request *request) |
| 1690 | { |
| 1691 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1692 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1693 | trace_i915_gem_request_retire(dev, request->seqno); |
| 1694 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1695 | /* Move any buffers on the active list that are no longer referenced |
| 1696 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1697 | */ |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1698 | spin_lock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1699 | while (!list_empty(&dev_priv->mm.active_list)) { |
| 1700 | struct drm_gem_object *obj; |
| 1701 | struct drm_i915_gem_object *obj_priv; |
| 1702 | |
| 1703 | obj_priv = list_first_entry(&dev_priv->mm.active_list, |
| 1704 | struct drm_i915_gem_object, |
| 1705 | list); |
| 1706 | obj = obj_priv->obj; |
| 1707 | |
| 1708 | /* If the seqno being retired doesn't match the oldest in the |
| 1709 | * list, then the oldest in the list must still be newer than |
| 1710 | * this seqno. |
| 1711 | */ |
| 1712 | if (obj_priv->last_rendering_seqno != request->seqno) |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1713 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1714 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1715 | #if WATCH_LRU |
| 1716 | DRM_INFO("%s: retire %d moves to inactive list %p\n", |
| 1717 | __func__, request->seqno, obj); |
| 1718 | #endif |
| 1719 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1720 | if (obj->write_domain != 0) |
| 1721 | i915_gem_object_move_to_flushing(obj); |
Shaohua Li | 68c8434 | 2009-04-08 10:58:23 +0800 | [diff] [blame] | 1722 | else { |
| 1723 | /* Take a reference on the object so it won't be |
| 1724 | * freed while the spinlock is held. The list |
| 1725 | * protection for this spinlock is safe when breaking |
| 1726 | * the lock like this since the next thing we do |
| 1727 | * is just get the head of the list again. |
| 1728 | */ |
| 1729 | drm_gem_object_reference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1730 | i915_gem_object_move_to_inactive(obj); |
Shaohua Li | 68c8434 | 2009-04-08 10:58:23 +0800 | [diff] [blame] | 1731 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 1732 | drm_gem_object_unreference(obj); |
| 1733 | spin_lock(&dev_priv->mm.active_list_lock); |
| 1734 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1735 | } |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1736 | out: |
| 1737 | spin_unlock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1738 | } |
| 1739 | |
| 1740 | /** |
| 1741 | * Returns true if seq1 is later than seq2. |
| 1742 | */ |
Ben Gamari | 22be172 | 2009-09-14 17:48:43 -0400 | [diff] [blame] | 1743 | bool |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1744 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
| 1745 | { |
| 1746 | return (int32_t)(seq1 - seq2) >= 0; |
| 1747 | } |
| 1748 | |
| 1749 | uint32_t |
| 1750 | i915_get_gem_seqno(struct drm_device *dev) |
| 1751 | { |
| 1752 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1753 | |
| 1754 | return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX); |
| 1755 | } |
| 1756 | |
| 1757 | /** |
| 1758 | * This function clears the request list as sequence numbers are passed. |
| 1759 | */ |
| 1760 | void |
| 1761 | i915_gem_retire_requests(struct drm_device *dev) |
| 1762 | { |
| 1763 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1764 | uint32_t seqno; |
| 1765 | |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1766 | if (!dev_priv->hw_status_page) |
| 1767 | return; |
| 1768 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1769 | seqno = i915_get_gem_seqno(dev); |
| 1770 | |
| 1771 | while (!list_empty(&dev_priv->mm.request_list)) { |
| 1772 | struct drm_i915_gem_request *request; |
| 1773 | uint32_t retiring_seqno; |
| 1774 | |
| 1775 | request = list_first_entry(&dev_priv->mm.request_list, |
| 1776 | struct drm_i915_gem_request, |
| 1777 | list); |
| 1778 | retiring_seqno = request->seqno; |
| 1779 | |
| 1780 | if (i915_seqno_passed(seqno, retiring_seqno) || |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1781 | atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1782 | i915_gem_retire_request(dev, request); |
| 1783 | |
| 1784 | list_del(&request->list); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1785 | list_del(&request->client_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1786 | kfree(request); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1787 | } else |
| 1788 | break; |
| 1789 | } |
| 1790 | } |
| 1791 | |
| 1792 | void |
| 1793 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1794 | { |
| 1795 | drm_i915_private_t *dev_priv; |
| 1796 | struct drm_device *dev; |
| 1797 | |
| 1798 | dev_priv = container_of(work, drm_i915_private_t, |
| 1799 | mm.retire_work.work); |
| 1800 | dev = dev_priv->dev; |
| 1801 | |
| 1802 | mutex_lock(&dev->struct_mutex); |
| 1803 | i915_gem_retire_requests(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 1804 | if (!dev_priv->mm.suspended && |
| 1805 | !list_empty(&dev_priv->mm.request_list)) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1806 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1807 | mutex_unlock(&dev->struct_mutex); |
| 1808 | } |
| 1809 | |
| 1810 | /** |
| 1811 | * Waits for a sequence number to be signaled, and cleans up the |
| 1812 | * request and object lists appropriately for that event. |
| 1813 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 1814 | static int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1815 | i915_wait_request(struct drm_device *dev, uint32_t seqno) |
| 1816 | { |
| 1817 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1818 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1819 | int ret = 0; |
| 1820 | |
| 1821 | BUG_ON(seqno == 0); |
| 1822 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1823 | if (atomic_read(&dev_priv->mm.wedged)) |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 1824 | return -EIO; |
| 1825 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1826 | if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) { |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1827 | if (IS_IGDNG(dev)) |
| 1828 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 1829 | else |
| 1830 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1831 | if (!ier) { |
| 1832 | DRM_ERROR("something (likely vbetool) disabled " |
| 1833 | "interrupts, re-enabling\n"); |
| 1834 | i915_driver_irq_preinstall(dev); |
| 1835 | i915_driver_irq_postinstall(dev); |
| 1836 | } |
| 1837 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1838 | trace_i915_gem_request_wait_begin(dev, seqno); |
| 1839 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1840 | dev_priv->mm.waiting_gem_seqno = seqno; |
| 1841 | i915_user_irq_get(dev); |
| 1842 | ret = wait_event_interruptible(dev_priv->irq_queue, |
| 1843 | i915_seqno_passed(i915_get_gem_seqno(dev), |
| 1844 | seqno) || |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1845 | atomic_read(&dev_priv->mm.wedged)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1846 | i915_user_irq_put(dev); |
| 1847 | dev_priv->mm.waiting_gem_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1848 | |
| 1849 | trace_i915_gem_request_wait_end(dev, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1850 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1851 | if (atomic_read(&dev_priv->mm.wedged)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1852 | ret = -EIO; |
| 1853 | |
| 1854 | if (ret && ret != -ERESTARTSYS) |
| 1855 | DRM_ERROR("%s returns %d (awaiting %d at %d)\n", |
| 1856 | __func__, ret, seqno, i915_get_gem_seqno(dev)); |
| 1857 | |
| 1858 | /* Directly dispatch request retiring. While we have the work queue |
| 1859 | * to handle this, the waiter on a request often wants an associated |
| 1860 | * buffer to have made it to the inactive list, and we would need |
| 1861 | * a separate wait queue to handle that. |
| 1862 | */ |
| 1863 | if (ret == 0) |
| 1864 | i915_gem_retire_requests(dev); |
| 1865 | |
| 1866 | return ret; |
| 1867 | } |
| 1868 | |
| 1869 | static void |
| 1870 | i915_gem_flush(struct drm_device *dev, |
| 1871 | uint32_t invalidate_domains, |
| 1872 | uint32_t flush_domains) |
| 1873 | { |
| 1874 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1875 | uint32_t cmd; |
| 1876 | RING_LOCALS; |
| 1877 | |
| 1878 | #if WATCH_EXEC |
| 1879 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, |
| 1880 | invalidate_domains, flush_domains); |
| 1881 | #endif |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1882 | trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno, |
| 1883 | invalidate_domains, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1884 | |
| 1885 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
| 1886 | drm_agp_chipset_flush(dev); |
| 1887 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1888 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1889 | /* |
| 1890 | * read/write caches: |
| 1891 | * |
| 1892 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 1893 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 1894 | * also flushed at 2d versus 3d pipeline switches. |
| 1895 | * |
| 1896 | * read-only caches: |
| 1897 | * |
| 1898 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 1899 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 1900 | * |
| 1901 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 1902 | * |
| 1903 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 1904 | * invalidated when MI_EXE_FLUSH is set. |
| 1905 | * |
| 1906 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 1907 | * invalidated with every MI_FLUSH. |
| 1908 | * |
| 1909 | * TLBs: |
| 1910 | * |
| 1911 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 1912 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 1913 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 1914 | * are flushed at any MI_FLUSH. |
| 1915 | */ |
| 1916 | |
| 1917 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
| 1918 | if ((invalidate_domains|flush_domains) & |
| 1919 | I915_GEM_DOMAIN_RENDER) |
| 1920 | cmd &= ~MI_NO_WRITE_FLUSH; |
| 1921 | if (!IS_I965G(dev)) { |
| 1922 | /* |
| 1923 | * On the 965, the sampler cache always gets flushed |
| 1924 | * and this bit is reserved. |
| 1925 | */ |
| 1926 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 1927 | cmd |= MI_READ_FLUSH; |
| 1928 | } |
| 1929 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 1930 | cmd |= MI_EXE_FLUSH; |
| 1931 | |
| 1932 | #if WATCH_EXEC |
| 1933 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); |
| 1934 | #endif |
| 1935 | BEGIN_LP_RING(2); |
| 1936 | OUT_RING(cmd); |
| 1937 | OUT_RING(0); /* noop */ |
| 1938 | ADVANCE_LP_RING(); |
| 1939 | } |
| 1940 | } |
| 1941 | |
| 1942 | /** |
| 1943 | * Ensures that all rendering to the object has completed and the object is |
| 1944 | * safe to unbind from the GTT or access from the CPU. |
| 1945 | */ |
| 1946 | static int |
| 1947 | i915_gem_object_wait_rendering(struct drm_gem_object *obj) |
| 1948 | { |
| 1949 | struct drm_device *dev = obj->dev; |
| 1950 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1951 | int ret; |
| 1952 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1953 | /* This function only exists to support waiting for existing rendering, |
| 1954 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1955 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1956 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1957 | |
| 1958 | /* If there is rendering queued on the buffer being evicted, wait for |
| 1959 | * it. |
| 1960 | */ |
| 1961 | if (obj_priv->active) { |
| 1962 | #if WATCH_BUF |
| 1963 | DRM_INFO("%s: object %p wait for seqno %08x\n", |
| 1964 | __func__, obj, obj_priv->last_rendering_seqno); |
| 1965 | #endif |
| 1966 | ret = i915_wait_request(dev, obj_priv->last_rendering_seqno); |
| 1967 | if (ret != 0) |
| 1968 | return ret; |
| 1969 | } |
| 1970 | |
| 1971 | return 0; |
| 1972 | } |
| 1973 | |
| 1974 | /** |
| 1975 | * Unbinds an object from the GTT aperture. |
| 1976 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1977 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1978 | i915_gem_object_unbind(struct drm_gem_object *obj) |
| 1979 | { |
| 1980 | struct drm_device *dev = obj->dev; |
| 1981 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1982 | int ret = 0; |
| 1983 | |
| 1984 | #if WATCH_BUF |
| 1985 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); |
| 1986 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); |
| 1987 | #endif |
| 1988 | if (obj_priv->gtt_space == NULL) |
| 1989 | return 0; |
| 1990 | |
| 1991 | if (obj_priv->pin_count != 0) { |
| 1992 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 1993 | return -EINVAL; |
| 1994 | } |
| 1995 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 1996 | /* blow away mappings if mapped through GTT */ |
| 1997 | i915_gem_release_mmap(obj); |
| 1998 | |
| 1999 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) |
| 2000 | i915_gem_clear_fence_reg(obj); |
| 2001 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2002 | /* Move the object to the CPU domain to ensure that |
| 2003 | * any possible CPU writes while it's not in the GTT |
| 2004 | * are flushed when we go to remap it. This will |
| 2005 | * also ensure that all pending GPU writes are finished |
| 2006 | * before we unbind. |
| 2007 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2008 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2009 | if (ret) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2010 | if (ret != -ERESTARTSYS) |
| 2011 | DRM_ERROR("set_domain failed: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2012 | return ret; |
| 2013 | } |
| 2014 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 2015 | BUG_ON(obj_priv->active); |
| 2016 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2017 | if (obj_priv->agp_mem != NULL) { |
| 2018 | drm_unbind_agp(obj_priv->agp_mem); |
| 2019 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); |
| 2020 | obj_priv->agp_mem = NULL; |
| 2021 | } |
| 2022 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2023 | i915_gem_object_put_pages(obj); |
Chris Wilson | a32808c | 2009-09-20 21:29:47 +0100 | [diff] [blame] | 2024 | BUG_ON(obj_priv->pages_refcount); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2025 | |
| 2026 | if (obj_priv->gtt_space) { |
| 2027 | atomic_dec(&dev->gtt_count); |
| 2028 | atomic_sub(obj->size, &dev->gtt_memory); |
| 2029 | |
| 2030 | drm_mm_put_block(obj_priv->gtt_space); |
| 2031 | obj_priv->gtt_space = NULL; |
| 2032 | } |
| 2033 | |
| 2034 | /* Remove ourselves from the LRU list if present. */ |
| 2035 | if (!list_empty(&obj_priv->list)) |
| 2036 | list_del_init(&obj_priv->list); |
| 2037 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2038 | if (i915_gem_object_is_purgeable(obj_priv)) |
| 2039 | i915_gem_object_truncate(obj); |
| 2040 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2041 | trace_i915_gem_object_unbind(obj); |
| 2042 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2043 | return 0; |
| 2044 | } |
| 2045 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2046 | static struct drm_gem_object * |
| 2047 | i915_gem_find_inactive_object(struct drm_device *dev, int min_size) |
| 2048 | { |
| 2049 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2050 | struct drm_i915_gem_object *obj_priv; |
| 2051 | struct drm_gem_object *best = NULL; |
| 2052 | struct drm_gem_object *first = NULL; |
| 2053 | |
| 2054 | /* Try to find the smallest clean object */ |
| 2055 | list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) { |
| 2056 | struct drm_gem_object *obj = obj_priv->obj; |
| 2057 | if (obj->size >= min_size) { |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2058 | if ((!obj_priv->dirty || |
| 2059 | i915_gem_object_is_purgeable(obj_priv)) && |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2060 | (!best || obj->size < best->size)) { |
| 2061 | best = obj; |
| 2062 | if (best->size == min_size) |
| 2063 | return best; |
| 2064 | } |
| 2065 | if (!first) |
| 2066 | first = obj; |
| 2067 | } |
| 2068 | } |
| 2069 | |
| 2070 | return best ? best : first; |
| 2071 | } |
| 2072 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2073 | static int |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2074 | i915_gem_evict_everything(struct drm_device *dev) |
| 2075 | { |
| 2076 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2077 | uint32_t seqno; |
| 2078 | int ret; |
| 2079 | bool lists_empty; |
| 2080 | |
| 2081 | DRM_INFO("GTT full, evicting everything: " |
| 2082 | "%d objects [%d pinned], " |
| 2083 | "%d object bytes [%d pinned], " |
| 2084 | "%d/%d gtt bytes\n", |
| 2085 | atomic_read(&dev->object_count), |
| 2086 | atomic_read(&dev->pin_count), |
| 2087 | atomic_read(&dev->object_memory), |
| 2088 | atomic_read(&dev->pin_memory), |
| 2089 | atomic_read(&dev->gtt_memory), |
| 2090 | dev->gtt_total); |
| 2091 | |
| 2092 | spin_lock(&dev_priv->mm.active_list_lock); |
| 2093 | lists_empty = (list_empty(&dev_priv->mm.inactive_list) && |
| 2094 | list_empty(&dev_priv->mm.flushing_list) && |
| 2095 | list_empty(&dev_priv->mm.active_list)); |
| 2096 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 2097 | |
| 2098 | if (lists_empty) { |
| 2099 | DRM_ERROR("GTT full, but lists empty!\n"); |
| 2100 | return -ENOSPC; |
| 2101 | } |
| 2102 | |
| 2103 | /* Flush everything (on to the inactive lists) and evict */ |
| 2104 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 2105 | seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS); |
| 2106 | if (seqno == 0) |
| 2107 | return -ENOMEM; |
| 2108 | |
| 2109 | ret = i915_wait_request(dev, seqno); |
| 2110 | if (ret) |
| 2111 | return ret; |
| 2112 | |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 2113 | ret = i915_gem_evict_from_inactive_list(dev); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2114 | if (ret) |
| 2115 | return ret; |
| 2116 | |
| 2117 | spin_lock(&dev_priv->mm.active_list_lock); |
| 2118 | lists_empty = (list_empty(&dev_priv->mm.inactive_list) && |
| 2119 | list_empty(&dev_priv->mm.flushing_list) && |
| 2120 | list_empty(&dev_priv->mm.active_list)); |
| 2121 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 2122 | BUG_ON(!lists_empty); |
| 2123 | |
| 2124 | return 0; |
| 2125 | } |
| 2126 | |
| 2127 | static int |
| 2128 | i915_gem_evict_something(struct drm_device *dev, int min_size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2129 | { |
| 2130 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2131 | struct drm_gem_object *obj; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2132 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2133 | |
| 2134 | for (;;) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2135 | i915_gem_retire_requests(dev); |
| 2136 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2137 | /* If there's an inactive buffer available now, grab it |
| 2138 | * and be done. |
| 2139 | */ |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2140 | obj = i915_gem_find_inactive_object(dev, min_size); |
| 2141 | if (obj) { |
| 2142 | struct drm_i915_gem_object *obj_priv; |
| 2143 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2144 | #if WATCH_LRU |
| 2145 | DRM_INFO("%s: evicting %p\n", __func__, obj); |
| 2146 | #endif |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2147 | obj_priv = obj->driver_private; |
| 2148 | BUG_ON(obj_priv->pin_count != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2149 | BUG_ON(obj_priv->active); |
| 2150 | |
| 2151 | /* Wait on the rendering and unbind the buffer. */ |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2152 | return i915_gem_object_unbind(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2153 | } |
| 2154 | |
| 2155 | /* If we didn't get anything, but the ring is still processing |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2156 | * things, wait for the next to finish and hopefully leave us |
| 2157 | * a buffer to evict. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2158 | */ |
| 2159 | if (!list_empty(&dev_priv->mm.request_list)) { |
| 2160 | struct drm_i915_gem_request *request; |
| 2161 | |
| 2162 | request = list_first_entry(&dev_priv->mm.request_list, |
| 2163 | struct drm_i915_gem_request, |
| 2164 | list); |
| 2165 | |
| 2166 | ret = i915_wait_request(dev, request->seqno); |
| 2167 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2168 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2169 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2170 | continue; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2171 | } |
| 2172 | |
| 2173 | /* If we didn't have anything on the request list but there |
| 2174 | * are buffers awaiting a flush, emit one and try again. |
| 2175 | * When we wait on it, those buffers waiting for that flush |
| 2176 | * will get moved to inactive. |
| 2177 | */ |
| 2178 | if (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2179 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2180 | |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2181 | /* Find an object that we can immediately reuse */ |
| 2182 | list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) { |
| 2183 | obj = obj_priv->obj; |
| 2184 | if (obj->size >= min_size) |
| 2185 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2186 | |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2187 | obj = NULL; |
| 2188 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2189 | |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2190 | if (obj != NULL) { |
| 2191 | uint32_t seqno; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2192 | |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2193 | i915_gem_flush(dev, |
| 2194 | obj->write_domain, |
| 2195 | obj->write_domain); |
| 2196 | seqno = i915_add_request(dev, NULL, obj->write_domain); |
| 2197 | if (seqno == 0) |
| 2198 | return -ENOMEM; |
| 2199 | |
| 2200 | ret = i915_wait_request(dev, seqno); |
| 2201 | if (ret) |
| 2202 | return ret; |
| 2203 | |
| 2204 | continue; |
| 2205 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2206 | } |
| 2207 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2208 | /* If we didn't do any of the above, there's no single buffer |
| 2209 | * large enough to swap out for the new one, so just evict |
| 2210 | * everything and start again. (This should be rare.) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2211 | */ |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2212 | if (!list_empty (&dev_priv->mm.inactive_list)) { |
| 2213 | DRM_INFO("GTT full, evicting inactive buffers\n"); |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 2214 | return i915_gem_evict_from_inactive_list(dev); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2215 | } else |
| 2216 | return i915_gem_evict_everything(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2217 | } |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 2218 | } |
| 2219 | |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 2220 | int |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2221 | i915_gem_object_get_pages(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2222 | { |
| 2223 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2224 | int page_count, i; |
| 2225 | struct address_space *mapping; |
| 2226 | struct inode *inode; |
| 2227 | struct page *page; |
| 2228 | int ret; |
| 2229 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2230 | if (obj_priv->pages_refcount++ != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2231 | return 0; |
| 2232 | |
| 2233 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2234 | * at this point until we release them. |
| 2235 | */ |
| 2236 | page_count = obj->size / PAGE_SIZE; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2237 | BUG_ON(obj_priv->pages != NULL); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 2238 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2239 | if (obj_priv->pages == NULL) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2240 | DRM_ERROR("Failed to allocate page list\n"); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2241 | obj_priv->pages_refcount--; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2242 | return -ENOMEM; |
| 2243 | } |
| 2244 | |
| 2245 | inode = obj->filp->f_path.dentry->d_inode; |
| 2246 | mapping = inode->i_mapping; |
| 2247 | for (i = 0; i < page_count; i++) { |
| 2248 | page = read_mapping_page(mapping, i, NULL); |
| 2249 | if (IS_ERR(page)) { |
| 2250 | ret = PTR_ERR(page); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2251 | i915_gem_object_put_pages(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2252 | return ret; |
| 2253 | } |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2254 | obj_priv->pages[i] = page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2255 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2256 | |
| 2257 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 2258 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2259 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2260 | return 0; |
| 2261 | } |
| 2262 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2263 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2264 | { |
| 2265 | struct drm_gem_object *obj = reg->obj; |
| 2266 | struct drm_device *dev = obj->dev; |
| 2267 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2268 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2269 | int regnum = obj_priv->fence_reg; |
| 2270 | uint64_t val; |
| 2271 | |
| 2272 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2273 | 0xfffff000) << 32; |
| 2274 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2275 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2276 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2277 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2278 | val |= I965_FENCE_REG_VALID; |
| 2279 | |
| 2280 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); |
| 2281 | } |
| 2282 | |
| 2283 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2284 | { |
| 2285 | struct drm_gem_object *obj = reg->obj; |
| 2286 | struct drm_device *dev = obj->dev; |
| 2287 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2288 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2289 | int regnum = obj_priv->fence_reg; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2290 | int tile_width; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2291 | uint32_t fence_reg, val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2292 | uint32_t pitch_val; |
| 2293 | |
| 2294 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2295 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Linus Torvalds | f06da26 | 2009-02-09 08:57:29 -0800 | [diff] [blame] | 2296 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2297 | __func__, obj_priv->gtt_offset, obj->size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2298 | return; |
| 2299 | } |
| 2300 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2301 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2302 | HAS_128_BYTE_Y_TILING(dev)) |
| 2303 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2304 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2305 | tile_width = 512; |
| 2306 | |
| 2307 | /* Note: pitch better be a power of two tile widths */ |
| 2308 | pitch_val = obj_priv->stride / tile_width; |
| 2309 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2310 | |
| 2311 | val = obj_priv->gtt_offset; |
| 2312 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2313 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2314 | val |= I915_FENCE_SIZE_BITS(obj->size); |
| 2315 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2316 | val |= I830_FENCE_REG_VALID; |
| 2317 | |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2318 | if (regnum < 8) |
| 2319 | fence_reg = FENCE_REG_830_0 + (regnum * 4); |
| 2320 | else |
| 2321 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); |
| 2322 | I915_WRITE(fence_reg, val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2323 | } |
| 2324 | |
| 2325 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2326 | { |
| 2327 | struct drm_gem_object *obj = reg->obj; |
| 2328 | struct drm_device *dev = obj->dev; |
| 2329 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2330 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2331 | int regnum = obj_priv->fence_reg; |
| 2332 | uint32_t val; |
| 2333 | uint32_t pitch_val; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2334 | uint32_t fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2335 | |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2336 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2337 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2338 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2339 | __func__, obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2340 | return; |
| 2341 | } |
| 2342 | |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2343 | pitch_val = obj_priv->stride / 128; |
| 2344 | pitch_val = ffs(pitch_val) - 1; |
| 2345 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2346 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2347 | val = obj_priv->gtt_offset; |
| 2348 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2349 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2350 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
| 2351 | WARN_ON(fence_size_bits & ~0x00000f00); |
| 2352 | val |= fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2353 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2354 | val |= I830_FENCE_REG_VALID; |
| 2355 | |
| 2356 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2357 | } |
| 2358 | |
| 2359 | /** |
| 2360 | * i915_gem_object_get_fence_reg - set up a fence reg for an object |
| 2361 | * @obj: object to map through a fence reg |
| 2362 | * |
| 2363 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2364 | * to them without having to worry about swizzling if the object is tiled. |
| 2365 | * |
| 2366 | * This function walks the fence regs looking for a free one for @obj, |
| 2367 | * stealing one if it can't find any. |
| 2368 | * |
| 2369 | * It then sets up the reg based on the object's properties: address, pitch |
| 2370 | * and tiling format. |
| 2371 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2372 | int |
| 2373 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2374 | { |
| 2375 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2376 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2377 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2378 | struct drm_i915_fence_reg *reg = NULL; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2379 | struct drm_i915_gem_object *old_obj_priv = NULL; |
| 2380 | int i, ret, avail; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2381 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2382 | /* Just update our place in the LRU if our fence is getting used. */ |
| 2383 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
| 2384 | list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list); |
| 2385 | return 0; |
| 2386 | } |
| 2387 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2388 | switch (obj_priv->tiling_mode) { |
| 2389 | case I915_TILING_NONE: |
| 2390 | WARN(1, "allocating a fence for non-tiled object?\n"); |
| 2391 | break; |
| 2392 | case I915_TILING_X: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2393 | if (!obj_priv->stride) |
| 2394 | return -EINVAL; |
| 2395 | WARN((obj_priv->stride & (512 - 1)), |
| 2396 | "object 0x%08x is X tiled but has non-512B pitch\n", |
| 2397 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2398 | break; |
| 2399 | case I915_TILING_Y: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2400 | if (!obj_priv->stride) |
| 2401 | return -EINVAL; |
| 2402 | WARN((obj_priv->stride & (128 - 1)), |
| 2403 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
| 2404 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2405 | break; |
| 2406 | } |
| 2407 | |
| 2408 | /* First try to find a free reg */ |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2409 | avail = 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2410 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2411 | reg = &dev_priv->fence_regs[i]; |
| 2412 | if (!reg->obj) |
| 2413 | break; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2414 | |
| 2415 | old_obj_priv = reg->obj->driver_private; |
| 2416 | if (!old_obj_priv->pin_count) |
| 2417 | avail++; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2418 | } |
| 2419 | |
| 2420 | /* None available, try to steal one or wait for a user to finish */ |
| 2421 | if (i == dev_priv->num_fence_regs) { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2422 | struct drm_gem_object *old_obj = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2423 | |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2424 | if (avail == 0) |
Chris Wilson | 2939e1f | 2009-06-06 09:46:03 +0100 | [diff] [blame] | 2425 | return -ENOSPC; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2426 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2427 | list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list, |
| 2428 | fence_list) { |
| 2429 | old_obj = old_obj_priv->obj; |
Chris Wilson | d7619c4 | 2009-02-11 14:26:47 +0000 | [diff] [blame] | 2430 | |
| 2431 | if (old_obj_priv->pin_count) |
| 2432 | continue; |
| 2433 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2434 | /* Take a reference, as otherwise the wait_rendering |
| 2435 | * below may cause the object to get freed out from |
| 2436 | * under us. |
| 2437 | */ |
| 2438 | drm_gem_object_reference(old_obj); |
| 2439 | |
Chris Wilson | d7619c4 | 2009-02-11 14:26:47 +0000 | [diff] [blame] | 2440 | /* i915 uses fences for GPU access to tiled buffers */ |
| 2441 | if (IS_I965G(dev) || !old_obj_priv->active) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2442 | break; |
Chris Wilson | d7619c4 | 2009-02-11 14:26:47 +0000 | [diff] [blame] | 2443 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2444 | /* This brings the object to the head of the LRU if it |
| 2445 | * had been written to. The only way this should |
| 2446 | * result in us waiting longer than the expected |
| 2447 | * optimal amount of time is if there was a |
| 2448 | * fence-using buffer later that was read-only. |
| 2449 | */ |
| 2450 | i915_gem_object_flush_gpu_write_domain(old_obj); |
| 2451 | ret = i915_gem_object_wait_rendering(old_obj); |
Chris Wilson | 58c2fb6 | 2009-09-01 12:02:39 +0100 | [diff] [blame] | 2452 | if (ret != 0) { |
| 2453 | drm_gem_object_unreference(old_obj); |
Chris Wilson | d7619c4 | 2009-02-11 14:26:47 +0000 | [diff] [blame] | 2454 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2455 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2456 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2457 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2458 | } |
| 2459 | |
| 2460 | /* |
| 2461 | * Zap this virtual mapping so we can set up a fence again |
| 2462 | * for this object next time we need it. |
| 2463 | */ |
Chris Wilson | 58c2fb6 | 2009-09-01 12:02:39 +0100 | [diff] [blame] | 2464 | i915_gem_release_mmap(old_obj); |
| 2465 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2466 | i = old_obj_priv->fence_reg; |
Chris Wilson | 58c2fb6 | 2009-09-01 12:02:39 +0100 | [diff] [blame] | 2467 | reg = &dev_priv->fence_regs[i]; |
| 2468 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2469 | old_obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2470 | list_del_init(&old_obj_priv->fence_list); |
Chris Wilson | 58c2fb6 | 2009-09-01 12:02:39 +0100 | [diff] [blame] | 2471 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2472 | drm_gem_object_unreference(old_obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2473 | } |
| 2474 | |
| 2475 | obj_priv->fence_reg = i; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2476 | list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list); |
| 2477 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2478 | reg->obj = obj; |
| 2479 | |
| 2480 | if (IS_I965G(dev)) |
| 2481 | i965_write_fence_reg(reg); |
| 2482 | else if (IS_I9XX(dev)) |
| 2483 | i915_write_fence_reg(reg); |
| 2484 | else |
| 2485 | i830_write_fence_reg(reg); |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2486 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2487 | trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode); |
| 2488 | |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2489 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2490 | } |
| 2491 | |
| 2492 | /** |
| 2493 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2494 | * @obj: object to clear |
| 2495 | * |
| 2496 | * Zeroes out the fence register itself and clears out the associated |
| 2497 | * data structures in dev_priv and obj_priv. |
| 2498 | */ |
| 2499 | static void |
| 2500 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) |
| 2501 | { |
| 2502 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2503 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2504 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2505 | |
| 2506 | if (IS_I965G(dev)) |
| 2507 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2508 | else { |
| 2509 | uint32_t fence_reg; |
| 2510 | |
| 2511 | if (obj_priv->fence_reg < 8) |
| 2512 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; |
| 2513 | else |
| 2514 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - |
| 2515 | 8) * 4; |
| 2516 | |
| 2517 | I915_WRITE(fence_reg, 0); |
| 2518 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2519 | |
| 2520 | dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL; |
| 2521 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2522 | list_del_init(&obj_priv->fence_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2523 | } |
| 2524 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2525 | /** |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2526 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access |
| 2527 | * to the buffer to finish, and then resets the fence register. |
| 2528 | * @obj: tiled object holding a fence register. |
| 2529 | * |
| 2530 | * Zeroes out the fence register itself and clears out the associated |
| 2531 | * data structures in dev_priv and obj_priv. |
| 2532 | */ |
| 2533 | int |
| 2534 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj) |
| 2535 | { |
| 2536 | struct drm_device *dev = obj->dev; |
| 2537 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2538 | |
| 2539 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) |
| 2540 | return 0; |
| 2541 | |
| 2542 | /* On the i915, GPU access to tiled buffers is via a fence, |
| 2543 | * therefore we must wait for any outstanding access to complete |
| 2544 | * before clearing the fence. |
| 2545 | */ |
| 2546 | if (!IS_I965G(dev)) { |
| 2547 | int ret; |
| 2548 | |
| 2549 | i915_gem_object_flush_gpu_write_domain(obj); |
| 2550 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2551 | ret = i915_gem_object_wait_rendering(obj); |
| 2552 | if (ret != 0) |
| 2553 | return ret; |
| 2554 | } |
| 2555 | |
| 2556 | i915_gem_clear_fence_reg (obj); |
| 2557 | |
| 2558 | return 0; |
| 2559 | } |
| 2560 | |
| 2561 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2562 | * Finds free space in the GTT aperture and binds the object there. |
| 2563 | */ |
| 2564 | static int |
| 2565 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) |
| 2566 | { |
| 2567 | struct drm_device *dev = obj->dev; |
| 2568 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2569 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2570 | struct drm_mm_node *free_space; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2571 | bool retry_alloc = false; |
| 2572 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2573 | |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 2574 | if (dev_priv->mm.suspended) |
| 2575 | return -EBUSY; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2576 | |
| 2577 | if (obj_priv->madv == I915_MADV_DONTNEED) { |
| 2578 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2579 | return -EINVAL; |
| 2580 | } |
| 2581 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2582 | if (alignment == 0) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2583 | alignment = i915_gem_get_gtt_alignment(obj); |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2584 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2585 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2586 | return -EINVAL; |
| 2587 | } |
| 2588 | |
| 2589 | search_free: |
| 2590 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
| 2591 | obj->size, alignment, 0); |
| 2592 | if (free_space != NULL) { |
| 2593 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, |
| 2594 | alignment); |
| 2595 | if (obj_priv->gtt_space != NULL) { |
| 2596 | obj_priv->gtt_space->private = obj; |
| 2597 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
| 2598 | } |
| 2599 | } |
| 2600 | if (obj_priv->gtt_space == NULL) { |
| 2601 | /* If the gtt is empty and we're still having trouble |
| 2602 | * fitting our object in, we're out of memory. |
| 2603 | */ |
| 2604 | #if WATCH_LRU |
| 2605 | DRM_INFO("%s: GTT full, evicting something\n", __func__); |
| 2606 | #endif |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2607 | ret = i915_gem_evict_something(dev, obj->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2608 | if (ret != 0) { |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 2609 | if (ret != -ERESTARTSYS) |
| 2610 | DRM_ERROR("Failed to evict a buffer %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2611 | return ret; |
| 2612 | } |
| 2613 | goto search_free; |
| 2614 | } |
| 2615 | |
| 2616 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 2617 | DRM_INFO("Binding object of size %zd at 0x%08x\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2618 | obj->size, obj_priv->gtt_offset); |
| 2619 | #endif |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2620 | if (retry_alloc) { |
| 2621 | i915_gem_object_set_page_gfp_mask (obj, |
| 2622 | i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY); |
| 2623 | } |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2624 | ret = i915_gem_object_get_pages(obj); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2625 | if (retry_alloc) { |
| 2626 | i915_gem_object_set_page_gfp_mask (obj, |
| 2627 | i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY); |
| 2628 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2629 | if (ret) { |
| 2630 | drm_mm_put_block(obj_priv->gtt_space); |
| 2631 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2632 | |
| 2633 | if (ret == -ENOMEM) { |
| 2634 | /* first try to clear up some space from the GTT */ |
| 2635 | ret = i915_gem_evict_something(dev, obj->size); |
| 2636 | if (ret) { |
| 2637 | if (ret != -ERESTARTSYS) |
| 2638 | DRM_ERROR("Failed to allocate space for backing pages %d\n", ret); |
| 2639 | |
| 2640 | /* now try to shrink everyone else */ |
| 2641 | if (! retry_alloc) { |
| 2642 | retry_alloc = true; |
| 2643 | goto search_free; |
| 2644 | } |
| 2645 | |
| 2646 | return ret; |
| 2647 | } |
| 2648 | |
| 2649 | goto search_free; |
| 2650 | } |
| 2651 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2652 | return ret; |
| 2653 | } |
| 2654 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2655 | /* Create an AGP memory structure pointing at our pages, and bind it |
| 2656 | * into the GTT. |
| 2657 | */ |
| 2658 | obj_priv->agp_mem = drm_agp_bind_pages(dev, |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2659 | obj_priv->pages, |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2660 | obj->size >> PAGE_SHIFT, |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 2661 | obj_priv->gtt_offset, |
| 2662 | obj_priv->agp_type); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2663 | if (obj_priv->agp_mem == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2664 | i915_gem_object_put_pages(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2665 | drm_mm_put_block(obj_priv->gtt_space); |
| 2666 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2667 | |
| 2668 | ret = i915_gem_evict_something(dev, obj->size); |
| 2669 | if (ret) { |
| 2670 | if (ret != -ERESTARTSYS) |
| 2671 | DRM_ERROR("Failed to allocate space to bind AGP: %d\n", ret); |
| 2672 | return ret; |
| 2673 | } |
| 2674 | |
| 2675 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2676 | } |
| 2677 | atomic_inc(&dev->gtt_count); |
| 2678 | atomic_add(obj->size, &dev->gtt_memory); |
| 2679 | |
| 2680 | /* Assert that the object is not currently in any GPU domain. As it |
| 2681 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2682 | * a GPU cache |
| 2683 | */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 2684 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
| 2685 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2686 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2687 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
| 2688 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2689 | return 0; |
| 2690 | } |
| 2691 | |
| 2692 | void |
| 2693 | i915_gem_clflush_object(struct drm_gem_object *obj) |
| 2694 | { |
| 2695 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2696 | |
| 2697 | /* If we don't have a page list set up, then we're not pinned |
| 2698 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2699 | * again at bind time. |
| 2700 | */ |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2701 | if (obj_priv->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2702 | return; |
| 2703 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2704 | trace_i915_gem_object_clflush(obj); |
| 2705 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2706 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2707 | } |
| 2708 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2709 | /** Flushes any GPU write domain for the object if it's dirty. */ |
| 2710 | static void |
| 2711 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) |
| 2712 | { |
| 2713 | struct drm_device *dev = obj->dev; |
| 2714 | uint32_t seqno; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2715 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2716 | |
| 2717 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
| 2718 | return; |
| 2719 | |
| 2720 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2721 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2722 | i915_gem_flush(dev, 0, obj->write_domain); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2723 | seqno = i915_add_request(dev, NULL, obj->write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2724 | obj->write_domain = 0; |
| 2725 | i915_gem_object_move_to_active(obj, seqno); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2726 | |
| 2727 | trace_i915_gem_object_change_domain(obj, |
| 2728 | obj->read_domains, |
| 2729 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2730 | } |
| 2731 | |
| 2732 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2733 | static void |
| 2734 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) |
| 2735 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2736 | uint32_t old_write_domain; |
| 2737 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2738 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
| 2739 | return; |
| 2740 | |
| 2741 | /* No actual flushing is required for the GTT write domain. Writes |
| 2742 | * to it immediately go to main memory as far as we know, so there's |
| 2743 | * no chipset flush. It also doesn't land in render cache. |
| 2744 | */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2745 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2746 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2747 | |
| 2748 | trace_i915_gem_object_change_domain(obj, |
| 2749 | obj->read_domains, |
| 2750 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2751 | } |
| 2752 | |
| 2753 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2754 | static void |
| 2755 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) |
| 2756 | { |
| 2757 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2758 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2759 | |
| 2760 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) |
| 2761 | return; |
| 2762 | |
| 2763 | i915_gem_clflush_object(obj); |
| 2764 | drm_agp_chipset_flush(dev); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2765 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2766 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2767 | |
| 2768 | trace_i915_gem_object_change_domain(obj, |
| 2769 | obj->read_domains, |
| 2770 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2771 | } |
| 2772 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2773 | /** |
| 2774 | * Moves a single object to the GTT read, and possibly write domain. |
| 2775 | * |
| 2776 | * This function returns when the move is complete, including waiting on |
| 2777 | * flushes to occur. |
| 2778 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2779 | int |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2780 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
| 2781 | { |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2782 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2783 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2784 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2785 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2786 | /* Not valid to be called on unbound objects. */ |
| 2787 | if (obj_priv->gtt_space == NULL) |
| 2788 | return -EINVAL; |
| 2789 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2790 | i915_gem_object_flush_gpu_write_domain(obj); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2791 | /* Wait on any GPU rendering and flushing to occur. */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2792 | ret = i915_gem_object_wait_rendering(obj); |
| 2793 | if (ret != 0) |
| 2794 | return ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2795 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2796 | old_write_domain = obj->write_domain; |
| 2797 | old_read_domains = obj->read_domains; |
| 2798 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2799 | /* If we're writing through the GTT domain, then CPU and GPU caches |
| 2800 | * will need to be invalidated at next use. |
| 2801 | */ |
| 2802 | if (write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2803 | obj->read_domains &= I915_GEM_DOMAIN_GTT; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2804 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2805 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2806 | |
| 2807 | /* It should now be out of any other write domains, and we can update |
| 2808 | * the domain values for our changes. |
| 2809 | */ |
| 2810 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2811 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2812 | if (write) { |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2813 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2814 | obj_priv->dirty = 1; |
| 2815 | } |
| 2816 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2817 | trace_i915_gem_object_change_domain(obj, |
| 2818 | old_read_domains, |
| 2819 | old_write_domain); |
| 2820 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2821 | return 0; |
| 2822 | } |
| 2823 | |
| 2824 | /** |
| 2825 | * Moves a single object to the CPU read, and possibly write domain. |
| 2826 | * |
| 2827 | * This function returns when the move is complete, including waiting on |
| 2828 | * flushes to occur. |
| 2829 | */ |
| 2830 | static int |
| 2831 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) |
| 2832 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2833 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2834 | int ret; |
| 2835 | |
| 2836 | i915_gem_object_flush_gpu_write_domain(obj); |
| 2837 | /* Wait on any GPU rendering and flushing to occur. */ |
| 2838 | ret = i915_gem_object_wait_rendering(obj); |
| 2839 | if (ret != 0) |
| 2840 | return ret; |
| 2841 | |
| 2842 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2843 | |
| 2844 | /* If we have a partially-valid cache of the object in the CPU, |
| 2845 | * finish invalidating it and free the per-page flags. |
| 2846 | */ |
| 2847 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 2848 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2849 | old_write_domain = obj->write_domain; |
| 2850 | old_read_domains = obj->read_domains; |
| 2851 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2852 | /* Flush the CPU cache if it's still invalid. */ |
| 2853 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
| 2854 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2855 | |
| 2856 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 2857 | } |
| 2858 | |
| 2859 | /* It should now be out of any other write domains, and we can update |
| 2860 | * the domain values for our changes. |
| 2861 | */ |
| 2862 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 2863 | |
| 2864 | /* If we're writing through the CPU, then the GPU read domains will |
| 2865 | * need to be invalidated at next use. |
| 2866 | */ |
| 2867 | if (write) { |
| 2868 | obj->read_domains &= I915_GEM_DOMAIN_CPU; |
| 2869 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 2870 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2871 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2872 | trace_i915_gem_object_change_domain(obj, |
| 2873 | old_read_domains, |
| 2874 | old_write_domain); |
| 2875 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2876 | return 0; |
| 2877 | } |
| 2878 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2879 | /* |
| 2880 | * Set the next domain for the specified object. This |
| 2881 | * may not actually perform the necessary flushing/invaliding though, |
| 2882 | * as that may want to be batched with other set_domain operations |
| 2883 | * |
| 2884 | * This is (we hope) the only really tricky part of gem. The goal |
| 2885 | * is fairly simple -- track which caches hold bits of the object |
| 2886 | * and make sure they remain coherent. A few concrete examples may |
| 2887 | * help to explain how it works. For shorthand, we use the notation |
| 2888 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 2889 | * a pair of read and write domain masks. |
| 2890 | * |
| 2891 | * Case 1: the batch buffer |
| 2892 | * |
| 2893 | * 1. Allocated |
| 2894 | * 2. Written by CPU |
| 2895 | * 3. Mapped to GTT |
| 2896 | * 4. Read by GPU |
| 2897 | * 5. Unmapped from GTT |
| 2898 | * 6. Freed |
| 2899 | * |
| 2900 | * Let's take these a step at a time |
| 2901 | * |
| 2902 | * 1. Allocated |
| 2903 | * Pages allocated from the kernel may still have |
| 2904 | * cache contents, so we set them to (CPU, CPU) always. |
| 2905 | * 2. Written by CPU (using pwrite) |
| 2906 | * The pwrite function calls set_domain (CPU, CPU) and |
| 2907 | * this function does nothing (as nothing changes) |
| 2908 | * 3. Mapped by GTT |
| 2909 | * This function asserts that the object is not |
| 2910 | * currently in any GPU-based read or write domains |
| 2911 | * 4. Read by GPU |
| 2912 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 2913 | * As write_domain is zero, this function adds in the |
| 2914 | * current read domains (CPU+COMMAND, 0). |
| 2915 | * flush_domains is set to CPU. |
| 2916 | * invalidate_domains is set to COMMAND |
| 2917 | * clflush is run to get data out of the CPU caches |
| 2918 | * then i915_dev_set_domain calls i915_gem_flush to |
| 2919 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 2920 | * 5. Unmapped from GTT |
| 2921 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 2922 | * flush_domains and invalidate_domains end up both zero |
| 2923 | * so no flushing/invalidating happens |
| 2924 | * 6. Freed |
| 2925 | * yay, done |
| 2926 | * |
| 2927 | * Case 2: The shared render buffer |
| 2928 | * |
| 2929 | * 1. Allocated |
| 2930 | * 2. Mapped to GTT |
| 2931 | * 3. Read/written by GPU |
| 2932 | * 4. set_domain to (CPU,CPU) |
| 2933 | * 5. Read/written by CPU |
| 2934 | * 6. Read/written by GPU |
| 2935 | * |
| 2936 | * 1. Allocated |
| 2937 | * Same as last example, (CPU, CPU) |
| 2938 | * 2. Mapped to GTT |
| 2939 | * Nothing changes (assertions find that it is not in the GPU) |
| 2940 | * 3. Read/written by GPU |
| 2941 | * execbuffer calls set_domain (RENDER, RENDER) |
| 2942 | * flush_domains gets CPU |
| 2943 | * invalidate_domains gets GPU |
| 2944 | * clflush (obj) |
| 2945 | * MI_FLUSH and drm_agp_chipset_flush |
| 2946 | * 4. set_domain (CPU, CPU) |
| 2947 | * flush_domains gets GPU |
| 2948 | * invalidate_domains gets CPU |
| 2949 | * wait_rendering (obj) to make sure all drawing is complete. |
| 2950 | * This will include an MI_FLUSH to get the data from GPU |
| 2951 | * to memory |
| 2952 | * clflush (obj) to invalidate the CPU cache |
| 2953 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 2954 | * 5. Read/written by CPU |
| 2955 | * cache lines are loaded and dirtied |
| 2956 | * 6. Read written by GPU |
| 2957 | * Same as last GPU access |
| 2958 | * |
| 2959 | * Case 3: The constant buffer |
| 2960 | * |
| 2961 | * 1. Allocated |
| 2962 | * 2. Written by CPU |
| 2963 | * 3. Read by GPU |
| 2964 | * 4. Updated (written) by CPU again |
| 2965 | * 5. Read by GPU |
| 2966 | * |
| 2967 | * 1. Allocated |
| 2968 | * (CPU, CPU) |
| 2969 | * 2. Written by CPU |
| 2970 | * (CPU, CPU) |
| 2971 | * 3. Read by GPU |
| 2972 | * (CPU+RENDER, 0) |
| 2973 | * flush_domains = CPU |
| 2974 | * invalidate_domains = RENDER |
| 2975 | * clflush (obj) |
| 2976 | * MI_FLUSH |
| 2977 | * drm_agp_chipset_flush |
| 2978 | * 4. Updated (written) by CPU again |
| 2979 | * (CPU, CPU) |
| 2980 | * flush_domains = 0 (no previous write domain) |
| 2981 | * invalidate_domains = 0 (no new read domains) |
| 2982 | * 5. Read by GPU |
| 2983 | * (CPU+RENDER, 0) |
| 2984 | * flush_domains = CPU |
| 2985 | * invalidate_domains = RENDER |
| 2986 | * clflush (obj) |
| 2987 | * MI_FLUSH |
| 2988 | * drm_agp_chipset_flush |
| 2989 | */ |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 2990 | static void |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 2991 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2992 | { |
| 2993 | struct drm_device *dev = obj->dev; |
| 2994 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2995 | uint32_t invalidate_domains = 0; |
| 2996 | uint32_t flush_domains = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2997 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2998 | |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 2999 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
| 3000 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3001 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3002 | intel_mark_busy(dev, obj); |
| 3003 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3004 | #if WATCH_BUF |
| 3005 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", |
| 3006 | __func__, obj, |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3007 | obj->read_domains, obj->pending_read_domains, |
| 3008 | obj->write_domain, obj->pending_write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3009 | #endif |
| 3010 | /* |
| 3011 | * If the object isn't moving to a new write domain, |
| 3012 | * let the object stay in multiple read domains |
| 3013 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3014 | if (obj->pending_write_domain == 0) |
| 3015 | obj->pending_read_domains |= obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3016 | else |
| 3017 | obj_priv->dirty = 1; |
| 3018 | |
| 3019 | /* |
| 3020 | * Flush the current write domain if |
| 3021 | * the new read domains don't match. Invalidate |
| 3022 | * any read domains which differ from the old |
| 3023 | * write domain |
| 3024 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3025 | if (obj->write_domain && |
| 3026 | obj->write_domain != obj->pending_read_domains) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3027 | flush_domains |= obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3028 | invalidate_domains |= |
| 3029 | obj->pending_read_domains & ~obj->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3030 | } |
| 3031 | /* |
| 3032 | * Invalidate any read caches which may have |
| 3033 | * stale data. That is, any new read domains. |
| 3034 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3035 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3036 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { |
| 3037 | #if WATCH_BUF |
| 3038 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", |
| 3039 | __func__, flush_domains, invalidate_domains); |
| 3040 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3041 | i915_gem_clflush_object(obj); |
| 3042 | } |
| 3043 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3044 | old_read_domains = obj->read_domains; |
| 3045 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3046 | /* The actual obj->write_domain will be updated with |
| 3047 | * pending_write_domain after we emit the accumulated flush for all |
| 3048 | * of our domain changes in execbuffers (which clears objects' |
| 3049 | * write_domains). So if we have a current write domain that we |
| 3050 | * aren't changing, set pending_write_domain to that. |
| 3051 | */ |
| 3052 | if (flush_domains == 0 && obj->pending_write_domain == 0) |
| 3053 | obj->pending_write_domain = obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3054 | obj->read_domains = obj->pending_read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3055 | |
| 3056 | dev->invalidate_domains |= invalidate_domains; |
| 3057 | dev->flush_domains |= flush_domains; |
| 3058 | #if WATCH_BUF |
| 3059 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", |
| 3060 | __func__, |
| 3061 | obj->read_domains, obj->write_domain, |
| 3062 | dev->invalidate_domains, dev->flush_domains); |
| 3063 | #endif |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3064 | |
| 3065 | trace_i915_gem_object_change_domain(obj, |
| 3066 | old_read_domains, |
| 3067 | obj->write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3068 | } |
| 3069 | |
| 3070 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3071 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3072 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3073 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 3074 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 3075 | */ |
| 3076 | static void |
| 3077 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) |
| 3078 | { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3079 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 3080 | |
| 3081 | if (!obj_priv->page_cpu_valid) |
| 3082 | return; |
| 3083 | |
| 3084 | /* If we're partially in the CPU read domain, finish moving it in. |
| 3085 | */ |
| 3086 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3087 | int i; |
| 3088 | |
| 3089 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { |
| 3090 | if (obj_priv->page_cpu_valid[i]) |
| 3091 | continue; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3092 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3093 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3094 | } |
| 3095 | |
| 3096 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 3097 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 3098 | */ |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3099 | kfree(obj_priv->page_cpu_valid); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3100 | obj_priv->page_cpu_valid = NULL; |
| 3101 | } |
| 3102 | |
| 3103 | /** |
| 3104 | * Set the CPU read domain on a range of the object. |
| 3105 | * |
| 3106 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 3107 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 3108 | * pages have been flushed, and will be respected by |
| 3109 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 3110 | * of the whole object. |
| 3111 | * |
| 3112 | * This function returns when the move is complete, including waiting on |
| 3113 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3114 | */ |
| 3115 | static int |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3116 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 3117 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3118 | { |
| 3119 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3120 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3121 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3122 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3123 | if (offset == 0 && size == obj->size) |
| 3124 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 3125 | |
| 3126 | i915_gem_object_flush_gpu_write_domain(obj); |
| 3127 | /* Wait on any GPU rendering and flushing to occur. */ |
| 3128 | ret = i915_gem_object_wait_rendering(obj); |
| 3129 | if (ret != 0) |
| 3130 | return ret; |
| 3131 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3132 | |
| 3133 | /* If we're already fully in the CPU read domain, we're done. */ |
| 3134 | if (obj_priv->page_cpu_valid == NULL && |
| 3135 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3136 | return 0; |
| 3137 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3138 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 3139 | * newly adding I915_GEM_DOMAIN_CPU |
| 3140 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3141 | if (obj_priv->page_cpu_valid == NULL) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3142 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
| 3143 | GFP_KERNEL); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3144 | if (obj_priv->page_cpu_valid == NULL) |
| 3145 | return -ENOMEM; |
| 3146 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 3147 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3148 | |
| 3149 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 3150 | * perspective. |
| 3151 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3152 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 3153 | i++) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3154 | if (obj_priv->page_cpu_valid[i]) |
| 3155 | continue; |
| 3156 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3157 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3158 | |
| 3159 | obj_priv->page_cpu_valid[i] = 1; |
| 3160 | } |
| 3161 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3162 | /* It should now be out of any other write domains, and we can update |
| 3163 | * the domain values for our changes. |
| 3164 | */ |
| 3165 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 3166 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3167 | old_read_domains = obj->read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3168 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 3169 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3170 | trace_i915_gem_object_change_domain(obj, |
| 3171 | old_read_domains, |
| 3172 | obj->write_domain); |
| 3173 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3174 | return 0; |
| 3175 | } |
| 3176 | |
| 3177 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3178 | * Pin an object to the GTT and evaluate the relocations landing in it. |
| 3179 | */ |
| 3180 | static int |
| 3181 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, |
| 3182 | struct drm_file *file_priv, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3183 | struct drm_i915_gem_exec_object *entry, |
| 3184 | struct drm_i915_gem_relocation_entry *relocs) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3185 | { |
| 3186 | struct drm_device *dev = obj->dev; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3187 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3188 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 3189 | int i, ret; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3190 | void __iomem *reloc_page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3191 | |
| 3192 | /* Choose the GTT offset for our buffer and put it there. */ |
| 3193 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); |
| 3194 | if (ret) |
| 3195 | return ret; |
| 3196 | |
| 3197 | entry->offset = obj_priv->gtt_offset; |
| 3198 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3199 | /* Apply the relocations, using the GTT aperture to avoid cache |
| 3200 | * flushing requirements. |
| 3201 | */ |
| 3202 | for (i = 0; i < entry->relocation_count; i++) { |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3203 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3204 | struct drm_gem_object *target_obj; |
| 3205 | struct drm_i915_gem_object *target_obj_priv; |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 3206 | uint32_t reloc_val, reloc_offset; |
| 3207 | uint32_t __iomem *reloc_entry; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3208 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3209 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3210 | reloc->target_handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3211 | if (target_obj == NULL) { |
| 3212 | i915_gem_object_unpin(obj); |
| 3213 | return -EBADF; |
| 3214 | } |
| 3215 | target_obj_priv = target_obj->driver_private; |
| 3216 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3217 | #if WATCH_RELOC |
| 3218 | DRM_INFO("%s: obj %p offset %08x target %d " |
| 3219 | "read %08x write %08x gtt %08x " |
| 3220 | "presumed %08x delta %08x\n", |
| 3221 | __func__, |
| 3222 | obj, |
| 3223 | (int) reloc->offset, |
| 3224 | (int) reloc->target_handle, |
| 3225 | (int) reloc->read_domains, |
| 3226 | (int) reloc->write_domain, |
| 3227 | (int) target_obj_priv->gtt_offset, |
| 3228 | (int) reloc->presumed_offset, |
| 3229 | reloc->delta); |
| 3230 | #endif |
| 3231 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3232 | /* The target buffer should have appeared before us in the |
| 3233 | * exec_object list, so it should have a GTT space bound by now. |
| 3234 | */ |
| 3235 | if (target_obj_priv->gtt_space == NULL) { |
| 3236 | DRM_ERROR("No GTT space found for object %d\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3237 | reloc->target_handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3238 | drm_gem_object_unreference(target_obj); |
| 3239 | i915_gem_object_unpin(obj); |
| 3240 | return -EINVAL; |
| 3241 | } |
| 3242 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3243 | /* Validate that the target is in a valid r/w GPU domain */ |
| 3244 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
| 3245 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3246 | DRM_ERROR("reloc with read/write CPU domains: " |
| 3247 | "obj %p target %d offset %d " |
| 3248 | "read %08x write %08x", |
| 3249 | obj, reloc->target_handle, |
| 3250 | (int) reloc->offset, |
| 3251 | reloc->read_domains, |
| 3252 | reloc->write_domain); |
| 3253 | drm_gem_object_unreference(target_obj); |
| 3254 | i915_gem_object_unpin(obj); |
| 3255 | return -EINVAL; |
| 3256 | } |
| 3257 | if (reloc->write_domain && target_obj->pending_write_domain && |
| 3258 | reloc->write_domain != target_obj->pending_write_domain) { |
| 3259 | DRM_ERROR("Write domain conflict: " |
| 3260 | "obj %p target %d offset %d " |
| 3261 | "new %08x old %08x\n", |
| 3262 | obj, reloc->target_handle, |
| 3263 | (int) reloc->offset, |
| 3264 | reloc->write_domain, |
| 3265 | target_obj->pending_write_domain); |
| 3266 | drm_gem_object_unreference(target_obj); |
| 3267 | i915_gem_object_unpin(obj); |
| 3268 | return -EINVAL; |
| 3269 | } |
| 3270 | |
| 3271 | target_obj->pending_read_domains |= reloc->read_domains; |
| 3272 | target_obj->pending_write_domain |= reloc->write_domain; |
| 3273 | |
| 3274 | /* If the relocation already has the right value in it, no |
| 3275 | * more work needs to be done. |
| 3276 | */ |
| 3277 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
| 3278 | drm_gem_object_unreference(target_obj); |
| 3279 | continue; |
| 3280 | } |
| 3281 | |
| 3282 | /* Check that the relocation address is valid... */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3283 | if (reloc->offset > obj->size - 4) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3284 | DRM_ERROR("Relocation beyond object bounds: " |
| 3285 | "obj %p target %d offset %d size %d.\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3286 | obj, reloc->target_handle, |
| 3287 | (int) reloc->offset, (int) obj->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3288 | drm_gem_object_unreference(target_obj); |
| 3289 | i915_gem_object_unpin(obj); |
| 3290 | return -EINVAL; |
| 3291 | } |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3292 | if (reloc->offset & 3) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3293 | DRM_ERROR("Relocation not 4-byte aligned: " |
| 3294 | "obj %p target %d offset %d.\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3295 | obj, reloc->target_handle, |
| 3296 | (int) reloc->offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3297 | drm_gem_object_unreference(target_obj); |
| 3298 | i915_gem_object_unpin(obj); |
| 3299 | return -EINVAL; |
| 3300 | } |
| 3301 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3302 | /* and points to somewhere within the target object. */ |
Chris Wilson | cd0b9fb | 2009-09-15 23:23:18 +0100 | [diff] [blame] | 3303 | if (reloc->delta >= target_obj->size) { |
| 3304 | DRM_ERROR("Relocation beyond target object bounds: " |
| 3305 | "obj %p target %d delta %d size %d.\n", |
| 3306 | obj, reloc->target_handle, |
| 3307 | (int) reloc->delta, (int) target_obj->size); |
| 3308 | drm_gem_object_unreference(target_obj); |
| 3309 | i915_gem_object_unpin(obj); |
| 3310 | return -EINVAL; |
| 3311 | } |
| 3312 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3313 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 3314 | if (ret != 0) { |
| 3315 | drm_gem_object_unreference(target_obj); |
| 3316 | i915_gem_object_unpin(obj); |
| 3317 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3318 | } |
| 3319 | |
| 3320 | /* Map the page containing the relocation we're going to |
| 3321 | * perform. |
| 3322 | */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3323 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3324 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
| 3325 | (reloc_offset & |
| 3326 | ~(PAGE_SIZE - 1))); |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 3327 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3328 | (reloc_offset & (PAGE_SIZE - 1))); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3329 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3330 | |
| 3331 | #if WATCH_BUF |
| 3332 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3333 | obj, (unsigned int) reloc->offset, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3334 | readl(reloc_entry), reloc_val); |
| 3335 | #endif |
| 3336 | writel(reloc_val, reloc_entry); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3337 | io_mapping_unmap_atomic(reloc_page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3338 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3339 | /* The updated presumed offset for this entry will be |
| 3340 | * copied back out to the user. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3341 | */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3342 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3343 | |
| 3344 | drm_gem_object_unreference(target_obj); |
| 3345 | } |
| 3346 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3347 | #if WATCH_BUF |
| 3348 | if (0) |
| 3349 | i915_gem_dump_object(obj, 128, __func__, ~0); |
| 3350 | #endif |
| 3351 | return 0; |
| 3352 | } |
| 3353 | |
| 3354 | /** Dispatch a batchbuffer to the ring |
| 3355 | */ |
| 3356 | static int |
| 3357 | i915_dispatch_gem_execbuffer(struct drm_device *dev, |
| 3358 | struct drm_i915_gem_execbuffer *exec, |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3359 | struct drm_clip_rect *cliprects, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3360 | uint64_t exec_offset) |
| 3361 | { |
| 3362 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3363 | int nbox = exec->num_cliprects; |
| 3364 | int i = 0, count; |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3365 | uint32_t exec_start, exec_len; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3366 | RING_LOCALS; |
| 3367 | |
| 3368 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3369 | exec_len = (uint32_t) exec->batch_len; |
| 3370 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3371 | trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno); |
| 3372 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3373 | count = nbox ? nbox : 1; |
| 3374 | |
| 3375 | for (i = 0; i < count; i++) { |
| 3376 | if (i < nbox) { |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3377 | int ret = i915_emit_box(dev, cliprects, i, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3378 | exec->DR1, exec->DR4); |
| 3379 | if (ret) |
| 3380 | return ret; |
| 3381 | } |
| 3382 | |
| 3383 | if (IS_I830(dev) || IS_845G(dev)) { |
| 3384 | BEGIN_LP_RING(4); |
| 3385 | OUT_RING(MI_BATCH_BUFFER); |
| 3386 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); |
| 3387 | OUT_RING(exec_start + exec_len - 4); |
| 3388 | OUT_RING(0); |
| 3389 | ADVANCE_LP_RING(); |
| 3390 | } else { |
| 3391 | BEGIN_LP_RING(2); |
| 3392 | if (IS_I965G(dev)) { |
| 3393 | OUT_RING(MI_BATCH_BUFFER_START | |
| 3394 | (2 << 6) | |
| 3395 | MI_BATCH_NON_SECURE_I965); |
| 3396 | OUT_RING(exec_start); |
| 3397 | } else { |
| 3398 | OUT_RING(MI_BATCH_BUFFER_START | |
| 3399 | (2 << 6)); |
| 3400 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); |
| 3401 | } |
| 3402 | ADVANCE_LP_RING(); |
| 3403 | } |
| 3404 | } |
| 3405 | |
| 3406 | /* XXX breadcrumb */ |
| 3407 | return 0; |
| 3408 | } |
| 3409 | |
| 3410 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3411 | * emitted over 20 msec ago. |
| 3412 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3413 | * Note that if we were to use the current jiffies each time around the loop, |
| 3414 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3415 | * render a frame was over 20ms. |
| 3416 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3417 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3418 | * relatively low latency when blocking on a particular request to finish. |
| 3419 | */ |
| 3420 | static int |
| 3421 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) |
| 3422 | { |
| 3423 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; |
| 3424 | int ret = 0; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3425 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3426 | |
| 3427 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3428 | while (!list_empty(&i915_file_priv->mm.request_list)) { |
| 3429 | struct drm_i915_gem_request *request; |
| 3430 | |
| 3431 | request = list_first_entry(&i915_file_priv->mm.request_list, |
| 3432 | struct drm_i915_gem_request, |
| 3433 | client_list); |
| 3434 | |
| 3435 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3436 | break; |
| 3437 | |
| 3438 | ret = i915_wait_request(dev, request->seqno); |
| 3439 | if (ret != 0) |
| 3440 | break; |
| 3441 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3442 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3443 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3444 | return ret; |
| 3445 | } |
| 3446 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3447 | static int |
| 3448 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list, |
| 3449 | uint32_t buffer_count, |
| 3450 | struct drm_i915_gem_relocation_entry **relocs) |
| 3451 | { |
| 3452 | uint32_t reloc_count = 0, reloc_index = 0, i; |
| 3453 | int ret; |
| 3454 | |
| 3455 | *relocs = NULL; |
| 3456 | for (i = 0; i < buffer_count; i++) { |
| 3457 | if (reloc_count + exec_list[i].relocation_count < reloc_count) |
| 3458 | return -EINVAL; |
| 3459 | reloc_count += exec_list[i].relocation_count; |
| 3460 | } |
| 3461 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3462 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3463 | if (*relocs == NULL) |
| 3464 | return -ENOMEM; |
| 3465 | |
| 3466 | for (i = 0; i < buffer_count; i++) { |
| 3467 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
| 3468 | |
| 3469 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; |
| 3470 | |
| 3471 | ret = copy_from_user(&(*relocs)[reloc_index], |
| 3472 | user_relocs, |
| 3473 | exec_list[i].relocation_count * |
| 3474 | sizeof(**relocs)); |
| 3475 | if (ret != 0) { |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3476 | drm_free_large(*relocs); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3477 | *relocs = NULL; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3478 | return -EFAULT; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3479 | } |
| 3480 | |
| 3481 | reloc_index += exec_list[i].relocation_count; |
| 3482 | } |
| 3483 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3484 | return 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3485 | } |
| 3486 | |
| 3487 | static int |
| 3488 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list, |
| 3489 | uint32_t buffer_count, |
| 3490 | struct drm_i915_gem_relocation_entry *relocs) |
| 3491 | { |
| 3492 | uint32_t reloc_count = 0, i; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3493 | int ret = 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3494 | |
| 3495 | for (i = 0; i < buffer_count; i++) { |
| 3496 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3497 | int unwritten; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3498 | |
| 3499 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; |
| 3500 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3501 | unwritten = copy_to_user(user_relocs, |
| 3502 | &relocs[reloc_count], |
| 3503 | exec_list[i].relocation_count * |
| 3504 | sizeof(*relocs)); |
| 3505 | |
| 3506 | if (unwritten) { |
| 3507 | ret = -EFAULT; |
| 3508 | goto err; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3509 | } |
| 3510 | |
| 3511 | reloc_count += exec_list[i].relocation_count; |
| 3512 | } |
| 3513 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3514 | err: |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3515 | drm_free_large(relocs); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3516 | |
| 3517 | return ret; |
| 3518 | } |
| 3519 | |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3520 | static int |
| 3521 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec, |
| 3522 | uint64_t exec_offset) |
| 3523 | { |
| 3524 | uint32_t exec_start, exec_len; |
| 3525 | |
| 3526 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3527 | exec_len = (uint32_t) exec->batch_len; |
| 3528 | |
| 3529 | if ((exec_start | exec_len) & 0x7) |
| 3530 | return -EINVAL; |
| 3531 | |
| 3532 | if (!exec_start) |
| 3533 | return -EINVAL; |
| 3534 | |
| 3535 | return 0; |
| 3536 | } |
| 3537 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3538 | int |
| 3539 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 3540 | struct drm_file *file_priv) |
| 3541 | { |
| 3542 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3543 | struct drm_i915_gem_execbuffer *args = data; |
| 3544 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 3545 | struct drm_gem_object **object_list = NULL; |
| 3546 | struct drm_gem_object *batch_obj; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3547 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3548 | struct drm_clip_rect *cliprects = NULL; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3549 | struct drm_i915_gem_relocation_entry *relocs; |
| 3550 | int ret, ret2, i, pinned = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3551 | uint64_t exec_offset; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3552 | uint32_t seqno, flush_domains, reloc_index; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3553 | int pin_tries; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3554 | |
| 3555 | #if WATCH_EXEC |
| 3556 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3557 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3558 | #endif |
| 3559 | |
Eric Anholt | 4f481ed | 2008-09-10 14:22:49 -0700 | [diff] [blame] | 3560 | if (args->buffer_count < 1) { |
| 3561 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3562 | return -EINVAL; |
| 3563 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3564 | /* Copy in the exec list from userland */ |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3565 | exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count); |
| 3566 | object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3567 | if (exec_list == NULL || object_list == NULL) { |
| 3568 | DRM_ERROR("Failed to allocate exec or object list " |
| 3569 | "for %d buffers\n", |
| 3570 | args->buffer_count); |
| 3571 | ret = -ENOMEM; |
| 3572 | goto pre_mutex_err; |
| 3573 | } |
| 3574 | ret = copy_from_user(exec_list, |
| 3575 | (struct drm_i915_relocation_entry __user *) |
| 3576 | (uintptr_t) args->buffers_ptr, |
| 3577 | sizeof(*exec_list) * args->buffer_count); |
| 3578 | if (ret != 0) { |
| 3579 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 3580 | args->buffer_count, ret); |
| 3581 | goto pre_mutex_err; |
| 3582 | } |
| 3583 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3584 | if (args->num_cliprects != 0) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3585 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
| 3586 | GFP_KERNEL); |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3587 | if (cliprects == NULL) |
| 3588 | goto pre_mutex_err; |
| 3589 | |
| 3590 | ret = copy_from_user(cliprects, |
| 3591 | (struct drm_clip_rect __user *) |
| 3592 | (uintptr_t) args->cliprects_ptr, |
| 3593 | sizeof(*cliprects) * args->num_cliprects); |
| 3594 | if (ret != 0) { |
| 3595 | DRM_ERROR("copy %d cliprects failed: %d\n", |
| 3596 | args->num_cliprects, ret); |
| 3597 | goto pre_mutex_err; |
| 3598 | } |
| 3599 | } |
| 3600 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3601 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
| 3602 | &relocs); |
| 3603 | if (ret != 0) |
| 3604 | goto pre_mutex_err; |
| 3605 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3606 | mutex_lock(&dev->struct_mutex); |
| 3607 | |
| 3608 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3609 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3610 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3611 | DRM_ERROR("Execbuf while wedged\n"); |
| 3612 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3613 | ret = -EIO; |
| 3614 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3615 | } |
| 3616 | |
| 3617 | if (dev_priv->mm.suspended) { |
| 3618 | DRM_ERROR("Execbuf while VT-switched.\n"); |
| 3619 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3620 | ret = -EBUSY; |
| 3621 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3622 | } |
| 3623 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3624 | /* Look up object handles */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3625 | for (i = 0; i < args->buffer_count; i++) { |
| 3626 | object_list[i] = drm_gem_object_lookup(dev, file_priv, |
| 3627 | exec_list[i].handle); |
| 3628 | if (object_list[i] == NULL) { |
| 3629 | DRM_ERROR("Invalid object handle %d at index %d\n", |
| 3630 | exec_list[i].handle, i); |
| 3631 | ret = -EBADF; |
| 3632 | goto err; |
| 3633 | } |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3634 | |
| 3635 | obj_priv = object_list[i]->driver_private; |
| 3636 | if (obj_priv->in_execbuffer) { |
| 3637 | DRM_ERROR("Object %p appears more than once in object list\n", |
| 3638 | object_list[i]); |
| 3639 | ret = -EBADF; |
| 3640 | goto err; |
| 3641 | } |
| 3642 | obj_priv->in_execbuffer = true; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3643 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3644 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3645 | /* Pin and relocate */ |
| 3646 | for (pin_tries = 0; ; pin_tries++) { |
| 3647 | ret = 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3648 | reloc_index = 0; |
| 3649 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3650 | for (i = 0; i < args->buffer_count; i++) { |
| 3651 | object_list[i]->pending_read_domains = 0; |
| 3652 | object_list[i]->pending_write_domain = 0; |
| 3653 | ret = i915_gem_object_pin_and_relocate(object_list[i], |
| 3654 | file_priv, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3655 | &exec_list[i], |
| 3656 | &relocs[reloc_index]); |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3657 | if (ret) |
| 3658 | break; |
| 3659 | pinned = i + 1; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3660 | reloc_index += exec_list[i].relocation_count; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3661 | } |
| 3662 | /* success */ |
| 3663 | if (ret == 0) |
| 3664 | break; |
| 3665 | |
| 3666 | /* error other than GTT full, or we've already tried again */ |
Chris Wilson | 2939e1f | 2009-06-06 09:46:03 +0100 | [diff] [blame] | 3667 | if (ret != -ENOSPC || pin_tries >= 1) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3668 | if (ret != -ERESTARTSYS) { |
| 3669 | unsigned long long total_size = 0; |
| 3670 | for (i = 0; i < args->buffer_count; i++) |
| 3671 | total_size += object_list[i]->size; |
| 3672 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n", |
| 3673 | pinned+1, args->buffer_count, |
| 3674 | total_size, ret); |
| 3675 | DRM_ERROR("%d objects [%d pinned], " |
| 3676 | "%d object bytes [%d pinned], " |
| 3677 | "%d/%d gtt bytes\n", |
| 3678 | atomic_read(&dev->object_count), |
| 3679 | atomic_read(&dev->pin_count), |
| 3680 | atomic_read(&dev->object_memory), |
| 3681 | atomic_read(&dev->pin_memory), |
| 3682 | atomic_read(&dev->gtt_memory), |
| 3683 | dev->gtt_total); |
| 3684 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3685 | goto err; |
| 3686 | } |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3687 | |
| 3688 | /* unpin all of our buffers */ |
| 3689 | for (i = 0; i < pinned; i++) |
| 3690 | i915_gem_object_unpin(object_list[i]); |
Eric Anholt | b117763 | 2008-12-10 10:09:41 -0800 | [diff] [blame] | 3691 | pinned = 0; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3692 | |
| 3693 | /* evict everyone we can from the aperture */ |
| 3694 | ret = i915_gem_evict_everything(dev); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3695 | if (ret && ret != -ENOSPC) |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3696 | goto err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3697 | } |
| 3698 | |
| 3699 | /* Set the pending read domains for the batch buffer to COMMAND */ |
| 3700 | batch_obj = object_list[args->buffer_count-1]; |
Chris Wilson | 5f26a2c | 2009-06-06 09:45:58 +0100 | [diff] [blame] | 3701 | if (batch_obj->pending_write_domain) { |
| 3702 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); |
| 3703 | ret = -EINVAL; |
| 3704 | goto err; |
| 3705 | } |
| 3706 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3707 | |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3708 | /* Sanity check the batch buffer, prior to moving objects */ |
| 3709 | exec_offset = exec_list[args->buffer_count - 1].offset; |
| 3710 | ret = i915_gem_check_execbuffer (args, exec_offset); |
| 3711 | if (ret != 0) { |
| 3712 | DRM_ERROR("execbuf with invalid offset/length\n"); |
| 3713 | goto err; |
| 3714 | } |
| 3715 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3716 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3717 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3718 | /* Zero the global flush/invalidate flags. These |
| 3719 | * will be modified as new domains are computed |
| 3720 | * for each object |
| 3721 | */ |
| 3722 | dev->invalidate_domains = 0; |
| 3723 | dev->flush_domains = 0; |
| 3724 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3725 | for (i = 0; i < args->buffer_count; i++) { |
| 3726 | struct drm_gem_object *obj = object_list[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3727 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3728 | /* Compute new gpu domains and update invalidate/flush */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3729 | i915_gem_object_set_to_gpu_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3730 | } |
| 3731 | |
| 3732 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3733 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3734 | if (dev->invalidate_domains | dev->flush_domains) { |
| 3735 | #if WATCH_EXEC |
| 3736 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", |
| 3737 | __func__, |
| 3738 | dev->invalidate_domains, |
| 3739 | dev->flush_domains); |
| 3740 | #endif |
| 3741 | i915_gem_flush(dev, |
| 3742 | dev->invalidate_domains, |
| 3743 | dev->flush_domains); |
| 3744 | if (dev->flush_domains) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3745 | (void)i915_add_request(dev, file_priv, |
| 3746 | dev->flush_domains); |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3747 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3748 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3749 | for (i = 0; i < args->buffer_count; i++) { |
| 3750 | struct drm_gem_object *obj = object_list[i]; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3751 | uint32_t old_write_domain = obj->write_domain; |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3752 | |
| 3753 | obj->write_domain = obj->pending_write_domain; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3754 | trace_i915_gem_object_change_domain(obj, |
| 3755 | obj->read_domains, |
| 3756 | old_write_domain); |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3757 | } |
| 3758 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3759 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3760 | |
| 3761 | #if WATCH_COHERENCY |
| 3762 | for (i = 0; i < args->buffer_count; i++) { |
| 3763 | i915_gem_object_check_coherency(object_list[i], |
| 3764 | exec_list[i].handle); |
| 3765 | } |
| 3766 | #endif |
| 3767 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3768 | #if WATCH_EXEC |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 3769 | i915_gem_dump_object(batch_obj, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3770 | args->batch_len, |
| 3771 | __func__, |
| 3772 | ~0); |
| 3773 | #endif |
| 3774 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3775 | /* Exec the batchbuffer */ |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3776 | ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3777 | if (ret) { |
| 3778 | DRM_ERROR("dispatch failed %d\n", ret); |
| 3779 | goto err; |
| 3780 | } |
| 3781 | |
| 3782 | /* |
| 3783 | * Ensure that the commands in the batch buffer are |
| 3784 | * finished before the interrupt fires |
| 3785 | */ |
| 3786 | flush_domains = i915_retire_commands(dev); |
| 3787 | |
| 3788 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3789 | |
| 3790 | /* |
| 3791 | * Get a seqno representing the execution of the current buffer, |
| 3792 | * which we can wait on. We would like to mitigate these interrupts, |
| 3793 | * likely by only creating seqnos occasionally (so that we have |
| 3794 | * *some* interrupts representing completion of buffers that we can |
| 3795 | * wait on when trying to clear up gtt space). |
| 3796 | */ |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3797 | seqno = i915_add_request(dev, file_priv, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3798 | BUG_ON(seqno == 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3799 | for (i = 0; i < args->buffer_count; i++) { |
| 3800 | struct drm_gem_object *obj = object_list[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3801 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 3802 | i915_gem_object_move_to_active(obj, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3803 | #if WATCH_LRU |
| 3804 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); |
| 3805 | #endif |
| 3806 | } |
| 3807 | #if WATCH_LRU |
| 3808 | i915_dump_lru(dev, __func__); |
| 3809 | #endif |
| 3810 | |
| 3811 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3812 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3813 | err: |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3814 | for (i = 0; i < pinned; i++) |
| 3815 | i915_gem_object_unpin(object_list[i]); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3816 | |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3817 | for (i = 0; i < args->buffer_count; i++) { |
| 3818 | if (object_list[i]) { |
| 3819 | obj_priv = object_list[i]->driver_private; |
| 3820 | obj_priv->in_execbuffer = false; |
| 3821 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3822 | drm_gem_object_unreference(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3823 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3824 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3825 | mutex_unlock(&dev->struct_mutex); |
| 3826 | |
Roland Dreier | a35f2e2 | 2009-02-06 17:48:09 -0800 | [diff] [blame] | 3827 | if (!ret) { |
| 3828 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 3829 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 3830 | (uintptr_t) args->buffers_ptr, |
| 3831 | exec_list, |
| 3832 | sizeof(*exec_list) * args->buffer_count); |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3833 | if (ret) { |
| 3834 | ret = -EFAULT; |
Roland Dreier | a35f2e2 | 2009-02-06 17:48:09 -0800 | [diff] [blame] | 3835 | DRM_ERROR("failed to copy %d exec entries " |
| 3836 | "back to user (%d)\n", |
| 3837 | args->buffer_count, ret); |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3838 | } |
Roland Dreier | a35f2e2 | 2009-02-06 17:48:09 -0800 | [diff] [blame] | 3839 | } |
| 3840 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3841 | /* Copy the updated relocations out regardless of current error |
| 3842 | * state. Failure to update the relocs would mean that the next |
| 3843 | * time userland calls execbuf, it would do so with presumed offset |
| 3844 | * state that didn't match the actual object state. |
| 3845 | */ |
| 3846 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, |
| 3847 | relocs); |
| 3848 | if (ret2 != 0) { |
| 3849 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); |
| 3850 | |
| 3851 | if (ret == 0) |
| 3852 | ret = ret2; |
| 3853 | } |
| 3854 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3855 | pre_mutex_err: |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3856 | drm_free_large(object_list); |
| 3857 | drm_free_large(exec_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3858 | kfree(cliprects); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3859 | |
| 3860 | return ret; |
| 3861 | } |
| 3862 | |
| 3863 | int |
| 3864 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) |
| 3865 | { |
| 3866 | struct drm_device *dev = obj->dev; |
| 3867 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 3868 | int ret; |
| 3869 | |
| 3870 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3871 | if (obj_priv->gtt_space == NULL) { |
| 3872 | ret = i915_gem_object_bind_to_gtt(obj, alignment); |
| 3873 | if (ret != 0) { |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 3874 | if (ret != -EBUSY && ret != -ERESTARTSYS) |
Kyle McMartin | 0fce81e | 2009-02-28 15:01:16 -0500 | [diff] [blame] | 3875 | DRM_ERROR("Failure to bind: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3876 | return ret; |
| 3877 | } |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3878 | } |
| 3879 | /* |
| 3880 | * Pre-965 chips need a fence register set up in order to |
| 3881 | * properly handle tiled surfaces. |
| 3882 | */ |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 3883 | if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 3884 | ret = i915_gem_object_get_fence_reg(obj); |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 3885 | if (ret != 0) { |
| 3886 | if (ret != -EBUSY && ret != -ERESTARTSYS) |
| 3887 | DRM_ERROR("Failure to install fence: %d\n", |
| 3888 | ret); |
| 3889 | return ret; |
| 3890 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3891 | } |
| 3892 | obj_priv->pin_count++; |
| 3893 | |
| 3894 | /* If the object is not active and not pending a flush, |
| 3895 | * remove it from the inactive list |
| 3896 | */ |
| 3897 | if (obj_priv->pin_count == 1) { |
| 3898 | atomic_inc(&dev->pin_count); |
| 3899 | atomic_add(obj->size, &dev->pin_memory); |
| 3900 | if (!obj_priv->active && |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 3901 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 && |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3902 | !list_empty(&obj_priv->list)) |
| 3903 | list_del_init(&obj_priv->list); |
| 3904 | } |
| 3905 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3906 | |
| 3907 | return 0; |
| 3908 | } |
| 3909 | |
| 3910 | void |
| 3911 | i915_gem_object_unpin(struct drm_gem_object *obj) |
| 3912 | { |
| 3913 | struct drm_device *dev = obj->dev; |
| 3914 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3915 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 3916 | |
| 3917 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3918 | obj_priv->pin_count--; |
| 3919 | BUG_ON(obj_priv->pin_count < 0); |
| 3920 | BUG_ON(obj_priv->gtt_space == NULL); |
| 3921 | |
| 3922 | /* If the object is no longer pinned, and is |
| 3923 | * neither active nor being flushed, then stick it on |
| 3924 | * the inactive list |
| 3925 | */ |
| 3926 | if (obj_priv->pin_count == 0) { |
| 3927 | if (!obj_priv->active && |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 3928 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3929 | list_move_tail(&obj_priv->list, |
| 3930 | &dev_priv->mm.inactive_list); |
| 3931 | atomic_dec(&dev->pin_count); |
| 3932 | atomic_sub(obj->size, &dev->pin_memory); |
| 3933 | } |
| 3934 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3935 | } |
| 3936 | |
| 3937 | int |
| 3938 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 3939 | struct drm_file *file_priv) |
| 3940 | { |
| 3941 | struct drm_i915_gem_pin *args = data; |
| 3942 | struct drm_gem_object *obj; |
| 3943 | struct drm_i915_gem_object *obj_priv; |
| 3944 | int ret; |
| 3945 | |
| 3946 | mutex_lock(&dev->struct_mutex); |
| 3947 | |
| 3948 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 3949 | if (obj == NULL) { |
| 3950 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", |
| 3951 | args->handle); |
| 3952 | mutex_unlock(&dev->struct_mutex); |
| 3953 | return -EBADF; |
| 3954 | } |
| 3955 | obj_priv = obj->driver_private; |
| 3956 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 3957 | if (obj_priv->madv == I915_MADV_DONTNEED) { |
| 3958 | DRM_ERROR("Attempting to pin a I915_MADV_DONTNEED buffer\n"); |
| 3959 | drm_gem_object_unreference(obj); |
| 3960 | mutex_unlock(&dev->struct_mutex); |
| 3961 | return -EINVAL; |
| 3962 | } |
| 3963 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3964 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
| 3965 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 3966 | args->handle); |
Chris Wilson | 96dec61 | 2009-02-08 19:08:04 +0000 | [diff] [blame] | 3967 | drm_gem_object_unreference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3968 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3969 | return -EINVAL; |
| 3970 | } |
| 3971 | |
| 3972 | obj_priv->user_pin_count++; |
| 3973 | obj_priv->pin_filp = file_priv; |
| 3974 | if (obj_priv->user_pin_count == 1) { |
| 3975 | ret = i915_gem_object_pin(obj, args->alignment); |
| 3976 | if (ret != 0) { |
| 3977 | drm_gem_object_unreference(obj); |
| 3978 | mutex_unlock(&dev->struct_mutex); |
| 3979 | return ret; |
| 3980 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3981 | } |
| 3982 | |
| 3983 | /* XXX - flush the CPU caches for pinned objects |
| 3984 | * as the X server doesn't manage domains yet |
| 3985 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3986 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3987 | args->offset = obj_priv->gtt_offset; |
| 3988 | drm_gem_object_unreference(obj); |
| 3989 | mutex_unlock(&dev->struct_mutex); |
| 3990 | |
| 3991 | return 0; |
| 3992 | } |
| 3993 | |
| 3994 | int |
| 3995 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 3996 | struct drm_file *file_priv) |
| 3997 | { |
| 3998 | struct drm_i915_gem_pin *args = data; |
| 3999 | struct drm_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4000 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4001 | |
| 4002 | mutex_lock(&dev->struct_mutex); |
| 4003 | |
| 4004 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4005 | if (obj == NULL) { |
| 4006 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", |
| 4007 | args->handle); |
| 4008 | mutex_unlock(&dev->struct_mutex); |
| 4009 | return -EBADF; |
| 4010 | } |
| 4011 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4012 | obj_priv = obj->driver_private; |
| 4013 | if (obj_priv->pin_filp != file_priv) { |
| 4014 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 4015 | args->handle); |
| 4016 | drm_gem_object_unreference(obj); |
| 4017 | mutex_unlock(&dev->struct_mutex); |
| 4018 | return -EINVAL; |
| 4019 | } |
| 4020 | obj_priv->user_pin_count--; |
| 4021 | if (obj_priv->user_pin_count == 0) { |
| 4022 | obj_priv->pin_filp = NULL; |
| 4023 | i915_gem_object_unpin(obj); |
| 4024 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4025 | |
| 4026 | drm_gem_object_unreference(obj); |
| 4027 | mutex_unlock(&dev->struct_mutex); |
| 4028 | return 0; |
| 4029 | } |
| 4030 | |
| 4031 | int |
| 4032 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 4033 | struct drm_file *file_priv) |
| 4034 | { |
| 4035 | struct drm_i915_gem_busy *args = data; |
| 4036 | struct drm_gem_object *obj; |
| 4037 | struct drm_i915_gem_object *obj_priv; |
| 4038 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4039 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4040 | if (obj == NULL) { |
| 4041 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", |
| 4042 | args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4043 | return -EBADF; |
| 4044 | } |
| 4045 | |
Chris Wilson | b1ce786 | 2009-06-06 09:46:00 +0100 | [diff] [blame] | 4046 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | f21289b | 2009-02-18 09:44:56 -0800 | [diff] [blame] | 4047 | /* Update the active list for the hardware's current position. |
| 4048 | * Otherwise this only updates on a delayed timer or when irqs are |
| 4049 | * actually unmasked, and our working set ends up being larger than |
| 4050 | * required. |
| 4051 | */ |
| 4052 | i915_gem_retire_requests(dev); |
| 4053 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4054 | obj_priv = obj->driver_private; |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4055 | /* Don't count being on the flushing list against the object being |
| 4056 | * done. Otherwise, a buffer left on the flushing list but not getting |
| 4057 | * flushed (because nobody's flushing that domain) won't ever return |
| 4058 | * unbusy and get reused by libdrm's bo cache. The other expected |
| 4059 | * consumer of this interface, OpenGL's occlusion queries, also specs |
| 4060 | * that the objects get unbusy "eventually" without any interference. |
| 4061 | */ |
| 4062 | args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4063 | |
| 4064 | drm_gem_object_unreference(obj); |
| 4065 | mutex_unlock(&dev->struct_mutex); |
| 4066 | return 0; |
| 4067 | } |
| 4068 | |
| 4069 | int |
| 4070 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4071 | struct drm_file *file_priv) |
| 4072 | { |
| 4073 | return i915_gem_ring_throttle(dev, file_priv); |
| 4074 | } |
| 4075 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4076 | int |
| 4077 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4078 | struct drm_file *file_priv) |
| 4079 | { |
| 4080 | struct drm_i915_gem_madvise *args = data; |
| 4081 | struct drm_gem_object *obj; |
| 4082 | struct drm_i915_gem_object *obj_priv; |
| 4083 | |
| 4084 | switch (args->madv) { |
| 4085 | case I915_MADV_DONTNEED: |
| 4086 | case I915_MADV_WILLNEED: |
| 4087 | break; |
| 4088 | default: |
| 4089 | return -EINVAL; |
| 4090 | } |
| 4091 | |
| 4092 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4093 | if (obj == NULL) { |
| 4094 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", |
| 4095 | args->handle); |
| 4096 | return -EBADF; |
| 4097 | } |
| 4098 | |
| 4099 | mutex_lock(&dev->struct_mutex); |
| 4100 | obj_priv = obj->driver_private; |
| 4101 | |
| 4102 | if (obj_priv->pin_count) { |
| 4103 | drm_gem_object_unreference(obj); |
| 4104 | mutex_unlock(&dev->struct_mutex); |
| 4105 | |
| 4106 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); |
| 4107 | return -EINVAL; |
| 4108 | } |
| 4109 | |
| 4110 | obj_priv->madv = args->madv; |
| 4111 | args->retained = obj_priv->gtt_space != NULL; |
| 4112 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame^] | 4113 | /* if the object is no longer bound, discard its backing storage */ |
| 4114 | if (i915_gem_object_is_purgeable(obj_priv) && |
| 4115 | obj_priv->gtt_space == NULL) |
| 4116 | i915_gem_object_truncate(obj); |
| 4117 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4118 | drm_gem_object_unreference(obj); |
| 4119 | mutex_unlock(&dev->struct_mutex); |
| 4120 | |
| 4121 | return 0; |
| 4122 | } |
| 4123 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4124 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 4125 | { |
| 4126 | struct drm_i915_gem_object *obj_priv; |
| 4127 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4128 | obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4129 | if (obj_priv == NULL) |
| 4130 | return -ENOMEM; |
| 4131 | |
| 4132 | /* |
| 4133 | * We've just allocated pages from the kernel, |
| 4134 | * so they've just been written by the CPU with |
| 4135 | * zeros. They'll need to be clflushed before we |
| 4136 | * use them with the GPU. |
| 4137 | */ |
| 4138 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 4139 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
| 4140 | |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 4141 | obj_priv->agp_type = AGP_USER_MEMORY; |
| 4142 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4143 | obj->driver_private = obj_priv; |
| 4144 | obj_priv->obj = obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4145 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4146 | INIT_LIST_HEAD(&obj_priv->list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4147 | INIT_LIST_HEAD(&obj_priv->fence_list); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4148 | obj_priv->madv = I915_MADV_WILLNEED; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4149 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4150 | trace_i915_gem_object_create(obj); |
| 4151 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4152 | return 0; |
| 4153 | } |
| 4154 | |
| 4155 | void i915_gem_free_object(struct drm_gem_object *obj) |
| 4156 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4157 | struct drm_device *dev = obj->dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4158 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 4159 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4160 | trace_i915_gem_object_destroy(obj); |
| 4161 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4162 | while (obj_priv->pin_count > 0) |
| 4163 | i915_gem_object_unpin(obj); |
| 4164 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4165 | if (obj_priv->phys_obj) |
| 4166 | i915_gem_detach_phys_object(dev, obj); |
| 4167 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4168 | i915_gem_object_unbind(obj); |
| 4169 | |
Chris Wilson | 7e61615 | 2009-09-10 08:53:04 +0100 | [diff] [blame] | 4170 | if (obj_priv->mmap_offset) |
| 4171 | i915_gem_free_mmap_offset(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4172 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4173 | kfree(obj_priv->page_cpu_valid); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 4174 | kfree(obj_priv->bit_17); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4175 | kfree(obj->driver_private); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4176 | } |
| 4177 | |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4178 | /** Unbinds all inactive objects. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4179 | static int |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4180 | i915_gem_evict_from_inactive_list(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4181 | { |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4182 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4183 | |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4184 | while (!list_empty(&dev_priv->mm.inactive_list)) { |
| 4185 | struct drm_gem_object *obj; |
| 4186 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4187 | |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4188 | obj = list_first_entry(&dev_priv->mm.inactive_list, |
| 4189 | struct drm_i915_gem_object, |
| 4190 | list)->obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4191 | |
| 4192 | ret = i915_gem_object_unbind(obj); |
| 4193 | if (ret != 0) { |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4194 | DRM_ERROR("Error unbinding object: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4195 | return ret; |
| 4196 | } |
| 4197 | } |
| 4198 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4199 | return 0; |
| 4200 | } |
| 4201 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4202 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4203 | i915_gem_idle(struct drm_device *dev) |
| 4204 | { |
| 4205 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4206 | uint32_t seqno, cur_seqno, last_seqno; |
| 4207 | int stuck, ret; |
| 4208 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4209 | mutex_lock(&dev->struct_mutex); |
| 4210 | |
| 4211 | if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) { |
| 4212 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4213 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4214 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4215 | |
| 4216 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4217 | * We need to replace this with a semaphore, or something. |
| 4218 | */ |
| 4219 | dev_priv->mm.suspended = 1; |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 4220 | del_timer(&dev_priv->hangcheck_timer); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4221 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4222 | /* Cancel the retire work handler, wait for it to finish if running |
| 4223 | */ |
| 4224 | mutex_unlock(&dev->struct_mutex); |
| 4225 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4226 | mutex_lock(&dev->struct_mutex); |
| 4227 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4228 | i915_kernel_lost_context(dev); |
| 4229 | |
| 4230 | /* Flush the GPU along with all non-CPU write domains |
| 4231 | */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 4232 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 4233 | seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4234 | |
| 4235 | if (seqno == 0) { |
| 4236 | mutex_unlock(&dev->struct_mutex); |
| 4237 | return -ENOMEM; |
| 4238 | } |
| 4239 | |
| 4240 | dev_priv->mm.waiting_gem_seqno = seqno; |
| 4241 | last_seqno = 0; |
| 4242 | stuck = 0; |
| 4243 | for (;;) { |
| 4244 | cur_seqno = i915_get_gem_seqno(dev); |
| 4245 | if (i915_seqno_passed(cur_seqno, seqno)) |
| 4246 | break; |
| 4247 | if (last_seqno == cur_seqno) { |
| 4248 | if (stuck++ > 100) { |
| 4249 | DRM_ERROR("hardware wedged\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4250 | atomic_set(&dev_priv->mm.wedged, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4251 | DRM_WAKEUP(&dev_priv->irq_queue); |
| 4252 | break; |
| 4253 | } |
| 4254 | } |
| 4255 | msleep(10); |
| 4256 | last_seqno = cur_seqno; |
| 4257 | } |
| 4258 | dev_priv->mm.waiting_gem_seqno = 0; |
| 4259 | |
| 4260 | i915_gem_retire_requests(dev); |
| 4261 | |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4262 | spin_lock(&dev_priv->mm.active_list_lock); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4263 | if (!atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4264 | /* Active and flushing should now be empty as we've |
| 4265 | * waited for a sequence higher than any pending execbuffer |
| 4266 | */ |
| 4267 | WARN_ON(!list_empty(&dev_priv->mm.active_list)); |
| 4268 | WARN_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 4269 | /* Request should now be empty as we've also waited |
| 4270 | * for the last request in the list |
| 4271 | */ |
| 4272 | WARN_ON(!list_empty(&dev_priv->mm.request_list)); |
| 4273 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4274 | |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4275 | /* Empty the active and flushing lists to inactive. If there's |
| 4276 | * anything left at this point, it means that we're wedged and |
| 4277 | * nothing good's going to happen by leaving them there. So strip |
| 4278 | * the GPU domains and just stuff them onto inactive. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4279 | */ |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4280 | while (!list_empty(&dev_priv->mm.active_list)) { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4281 | struct drm_gem_object *obj; |
| 4282 | uint32_t old_write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4283 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4284 | obj = list_first_entry(&dev_priv->mm.active_list, |
| 4285 | struct drm_i915_gem_object, |
| 4286 | list)->obj; |
| 4287 | old_write_domain = obj->write_domain; |
| 4288 | obj->write_domain &= ~I915_GEM_GPU_DOMAINS; |
| 4289 | i915_gem_object_move_to_inactive(obj); |
| 4290 | |
| 4291 | trace_i915_gem_object_change_domain(obj, |
| 4292 | obj->read_domains, |
| 4293 | old_write_domain); |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4294 | } |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4295 | spin_unlock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4296 | |
| 4297 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4298 | struct drm_gem_object *obj; |
| 4299 | uint32_t old_write_domain; |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4300 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4301 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
| 4302 | struct drm_i915_gem_object, |
| 4303 | list)->obj; |
| 4304 | old_write_domain = obj->write_domain; |
| 4305 | obj->write_domain &= ~I915_GEM_GPU_DOMAINS; |
| 4306 | i915_gem_object_move_to_inactive(obj); |
| 4307 | |
| 4308 | trace_i915_gem_object_change_domain(obj, |
| 4309 | obj->read_domains, |
| 4310 | old_write_domain); |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4311 | } |
| 4312 | |
| 4313 | |
| 4314 | /* Move all inactive buffers out of the GTT. */ |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4315 | ret = i915_gem_evict_from_inactive_list(dev); |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 4316 | WARN_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4317 | if (ret) { |
| 4318 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4319 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4320 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4321 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4322 | i915_gem_cleanup_ringbuffer(dev); |
| 4323 | mutex_unlock(&dev->struct_mutex); |
| 4324 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4325 | return 0; |
| 4326 | } |
| 4327 | |
| 4328 | static int |
| 4329 | i915_gem_init_hws(struct drm_device *dev) |
| 4330 | { |
| 4331 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4332 | struct drm_gem_object *obj; |
| 4333 | struct drm_i915_gem_object *obj_priv; |
| 4334 | int ret; |
| 4335 | |
| 4336 | /* If we need a physical address for the status page, it's already |
| 4337 | * initialized at driver load time. |
| 4338 | */ |
| 4339 | if (!I915_NEED_GFX_HWS(dev)) |
| 4340 | return 0; |
| 4341 | |
| 4342 | obj = drm_gem_object_alloc(dev, 4096); |
| 4343 | if (obj == NULL) { |
| 4344 | DRM_ERROR("Failed to allocate status page\n"); |
| 4345 | return -ENOMEM; |
| 4346 | } |
| 4347 | obj_priv = obj->driver_private; |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 4348 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4349 | |
| 4350 | ret = i915_gem_object_pin(obj, 4096); |
| 4351 | if (ret != 0) { |
| 4352 | drm_gem_object_unreference(obj); |
| 4353 | return ret; |
| 4354 | } |
| 4355 | |
| 4356 | dev_priv->status_gfx_addr = obj_priv->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4357 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4358 | dev_priv->hw_status_page = kmap(obj_priv->pages[0]); |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 4359 | if (dev_priv->hw_status_page == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4360 | DRM_ERROR("Failed to map status page.\n"); |
| 4361 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
Chris Wilson | 3eb2ee7 | 2009-02-11 14:26:34 +0000 | [diff] [blame] | 4362 | i915_gem_object_unpin(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4363 | drm_gem_object_unreference(obj); |
| 4364 | return -EINVAL; |
| 4365 | } |
| 4366 | dev_priv->hws_obj = obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4367 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); |
| 4368 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 4369 | I915_READ(HWS_PGA); /* posting read */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4370 | DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr); |
| 4371 | |
| 4372 | return 0; |
| 4373 | } |
| 4374 | |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4375 | static void |
| 4376 | i915_gem_cleanup_hws(struct drm_device *dev) |
| 4377 | { |
| 4378 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | bab2d1f | 2009-02-20 17:52:20 +0000 | [diff] [blame] | 4379 | struct drm_gem_object *obj; |
| 4380 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4381 | |
| 4382 | if (dev_priv->hws_obj == NULL) |
| 4383 | return; |
| 4384 | |
Chris Wilson | bab2d1f | 2009-02-20 17:52:20 +0000 | [diff] [blame] | 4385 | obj = dev_priv->hws_obj; |
| 4386 | obj_priv = obj->driver_private; |
| 4387 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4388 | kunmap(obj_priv->pages[0]); |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4389 | i915_gem_object_unpin(obj); |
| 4390 | drm_gem_object_unreference(obj); |
| 4391 | dev_priv->hws_obj = NULL; |
Chris Wilson | bab2d1f | 2009-02-20 17:52:20 +0000 | [diff] [blame] | 4392 | |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4393 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
| 4394 | dev_priv->hw_status_page = NULL; |
| 4395 | |
| 4396 | /* Write high address into HWS_PGA when disabling. */ |
| 4397 | I915_WRITE(HWS_PGA, 0x1ffff000); |
| 4398 | } |
| 4399 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4400 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4401 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 4402 | { |
| 4403 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4404 | struct drm_gem_object *obj; |
| 4405 | struct drm_i915_gem_object *obj_priv; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4406 | drm_i915_ring_buffer_t *ring = &dev_priv->ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4407 | int ret; |
Keith Packard | 50aa253 | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 4408 | u32 head; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4409 | |
| 4410 | ret = i915_gem_init_hws(dev); |
| 4411 | if (ret != 0) |
| 4412 | return ret; |
| 4413 | |
| 4414 | obj = drm_gem_object_alloc(dev, 128 * 1024); |
| 4415 | if (obj == NULL) { |
| 4416 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4417 | i915_gem_cleanup_hws(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4418 | return -ENOMEM; |
| 4419 | } |
| 4420 | obj_priv = obj->driver_private; |
| 4421 | |
| 4422 | ret = i915_gem_object_pin(obj, 4096); |
| 4423 | if (ret != 0) { |
| 4424 | drm_gem_object_unreference(obj); |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4425 | i915_gem_cleanup_hws(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4426 | return ret; |
| 4427 | } |
| 4428 | |
| 4429 | /* Set up the kernel mapping for the ring. */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4430 | ring->Size = obj->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4431 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4432 | ring->map.offset = dev->agp->base + obj_priv->gtt_offset; |
| 4433 | ring->map.size = obj->size; |
| 4434 | ring->map.type = 0; |
| 4435 | ring->map.flags = 0; |
| 4436 | ring->map.mtrr = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4437 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4438 | drm_core_ioremap_wc(&ring->map, dev); |
| 4439 | if (ring->map.handle == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4440 | DRM_ERROR("Failed to map ringbuffer.\n"); |
| 4441 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); |
Chris Wilson | 47ed185 | 2009-02-11 14:26:33 +0000 | [diff] [blame] | 4442 | i915_gem_object_unpin(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4443 | drm_gem_object_unreference(obj); |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4444 | i915_gem_cleanup_hws(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4445 | return -EINVAL; |
| 4446 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4447 | ring->ring_obj = obj; |
| 4448 | ring->virtual_start = ring->map.handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4449 | |
| 4450 | /* Stop the ring if it's running. */ |
| 4451 | I915_WRITE(PRB0_CTL, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4452 | I915_WRITE(PRB0_TAIL, 0); |
Keith Packard | 50aa253 | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 4453 | I915_WRITE(PRB0_HEAD, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4454 | |
| 4455 | /* Initialize the ring. */ |
| 4456 | I915_WRITE(PRB0_START, obj_priv->gtt_offset); |
Keith Packard | 50aa253 | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 4457 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
| 4458 | |
| 4459 | /* G45 ring initialization fails to reset head to zero */ |
| 4460 | if (head != 0) { |
| 4461 | DRM_ERROR("Ring head not reset to zero " |
| 4462 | "ctl %08x head %08x tail %08x start %08x\n", |
| 4463 | I915_READ(PRB0_CTL), |
| 4464 | I915_READ(PRB0_HEAD), |
| 4465 | I915_READ(PRB0_TAIL), |
| 4466 | I915_READ(PRB0_START)); |
| 4467 | I915_WRITE(PRB0_HEAD, 0); |
| 4468 | |
| 4469 | DRM_ERROR("Ring head forced to zero " |
| 4470 | "ctl %08x head %08x tail %08x start %08x\n", |
| 4471 | I915_READ(PRB0_CTL), |
| 4472 | I915_READ(PRB0_HEAD), |
| 4473 | I915_READ(PRB0_TAIL), |
| 4474 | I915_READ(PRB0_START)); |
| 4475 | } |
| 4476 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4477 | I915_WRITE(PRB0_CTL, |
| 4478 | ((obj->size - 4096) & RING_NR_PAGES) | |
| 4479 | RING_NO_REPORT | |
| 4480 | RING_VALID); |
| 4481 | |
Keith Packard | 50aa253 | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 4482 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
| 4483 | |
| 4484 | /* If the head is still not zero, the ring is dead */ |
| 4485 | if (head != 0) { |
| 4486 | DRM_ERROR("Ring initialization failed " |
| 4487 | "ctl %08x head %08x tail %08x start %08x\n", |
| 4488 | I915_READ(PRB0_CTL), |
| 4489 | I915_READ(PRB0_HEAD), |
| 4490 | I915_READ(PRB0_TAIL), |
| 4491 | I915_READ(PRB0_START)); |
| 4492 | return -EIO; |
| 4493 | } |
| 4494 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4495 | /* Update our cache of the ring state */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4496 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4497 | i915_kernel_lost_context(dev); |
| 4498 | else { |
| 4499 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
| 4500 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; |
| 4501 | ring->space = ring->head - (ring->tail + 8); |
| 4502 | if (ring->space < 0) |
| 4503 | ring->space += ring->Size; |
| 4504 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4505 | |
| 4506 | return 0; |
| 4507 | } |
| 4508 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4509 | void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4510 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4511 | { |
| 4512 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4513 | |
| 4514 | if (dev_priv->ring.ring_obj == NULL) |
| 4515 | return; |
| 4516 | |
| 4517 | drm_core_ioremapfree(&dev_priv->ring.map, dev); |
| 4518 | |
| 4519 | i915_gem_object_unpin(dev_priv->ring.ring_obj); |
| 4520 | drm_gem_object_unreference(dev_priv->ring.ring_obj); |
| 4521 | dev_priv->ring.ring_obj = NULL; |
| 4522 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); |
| 4523 | |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4524 | i915_gem_cleanup_hws(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4525 | } |
| 4526 | |
| 4527 | int |
| 4528 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4529 | struct drm_file *file_priv) |
| 4530 | { |
| 4531 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4532 | int ret; |
| 4533 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4534 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4535 | return 0; |
| 4536 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4537 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4538 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4539 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4540 | } |
| 4541 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4542 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4543 | dev_priv->mm.suspended = 0; |
| 4544 | |
| 4545 | ret = i915_gem_init_ringbuffer(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4546 | if (ret != 0) { |
| 4547 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4548 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4549 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4550 | |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4551 | spin_lock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4552 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4553 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 4554 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4555 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 4556 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
| 4557 | BUG_ON(!list_empty(&dev_priv->mm.request_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4558 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4559 | |
| 4560 | drm_irq_install(dev); |
| 4561 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4562 | return 0; |
| 4563 | } |
| 4564 | |
| 4565 | int |
| 4566 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4567 | struct drm_file *file_priv) |
| 4568 | { |
| 4569 | int ret; |
| 4570 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4571 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4572 | return 0; |
| 4573 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4574 | ret = i915_gem_idle(dev); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4575 | drm_irq_uninstall(dev); |
| 4576 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4577 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4578 | } |
| 4579 | |
| 4580 | void |
| 4581 | i915_gem_lastclose(struct drm_device *dev) |
| 4582 | { |
| 4583 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4584 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4585 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4586 | return; |
| 4587 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4588 | ret = i915_gem_idle(dev); |
| 4589 | if (ret) |
| 4590 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4591 | } |
| 4592 | |
| 4593 | void |
| 4594 | i915_gem_load(struct drm_device *dev) |
| 4595 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4596 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4597 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4598 | |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4599 | spin_lock_init(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4600 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
| 4601 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 4602 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
| 4603 | INIT_LIST_HEAD(&dev_priv->mm.request_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4604 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4605 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4606 | i915_gem_retire_work_handler); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4607 | dev_priv->mm.next_gem_seqno = 1; |
| 4608 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4609 | spin_lock(&shrink_list_lock); |
| 4610 | list_add(&dev_priv->mm.shrink_list, &shrink_list); |
| 4611 | spin_unlock(&shrink_list_lock); |
| 4612 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4613 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
| 4614 | dev_priv->fence_reg_start = 3; |
| 4615 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 4616 | if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4617 | dev_priv->num_fence_regs = 16; |
| 4618 | else |
| 4619 | dev_priv->num_fence_regs = 8; |
| 4620 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4621 | /* Initialize fence registers to zero */ |
| 4622 | if (IS_I965G(dev)) { |
| 4623 | for (i = 0; i < 16; i++) |
| 4624 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); |
| 4625 | } else { |
| 4626 | for (i = 0; i < 8; i++) |
| 4627 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); |
| 4628 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 4629 | for (i = 0; i < 8; i++) |
| 4630 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); |
| 4631 | } |
| 4632 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4633 | i915_gem_detect_bit_6_swizzle(dev); |
| 4634 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4635 | |
| 4636 | /* |
| 4637 | * Create a physically contiguous memory object for this object |
| 4638 | * e.g. for cursor + overlay regs |
| 4639 | */ |
| 4640 | int i915_gem_init_phys_object(struct drm_device *dev, |
| 4641 | int id, int size) |
| 4642 | { |
| 4643 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4644 | struct drm_i915_gem_phys_object *phys_obj; |
| 4645 | int ret; |
| 4646 | |
| 4647 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4648 | return 0; |
| 4649 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4650 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4651 | if (!phys_obj) |
| 4652 | return -ENOMEM; |
| 4653 | |
| 4654 | phys_obj->id = id; |
| 4655 | |
| 4656 | phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff); |
| 4657 | if (!phys_obj->handle) { |
| 4658 | ret = -ENOMEM; |
| 4659 | goto kfree_obj; |
| 4660 | } |
| 4661 | #ifdef CONFIG_X86 |
| 4662 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4663 | #endif |
| 4664 | |
| 4665 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4666 | |
| 4667 | return 0; |
| 4668 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4669 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4670 | return ret; |
| 4671 | } |
| 4672 | |
| 4673 | void i915_gem_free_phys_object(struct drm_device *dev, int id) |
| 4674 | { |
| 4675 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4676 | struct drm_i915_gem_phys_object *phys_obj; |
| 4677 | |
| 4678 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4679 | return; |
| 4680 | |
| 4681 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4682 | if (phys_obj->cur_obj) { |
| 4683 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4684 | } |
| 4685 | |
| 4686 | #ifdef CONFIG_X86 |
| 4687 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4688 | #endif |
| 4689 | drm_pci_free(dev, phys_obj->handle); |
| 4690 | kfree(phys_obj); |
| 4691 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4692 | } |
| 4693 | |
| 4694 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4695 | { |
| 4696 | int i; |
| 4697 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4698 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4699 | i915_gem_free_phys_object(dev, i); |
| 4700 | } |
| 4701 | |
| 4702 | void i915_gem_detach_phys_object(struct drm_device *dev, |
| 4703 | struct drm_gem_object *obj) |
| 4704 | { |
| 4705 | struct drm_i915_gem_object *obj_priv; |
| 4706 | int i; |
| 4707 | int ret; |
| 4708 | int page_count; |
| 4709 | |
| 4710 | obj_priv = obj->driver_private; |
| 4711 | if (!obj_priv->phys_obj) |
| 4712 | return; |
| 4713 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4714 | ret = i915_gem_object_get_pages(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4715 | if (ret) |
| 4716 | goto out; |
| 4717 | |
| 4718 | page_count = obj->size / PAGE_SIZE; |
| 4719 | |
| 4720 | for (i = 0; i < page_count; i++) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4721 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4722 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4723 | |
| 4724 | memcpy(dst, src, PAGE_SIZE); |
| 4725 | kunmap_atomic(dst, KM_USER0); |
| 4726 | } |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4727 | drm_clflush_pages(obj_priv->pages, page_count); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4728 | drm_agp_chipset_flush(dev); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4729 | |
| 4730 | i915_gem_object_put_pages(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4731 | out: |
| 4732 | obj_priv->phys_obj->cur_obj = NULL; |
| 4733 | obj_priv->phys_obj = NULL; |
| 4734 | } |
| 4735 | |
| 4736 | int |
| 4737 | i915_gem_attach_phys_object(struct drm_device *dev, |
| 4738 | struct drm_gem_object *obj, int id) |
| 4739 | { |
| 4740 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4741 | struct drm_i915_gem_object *obj_priv; |
| 4742 | int ret = 0; |
| 4743 | int page_count; |
| 4744 | int i; |
| 4745 | |
| 4746 | if (id > I915_MAX_PHYS_OBJECT) |
| 4747 | return -EINVAL; |
| 4748 | |
| 4749 | obj_priv = obj->driver_private; |
| 4750 | |
| 4751 | if (obj_priv->phys_obj) { |
| 4752 | if (obj_priv->phys_obj->id == id) |
| 4753 | return 0; |
| 4754 | i915_gem_detach_phys_object(dev, obj); |
| 4755 | } |
| 4756 | |
| 4757 | |
| 4758 | /* create a new object */ |
| 4759 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4760 | ret = i915_gem_init_phys_object(dev, id, |
| 4761 | obj->size); |
| 4762 | if (ret) { |
Linus Torvalds | aeb565d | 2009-01-26 10:01:53 -0800 | [diff] [blame] | 4763 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4764 | goto out; |
| 4765 | } |
| 4766 | } |
| 4767 | |
| 4768 | /* bind to the object */ |
| 4769 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4770 | obj_priv->phys_obj->cur_obj = obj; |
| 4771 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4772 | ret = i915_gem_object_get_pages(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4773 | if (ret) { |
| 4774 | DRM_ERROR("failed to get page list\n"); |
| 4775 | goto out; |
| 4776 | } |
| 4777 | |
| 4778 | page_count = obj->size / PAGE_SIZE; |
| 4779 | |
| 4780 | for (i = 0; i < page_count; i++) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4781 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4782 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4783 | |
| 4784 | memcpy(dst, src, PAGE_SIZE); |
| 4785 | kunmap_atomic(src, KM_USER0); |
| 4786 | } |
| 4787 | |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4788 | i915_gem_object_put_pages(obj); |
| 4789 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4790 | return 0; |
| 4791 | out: |
| 4792 | return ret; |
| 4793 | } |
| 4794 | |
| 4795 | static int |
| 4796 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 4797 | struct drm_i915_gem_pwrite *args, |
| 4798 | struct drm_file *file_priv) |
| 4799 | { |
| 4800 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 4801 | void *obj_addr; |
| 4802 | int ret; |
| 4803 | char __user *user_data; |
| 4804 | |
| 4805 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 4806 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; |
| 4807 | |
Dave Airlie | e08fb4f | 2009-02-25 14:52:30 +1000 | [diff] [blame] | 4808 | DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4809 | ret = copy_from_user(obj_addr, user_data, args->size); |
| 4810 | if (ret) |
| 4811 | return -EFAULT; |
| 4812 | |
| 4813 | drm_agp_chipset_flush(dev); |
| 4814 | return 0; |
| 4815 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4816 | |
| 4817 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv) |
| 4818 | { |
| 4819 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; |
| 4820 | |
| 4821 | /* Clean up our request list when the client is going away, so that |
| 4822 | * later retire_requests won't dereference our soon-to-be-gone |
| 4823 | * file_priv. |
| 4824 | */ |
| 4825 | mutex_lock(&dev->struct_mutex); |
| 4826 | while (!list_empty(&i915_file_priv->mm.request_list)) |
| 4827 | list_del_init(i915_file_priv->mm.request_list.next); |
| 4828 | mutex_unlock(&dev->struct_mutex); |
| 4829 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4830 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4831 | static int |
| 4832 | i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask) |
| 4833 | { |
| 4834 | drm_i915_private_t *dev_priv, *next_dev; |
| 4835 | struct drm_i915_gem_object *obj_priv, *next_obj; |
| 4836 | int cnt = 0; |
| 4837 | int would_deadlock = 1; |
| 4838 | |
| 4839 | /* "fast-path" to count number of available objects */ |
| 4840 | if (nr_to_scan == 0) { |
| 4841 | spin_lock(&shrink_list_lock); |
| 4842 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 4843 | struct drm_device *dev = dev_priv->dev; |
| 4844 | |
| 4845 | if (mutex_trylock(&dev->struct_mutex)) { |
| 4846 | list_for_each_entry(obj_priv, |
| 4847 | &dev_priv->mm.inactive_list, |
| 4848 | list) |
| 4849 | cnt++; |
| 4850 | mutex_unlock(&dev->struct_mutex); |
| 4851 | } |
| 4852 | } |
| 4853 | spin_unlock(&shrink_list_lock); |
| 4854 | |
| 4855 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 4856 | } |
| 4857 | |
| 4858 | spin_lock(&shrink_list_lock); |
| 4859 | |
| 4860 | /* first scan for clean buffers */ |
| 4861 | list_for_each_entry_safe(dev_priv, next_dev, |
| 4862 | &shrink_list, mm.shrink_list) { |
| 4863 | struct drm_device *dev = dev_priv->dev; |
| 4864 | |
| 4865 | if (! mutex_trylock(&dev->struct_mutex)) |
| 4866 | continue; |
| 4867 | |
| 4868 | spin_unlock(&shrink_list_lock); |
| 4869 | |
| 4870 | i915_gem_retire_requests(dev); |
| 4871 | |
| 4872 | list_for_each_entry_safe(obj_priv, next_obj, |
| 4873 | &dev_priv->mm.inactive_list, |
| 4874 | list) { |
| 4875 | if (i915_gem_object_is_purgeable(obj_priv)) { |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 4876 | i915_gem_object_unbind(obj_priv->obj); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4877 | if (--nr_to_scan <= 0) |
| 4878 | break; |
| 4879 | } |
| 4880 | } |
| 4881 | |
| 4882 | spin_lock(&shrink_list_lock); |
| 4883 | mutex_unlock(&dev->struct_mutex); |
| 4884 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 4885 | would_deadlock = 0; |
| 4886 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4887 | if (nr_to_scan <= 0) |
| 4888 | break; |
| 4889 | } |
| 4890 | |
| 4891 | /* second pass, evict/count anything still on the inactive list */ |
| 4892 | list_for_each_entry_safe(dev_priv, next_dev, |
| 4893 | &shrink_list, mm.shrink_list) { |
| 4894 | struct drm_device *dev = dev_priv->dev; |
| 4895 | |
| 4896 | if (! mutex_trylock(&dev->struct_mutex)) |
| 4897 | continue; |
| 4898 | |
| 4899 | spin_unlock(&shrink_list_lock); |
| 4900 | |
| 4901 | list_for_each_entry_safe(obj_priv, next_obj, |
| 4902 | &dev_priv->mm.inactive_list, |
| 4903 | list) { |
| 4904 | if (nr_to_scan > 0) { |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 4905 | i915_gem_object_unbind(obj_priv->obj); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4906 | nr_to_scan--; |
| 4907 | } else |
| 4908 | cnt++; |
| 4909 | } |
| 4910 | |
| 4911 | spin_lock(&shrink_list_lock); |
| 4912 | mutex_unlock(&dev->struct_mutex); |
| 4913 | |
| 4914 | would_deadlock = 0; |
| 4915 | } |
| 4916 | |
| 4917 | spin_unlock(&shrink_list_lock); |
| 4918 | |
| 4919 | if (would_deadlock) |
| 4920 | return -1; |
| 4921 | else if (cnt > 0) |
| 4922 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 4923 | else |
| 4924 | return 0; |
| 4925 | } |
| 4926 | |
| 4927 | static struct shrinker shrinker = { |
| 4928 | .shrink = i915_gem_shrink, |
| 4929 | .seeks = DEFAULT_SEEKS, |
| 4930 | }; |
| 4931 | |
| 4932 | __init void |
| 4933 | i915_gem_shrinker_init(void) |
| 4934 | { |
| 4935 | register_shrinker(&shrinker); |
| 4936 | } |
| 4937 | |
| 4938 | __exit void |
| 4939 | i915_gem_shrinker_exit(void) |
| 4940 | { |
| 4941 | unregister_shrinker(&shrinker); |
| 4942 | } |