blob: 3b9f4c1f8d4e41a10dacfb45c54be5d391a8df42 [file] [log] [blame]
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001/*
Sujithcee075a2009-03-13 09:07:23 +05302 * Copyright (c) 2008-2009 Atheros Communications Inc.
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
Luis R. Rodriguezaf03abe2009-09-09 02:33:11 -070020#include "hw.h"
Luis R. Rodriguezcfe8cba2009-09-13 23:39:31 -070021#include "rc.h"
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070022#include "initvals.h"
23
Luis R. Rodriguez4febf7b2008-12-23 15:58:48 -080024#define ATH9K_CLOCK_RATE_CCK 22
25#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070027
Sujithcbe61d82009-02-09 13:27:12 +053028static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -070029static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070030
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040031MODULE_AUTHOR("Atheros Communications");
32MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
33MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
34MODULE_LICENSE("Dual BSD/GPL");
35
36static int __init ath9k_init(void)
37{
38 return 0;
39}
40module_init(ath9k_init);
41
42static void __exit ath9k_exit(void)
43{
44 return;
45}
46module_exit(ath9k_exit);
47
Sujithf1dc5602008-10-29 10:16:30 +053048/********************/
49/* Helper Functions */
50/********************/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070051
Sujithcbe61d82009-02-09 13:27:12 +053052static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
Sujithf1dc5602008-10-29 10:16:30 +053053{
Luis R. Rodriguezb002a4a2009-09-13 00:03:27 -070054 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
Sujithcbe61d82009-02-09 13:27:12 +053055
Sujith2660b812009-02-09 13:27:26 +053056 if (!ah->curchan) /* should really check for CCK instead */
Luis R. Rodriguez4febf7b2008-12-23 15:58:48 -080057 return usecs *ATH9K_CLOCK_RATE_CCK;
58 if (conf->channel->band == IEEE80211_BAND_2GHZ)
59 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
60 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
Sujithf1dc5602008-10-29 10:16:30 +053061}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070062
Sujithcbe61d82009-02-09 13:27:12 +053063static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
Sujithf1dc5602008-10-29 10:16:30 +053064{
Luis R. Rodriguezb002a4a2009-09-13 00:03:27 -070065 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
Sujithcbe61d82009-02-09 13:27:12 +053066
Luis R. Rodriguez4febf7b2008-12-23 15:58:48 -080067 if (conf_is_ht40(conf))
Sujithf1dc5602008-10-29 10:16:30 +053068 return ath9k_hw_mac_clks(ah, usecs) * 2;
69 else
70 return ath9k_hw_mac_clks(ah, usecs);
71}
72
Sujith0caa7b12009-02-16 13:23:20 +053073bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070074{
75 int i;
76
Sujith0caa7b12009-02-16 13:23:20 +053077 BUG_ON(timeout < AH_TIME_QUANTUM);
78
79 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070080 if ((REG_READ(ah, reg) & mask) == val)
81 return true;
82
83 udelay(AH_TIME_QUANTUM);
84 }
Sujith04bd4632008-11-28 22:18:05 +053085
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -070086 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
87 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
88 timeout, reg, REG_READ(ah, reg), mask, val);
Sujithf1dc5602008-10-29 10:16:30 +053089
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070090 return false;
91}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040092EXPORT_SYMBOL(ath9k_hw_wait);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070093
Luis R. Rodriguezf078f202008-08-04 00:16:41 -070094u32 ath9k_hw_reverse_bits(u32 val, u32 n)
95{
96 u32 retval;
97 int i;
98
99 for (i = 0, retval = 0; i < n; i++) {
100 retval = (retval << 1) | (val & 1);
101 val >>= 1;
102 }
103 return retval;
104}
105
Sujithcbe61d82009-02-09 13:27:12 +0530106bool ath9k_get_channel_edges(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530107 u16 flags, u16 *low,
108 u16 *high)
109{
Sujith2660b812009-02-09 13:27:26 +0530110 struct ath9k_hw_capabilities *pCap = &ah->caps;
Sujithf1dc5602008-10-29 10:16:30 +0530111
112 if (flags & CHANNEL_5GHZ) {
113 *low = pCap->low_5ghz_chan;
114 *high = pCap->high_5ghz_chan;
115 return true;
116 }
117 if ((flags & CHANNEL_2GHZ)) {
118 *low = pCap->low_2ghz_chan;
119 *high = pCap->high_2ghz_chan;
120 return true;
121 }
122 return false;
123}
124
Sujithcbe61d82009-02-09 13:27:12 +0530125u16 ath9k_hw_computetxtime(struct ath_hw *ah,
Felix Fietkau545750d2009-11-23 22:21:01 +0100126 u8 phy, int kbps,
Sujithf1dc5602008-10-29 10:16:30 +0530127 u32 frameLen, u16 rateix,
128 bool shortPreamble)
129{
130 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
Sujithf1dc5602008-10-29 10:16:30 +0530131
132 if (kbps == 0)
133 return 0;
134
Felix Fietkau545750d2009-11-23 22:21:01 +0100135 switch (phy) {
Sujith46d14a52008-11-18 09:08:13 +0530136 case WLAN_RC_PHY_CCK:
Sujithf1dc5602008-10-29 10:16:30 +0530137 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
Felix Fietkau545750d2009-11-23 22:21:01 +0100138 if (shortPreamble)
Sujithf1dc5602008-10-29 10:16:30 +0530139 phyTime >>= 1;
140 numBits = frameLen << 3;
141 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
142 break;
Sujith46d14a52008-11-18 09:08:13 +0530143 case WLAN_RC_PHY_OFDM:
Sujith2660b812009-02-09 13:27:26 +0530144 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530145 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
146 numBits = OFDM_PLCP_BITS + (frameLen << 3);
147 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
148 txTime = OFDM_SIFS_TIME_QUARTER
149 + OFDM_PREAMBLE_TIME_QUARTER
150 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
Sujith2660b812009-02-09 13:27:26 +0530151 } else if (ah->curchan &&
152 IS_CHAN_HALF_RATE(ah->curchan)) {
Sujithf1dc5602008-10-29 10:16:30 +0530153 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
154 numBits = OFDM_PLCP_BITS + (frameLen << 3);
155 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
156 txTime = OFDM_SIFS_TIME_HALF +
157 OFDM_PREAMBLE_TIME_HALF
158 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
159 } else {
160 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
161 numBits = OFDM_PLCP_BITS + (frameLen << 3);
162 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
163 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
164 + (numSymbols * OFDM_SYMBOL_TIME);
165 }
166 break;
167 default:
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700168 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
Felix Fietkau545750d2009-11-23 22:21:01 +0100169 "Unknown phy %u (rate ix %u)\n", phy, rateix);
Sujithf1dc5602008-10-29 10:16:30 +0530170 txTime = 0;
171 break;
172 }
173
174 return txTime;
175}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400176EXPORT_SYMBOL(ath9k_hw_computetxtime);
Sujithf1dc5602008-10-29 10:16:30 +0530177
Sujithcbe61d82009-02-09 13:27:12 +0530178void ath9k_hw_get_channel_centers(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530179 struct ath9k_channel *chan,
180 struct chan_centers *centers)
181{
182 int8_t extoff;
Sujithf1dc5602008-10-29 10:16:30 +0530183
184 if (!IS_CHAN_HT40(chan)) {
185 centers->ctl_center = centers->ext_center =
186 centers->synth_center = chan->channel;
187 return;
188 }
189
190 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
191 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
192 centers->synth_center =
193 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
194 extoff = 1;
195 } else {
196 centers->synth_center =
197 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
198 extoff = -1;
199 }
200
201 centers->ctl_center =
202 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
Luis R. Rodriguez64200142009-09-13 22:05:04 -0700203 /* 25 MHz spacing is supported by hw but not on upper layers */
Sujithf1dc5602008-10-29 10:16:30 +0530204 centers->ext_center =
Luis R. Rodriguez64200142009-09-13 22:05:04 -0700205 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
Sujithf1dc5602008-10-29 10:16:30 +0530206}
207
208/******************/
209/* Chip Revisions */
210/******************/
211
Sujithcbe61d82009-02-09 13:27:12 +0530212static void ath9k_hw_read_revisions(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530213{
214 u32 val;
215
216 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
217
218 if (val == 0xFF) {
219 val = REG_READ(ah, AR_SREV);
Sujithd535a422009-02-09 13:27:06 +0530220 ah->hw_version.macVersion =
221 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
222 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
Sujith2660b812009-02-09 13:27:26 +0530223 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
Sujithf1dc5602008-10-29 10:16:30 +0530224 } else {
225 if (!AR_SREV_9100(ah))
Sujithd535a422009-02-09 13:27:06 +0530226 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
Sujithf1dc5602008-10-29 10:16:30 +0530227
Sujithd535a422009-02-09 13:27:06 +0530228 ah->hw_version.macRev = val & AR_SREV_REVISION;
Sujithf1dc5602008-10-29 10:16:30 +0530229
Sujithd535a422009-02-09 13:27:06 +0530230 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
Sujith2660b812009-02-09 13:27:26 +0530231 ah->is_pciexpress = true;
Sujithf1dc5602008-10-29 10:16:30 +0530232 }
233}
234
Sujithcbe61d82009-02-09 13:27:12 +0530235static int ath9k_hw_get_radiorev(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530236{
237 u32 val;
238 int i;
239
240 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
241
242 for (i = 0; i < 8; i++)
243 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
244 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
245 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
246
247 return ath9k_hw_reverse_bits(val, 8);
248}
249
250/************************************/
251/* HW Attach, Detach, Init Routines */
252/************************************/
253
Sujithcbe61d82009-02-09 13:27:12 +0530254static void ath9k_hw_disablepcie(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530255{
Sujithfeed0292009-01-29 11:37:35 +0530256 if (AR_SREV_9100(ah))
Sujithf1dc5602008-10-29 10:16:30 +0530257 return;
258
259 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
260 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
261 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
262 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
263 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
264 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
265 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
266 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
267 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
268
269 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
270}
271
Sujithcbe61d82009-02-09 13:27:12 +0530272static bool ath9k_hw_chip_test(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530273{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700274 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530275 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
276 u32 regHold[2];
277 u32 patternData[4] = { 0x55555555,
278 0xaaaaaaaa,
279 0x66666666,
280 0x99999999 };
281 int i, j;
282
283 for (i = 0; i < 2; i++) {
284 u32 addr = regAddr[i];
285 u32 wrData, rdData;
286
287 regHold[i] = REG_READ(ah, addr);
288 for (j = 0; j < 0x100; j++) {
289 wrData = (j << 16) | j;
290 REG_WRITE(ah, addr, wrData);
291 rdData = REG_READ(ah, addr);
292 if (rdData != wrData) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700293 ath_print(common, ATH_DBG_FATAL,
294 "address test failed "
295 "addr: 0x%08x - wr:0x%08x != "
296 "rd:0x%08x\n",
297 addr, wrData, rdData);
Sujithf1dc5602008-10-29 10:16:30 +0530298 return false;
299 }
300 }
301 for (j = 0; j < 4; j++) {
302 wrData = patternData[j];
303 REG_WRITE(ah, addr, wrData);
304 rdData = REG_READ(ah, addr);
305 if (wrData != rdData) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700306 ath_print(common, ATH_DBG_FATAL,
307 "address test failed "
308 "addr: 0x%08x - wr:0x%08x != "
309 "rd:0x%08x\n",
310 addr, wrData, rdData);
Sujithf1dc5602008-10-29 10:16:30 +0530311 return false;
312 }
313 }
314 REG_WRITE(ah, regAddr[i], regHold[i]);
315 }
316 udelay(100);
Sujithcbe61d82009-02-09 13:27:12 +0530317
Sujithf1dc5602008-10-29 10:16:30 +0530318 return true;
319}
320
Luis R. Rodriguezb8b0f372009-08-03 12:24:43 -0700321static void ath9k_hw_init_config(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700322{
323 int i;
324
Sujith2660b812009-02-09 13:27:26 +0530325 ah->config.dma_beacon_response_time = 2;
326 ah->config.sw_beacon_response_time = 10;
327 ah->config.additional_swba_backoff = 0;
328 ah->config.ack_6mb = 0x0;
329 ah->config.cwm_ignore_extcca = 0;
330 ah->config.pcie_powersave_enable = 0;
Sujith2660b812009-02-09 13:27:26 +0530331 ah->config.pcie_clock_req = 0;
Sujith2660b812009-02-09 13:27:26 +0530332 ah->config.pcie_waen = 0;
333 ah->config.analog_shiftreg = 1;
Sujith2660b812009-02-09 13:27:26 +0530334 ah->config.ofdm_trig_low = 200;
335 ah->config.ofdm_trig_high = 500;
336 ah->config.cck_trig_high = 200;
337 ah->config.cck_trig_low = 100;
338 ah->config.enable_ani = 1;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700339
340 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
Sujith2660b812009-02-09 13:27:26 +0530341 ah->config.spurchans[i][0] = AR_NO_SPUR;
342 ah->config.spurchans[i][1] = AR_NO_SPUR;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700343 }
344
Luis R. Rodriguez5ffaf8a2010-02-02 11:58:33 -0500345 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
346 ah->config.ht_enable = 1;
347 else
348 ah->config.ht_enable = 0;
349
Sujith0ce024c2009-12-14 14:57:00 +0530350 ah->config.rx_intr_mitigation = true;
Luis R. Rodriguez61584252009-03-12 18:18:49 -0400351
352 /*
353 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
354 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
355 * This means we use it for all AR5416 devices, and the few
356 * minor PCI AR9280 devices out there.
357 *
358 * Serialization is required because these devices do not handle
359 * well the case of two concurrent reads/writes due to the latency
360 * involved. During one read/write another read/write can be issued
361 * on another CPU while the previous read/write may still be working
362 * on our hardware, if we hit this case the hardware poops in a loop.
363 * We prevent this by serializing reads and writes.
364 *
365 * This issue is not present on PCI-Express devices or pre-AR5416
366 * devices (legacy, 802.11abg).
367 */
368 if (num_possible_cpus() > 1)
David S. Miller2d6a5e92009-03-17 15:01:30 -0700369 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700370}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400371EXPORT_SYMBOL(ath9k_hw_init);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700372
Luis R. Rodriguez50aca252009-08-03 12:24:42 -0700373static void ath9k_hw_init_defaults(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700374{
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700375 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
376
377 regulatory->country_code = CTRY_DEFAULT;
378 regulatory->power_limit = MAX_RATE_POWER;
379 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
380
Sujithd535a422009-02-09 13:27:06 +0530381 ah->hw_version.magic = AR5416_MAGIC;
Sujithd535a422009-02-09 13:27:06 +0530382 ah->hw_version.subvendorid = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700383
384 ah->ah_flags = 0;
Luis R. Rodriguez8df5d1b2009-08-03 12:24:37 -0700385 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
Sujithd535a422009-02-09 13:27:06 +0530386 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700387 if (!AR_SREV_9100(ah))
388 ah->ah_flags = AH_USE_EEPROM;
389
Sujith2660b812009-02-09 13:27:26 +0530390 ah->atim_window = 0;
Sujith2660b812009-02-09 13:27:26 +0530391 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
392 ah->beacon_interval = 100;
393 ah->enable_32kHz_clock = DONT_USE_32KHZ;
394 ah->slottime = (u32) -1;
Sujith2660b812009-02-09 13:27:26 +0530395 ah->globaltxtimeout = (u32) -1;
Gabor Juhoscbdec972009-07-24 17:27:22 +0200396 ah->power_mode = ATH9K_PM_UNDEFINED;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700397}
398
Sujithcbe61d82009-02-09 13:27:12 +0530399static int ath9k_hw_rf_claim(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700400{
401 u32 val;
402
403 REG_WRITE(ah, AR_PHY(0), 0x00000007);
404
405 val = ath9k_hw_get_radiorev(ah);
406 switch (val & AR_RADIO_SREV_MAJOR) {
407 case 0:
408 val = AR_RAD5133_SREV_MAJOR;
409 break;
410 case AR_RAD5133_SREV_MAJOR:
411 case AR_RAD5122_SREV_MAJOR:
412 case AR_RAD2133_SREV_MAJOR:
413 case AR_RAD2122_SREV_MAJOR:
414 break;
415 default:
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700416 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
417 "Radio Chip Rev 0x%02X not supported\n",
418 val & AR_RADIO_SREV_MAJOR);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700419 return -EOPNOTSUPP;
420 }
421
Sujithd535a422009-02-09 13:27:06 +0530422 ah->hw_version.analog5GhzRev = val;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700423
424 return 0;
425}
426
Sujithcbe61d82009-02-09 13:27:12 +0530427static int ath9k_hw_init_macaddr(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700428{
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700429 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530430 u32 sum;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700431 int i;
Sujithf1dc5602008-10-29 10:16:30 +0530432 u16 eeval;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700433
Sujithf1dc5602008-10-29 10:16:30 +0530434 sum = 0;
435 for (i = 0; i < 3; i++) {
Sujithf74df6f2009-02-09 13:27:24 +0530436 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
Sujithf1dc5602008-10-29 10:16:30 +0530437 sum += eeval;
Luis R. Rodriguez15107182009-09-10 09:22:37 -0700438 common->macaddr[2 * i] = eeval >> 8;
439 common->macaddr[2 * i + 1] = eeval & 0xff;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700440 }
Sujithd8baa932009-03-30 15:28:25 +0530441 if (sum == 0 || sum == 0xffff * 3)
Sujithf1dc5602008-10-29 10:16:30 +0530442 return -EADDRNOTAVAIL;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700443
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700444 return 0;
445}
446
Sujithcbe61d82009-02-09 13:27:12 +0530447static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530448{
449 u32 rxgain_type;
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530450
Sujithf74df6f2009-02-09 13:27:24 +0530451 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
452 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530453
454 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
Sujith2660b812009-02-09 13:27:26 +0530455 INIT_INI_ARRAY(&ah->iniModesRxGain,
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530456 ar9280Modes_backoff_13db_rxgain_9280_2,
457 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
458 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
Sujith2660b812009-02-09 13:27:26 +0530459 INIT_INI_ARRAY(&ah->iniModesRxGain,
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530460 ar9280Modes_backoff_23db_rxgain_9280_2,
461 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
462 else
Sujith2660b812009-02-09 13:27:26 +0530463 INIT_INI_ARRAY(&ah->iniModesRxGain,
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530464 ar9280Modes_original_rxgain_9280_2,
465 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
Sujithcbe61d82009-02-09 13:27:12 +0530466 } else {
Sujith2660b812009-02-09 13:27:26 +0530467 INIT_INI_ARRAY(&ah->iniModesRxGain,
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530468 ar9280Modes_original_rxgain_9280_2,
469 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
Sujithcbe61d82009-02-09 13:27:12 +0530470 }
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530471}
472
Sujithcbe61d82009-02-09 13:27:12 +0530473static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530474{
475 u32 txgain_type;
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530476
Sujithf74df6f2009-02-09 13:27:24 +0530477 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
478 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530479
480 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
Sujith2660b812009-02-09 13:27:26 +0530481 INIT_INI_ARRAY(&ah->iniModesTxGain,
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530482 ar9280Modes_high_power_tx_gain_9280_2,
483 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
484 else
Sujith2660b812009-02-09 13:27:26 +0530485 INIT_INI_ARRAY(&ah->iniModesTxGain,
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530486 ar9280Modes_original_tx_gain_9280_2,
487 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
Sujithcbe61d82009-02-09 13:27:12 +0530488 } else {
Sujith2660b812009-02-09 13:27:26 +0530489 INIT_INI_ARRAY(&ah->iniModesTxGain,
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530490 ar9280Modes_original_tx_gain_9280_2,
491 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
Sujithcbe61d82009-02-09 13:27:12 +0530492 }
Senthil Balasubramanian9f804202008-11-13 17:58:41 +0530493}
494
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700495static int ath9k_hw_post_init(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700496{
497 int ecode;
498
Sujith527d4852010-03-17 14:25:16 +0530499 if (!AR_SREV_9271(ah)) {
500 if (!ath9k_hw_chip_test(ah))
501 return -ENODEV;
502 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700503
504 ecode = ath9k_hw_rf_claim(ah);
505 if (ecode != 0)
506 return ecode;
507
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700508 ecode = ath9k_hw_eeprom_init(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700509 if (ecode != 0)
510 return ecode;
Sujith7d01b222009-03-13 08:55:55 +0530511
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700512 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
513 "Eeprom VER: %d, REV: %d\n",
514 ah->eep_ops->get_eeprom_ver(ah),
515 ah->eep_ops->get_eeprom_rev(ah));
Sujith7d01b222009-03-13 08:55:55 +0530516
Luis R. Rodriguez574d6b12009-10-19 02:33:37 -0400517 if (!AR_SREV_9280_10_OR_LATER(ah)) {
518 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
519 if (ecode) {
520 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
521 "Failed allocating banks for "
522 "external radio\n");
523 return ecode;
524 }
525 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700526
527 if (!AR_SREV_9100(ah)) {
528 ath9k_hw_ani_setup(ah);
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700529 ath9k_hw_ani_init(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700530 }
Sujithf1dc5602008-10-29 10:16:30 +0530531
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700532 return 0;
533}
534
Luis R. Rodriguezee2bb462009-08-03 12:24:39 -0700535static bool ath9k_hw_devid_supported(u16 devid)
536{
537 switch (devid) {
538 case AR5416_DEVID_PCI:
539 case AR5416_DEVID_PCIE:
540 case AR5416_AR9100_DEVID:
541 case AR9160_DEVID_PCI:
542 case AR9280_DEVID_PCI:
543 case AR9280_DEVID_PCIE:
544 case AR9285_DEVID_PCIE:
545 case AR5416_DEVID_AR9287_PCI:
546 case AR5416_DEVID_AR9287_PCIE:
Luis R. Rodriguez5ffaf8a2010-02-02 11:58:33 -0500547 case AR2427_DEVID_PCIE:
Luis R. Rodriguezee2bb462009-08-03 12:24:39 -0700548 return true;
549 default:
550 break;
551 }
552 return false;
553}
554
Luis R. Rodriguezf9d4a662009-08-03 12:24:41 -0700555static bool ath9k_hw_macversion_supported(u32 macversion)
556{
557 switch (macversion) {
558 case AR_SREV_VERSION_5416_PCI:
559 case AR_SREV_VERSION_5416_PCIE:
560 case AR_SREV_VERSION_9160:
561 case AR_SREV_VERSION_9100:
562 case AR_SREV_VERSION_9280:
563 case AR_SREV_VERSION_9285:
564 case AR_SREV_VERSION_9287:
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400565 case AR_SREV_VERSION_9271:
Luis R. Rodriguez7976b422009-09-23 23:07:02 -0400566 return true;
Luis R. Rodriguezf9d4a662009-08-03 12:24:41 -0700567 default:
568 break;
569 }
570 return false;
571}
572
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700573static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700574{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700575 if (AR_SREV_9160_10_OR_LATER(ah)) {
576 if (AR_SREV_9280_10_OR_LATER(ah)) {
Sujith2660b812009-02-09 13:27:26 +0530577 ah->iq_caldata.calData = &iq_cal_single_sample;
578 ah->adcgain_caldata.calData =
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700579 &adc_gain_cal_single_sample;
Sujith2660b812009-02-09 13:27:26 +0530580 ah->adcdc_caldata.calData =
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700581 &adc_dc_cal_single_sample;
Sujith2660b812009-02-09 13:27:26 +0530582 ah->adcdc_calinitdata.calData =
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700583 &adc_init_dc_cal;
584 } else {
Sujith2660b812009-02-09 13:27:26 +0530585 ah->iq_caldata.calData = &iq_cal_multi_sample;
586 ah->adcgain_caldata.calData =
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700587 &adc_gain_cal_multi_sample;
Sujith2660b812009-02-09 13:27:26 +0530588 ah->adcdc_caldata.calData =
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700589 &adc_dc_cal_multi_sample;
Sujith2660b812009-02-09 13:27:26 +0530590 ah->adcdc_calinitdata.calData =
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700591 &adc_init_dc_cal;
592 }
Sujith2660b812009-02-09 13:27:26 +0530593 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700594 }
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700595}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700596
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700597static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
598{
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400599 if (AR_SREV_9271(ah)) {
Luis R. Rodriguez85643282009-10-19 02:33:33 -0400600 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
601 ARRAY_SIZE(ar9271Modes_9271), 6);
602 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
603 ARRAY_SIZE(ar9271Common_9271), 2);
Sujith70807e92010-03-17 14:25:14 +0530604 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
605 ar9271Common_normal_cck_fir_coeff_9271,
606 ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
607 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
608 ar9271Common_japan_2484_cck_fir_coeff_9271,
609 ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
Luis R. Rodriguez85643282009-10-19 02:33:33 -0400610 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
611 ar9271Modes_9271_1_0_only,
612 ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
Sujith70807e92010-03-17 14:25:14 +0530613 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
614 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
615 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
616 ar9271Modes_high_power_tx_gain_9271,
617 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
618 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
619 ar9271Modes_normal_power_tx_gain_9271,
620 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400621 return;
622 }
623
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530624 if (AR_SREV_9287_11_OR_LATER(ah)) {
625 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
626 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
627 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
628 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
629 if (ah->config.pcie_clock_req)
630 INIT_INI_ARRAY(&ah->iniPcieSerdes,
631 ar9287PciePhy_clkreq_off_L1_9287_1_1,
632 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
633 else
634 INIT_INI_ARRAY(&ah->iniPcieSerdes,
635 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
636 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
637 2);
638 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
639 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
640 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
641 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
642 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700643
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530644 if (ah->config.pcie_clock_req)
645 INIT_INI_ARRAY(&ah->iniPcieSerdes,
646 ar9287PciePhy_clkreq_off_L1_9287_1_0,
647 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
648 else
649 INIT_INI_ARRAY(&ah->iniPcieSerdes,
650 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
651 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
652 2);
653 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
654
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530655
Sujith2660b812009-02-09 13:27:26 +0530656 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530657 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
Sujith2660b812009-02-09 13:27:26 +0530658 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530659 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
660
Sujith2660b812009-02-09 13:27:26 +0530661 if (ah->config.pcie_clock_req) {
662 INIT_INI_ARRAY(&ah->iniPcieSerdes,
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530663 ar9285PciePhy_clkreq_off_L1_9285_1_2,
664 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
665 } else {
Sujith2660b812009-02-09 13:27:26 +0530666 INIT_INI_ARRAY(&ah->iniPcieSerdes,
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530667 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
668 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
669 2);
670 }
671 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
Sujith2660b812009-02-09 13:27:26 +0530672 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530673 ARRAY_SIZE(ar9285Modes_9285), 6);
Sujith2660b812009-02-09 13:27:26 +0530674 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530675 ARRAY_SIZE(ar9285Common_9285), 2);
676
Sujith2660b812009-02-09 13:27:26 +0530677 if (ah->config.pcie_clock_req) {
678 INIT_INI_ARRAY(&ah->iniPcieSerdes,
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530679 ar9285PciePhy_clkreq_off_L1_9285,
680 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
681 } else {
Sujith2660b812009-02-09 13:27:26 +0530682 INIT_INI_ARRAY(&ah->iniPcieSerdes,
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530683 ar9285PciePhy_clkreq_always_on_L1_9285,
684 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
685 }
686 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
Sujith2660b812009-02-09 13:27:26 +0530687 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700688 ARRAY_SIZE(ar9280Modes_9280_2), 6);
Sujith2660b812009-02-09 13:27:26 +0530689 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700690 ARRAY_SIZE(ar9280Common_9280_2), 2);
691
Sujith2660b812009-02-09 13:27:26 +0530692 if (ah->config.pcie_clock_req) {
693 INIT_INI_ARRAY(&ah->iniPcieSerdes,
Sujithf1dc5602008-10-29 10:16:30 +0530694 ar9280PciePhy_clkreq_off_L1_9280,
695 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700696 } else {
Sujith2660b812009-02-09 13:27:26 +0530697 INIT_INI_ARRAY(&ah->iniPcieSerdes,
Sujithf1dc5602008-10-29 10:16:30 +0530698 ar9280PciePhy_clkreq_always_on_L1_9280,
699 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700700 }
Sujith2660b812009-02-09 13:27:26 +0530701 INIT_INI_ARRAY(&ah->iniModesAdditional,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700702 ar9280Modes_fast_clock_9280_2,
Sujithf1dc5602008-10-29 10:16:30 +0530703 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700704 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
Sujith2660b812009-02-09 13:27:26 +0530705 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700706 ARRAY_SIZE(ar9280Modes_9280), 6);
Sujith2660b812009-02-09 13:27:26 +0530707 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700708 ARRAY_SIZE(ar9280Common_9280), 2);
709 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
Sujith2660b812009-02-09 13:27:26 +0530710 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700711 ARRAY_SIZE(ar5416Modes_9160), 6);
Sujith2660b812009-02-09 13:27:26 +0530712 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700713 ARRAY_SIZE(ar5416Common_9160), 2);
Sujith2660b812009-02-09 13:27:26 +0530714 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700715 ARRAY_SIZE(ar5416Bank0_9160), 2);
Sujith2660b812009-02-09 13:27:26 +0530716 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700717 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
Sujith2660b812009-02-09 13:27:26 +0530718 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700719 ARRAY_SIZE(ar5416Bank1_9160), 2);
Sujith2660b812009-02-09 13:27:26 +0530720 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700721 ARRAY_SIZE(ar5416Bank2_9160), 2);
Sujith2660b812009-02-09 13:27:26 +0530722 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700723 ARRAY_SIZE(ar5416Bank3_9160), 3);
Sujith2660b812009-02-09 13:27:26 +0530724 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700725 ARRAY_SIZE(ar5416Bank6_9160), 3);
Sujith2660b812009-02-09 13:27:26 +0530726 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700727 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
Sujith2660b812009-02-09 13:27:26 +0530728 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700729 ARRAY_SIZE(ar5416Bank7_9160), 2);
730 if (AR_SREV_9160_11(ah)) {
Sujith2660b812009-02-09 13:27:26 +0530731 INIT_INI_ARRAY(&ah->iniAddac,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700732 ar5416Addac_91601_1,
733 ARRAY_SIZE(ar5416Addac_91601_1), 2);
734 } else {
Sujith2660b812009-02-09 13:27:26 +0530735 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700736 ARRAY_SIZE(ar5416Addac_9160), 2);
737 }
738 } else if (AR_SREV_9100_OR_LATER(ah)) {
Sujith2660b812009-02-09 13:27:26 +0530739 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700740 ARRAY_SIZE(ar5416Modes_9100), 6);
Sujith2660b812009-02-09 13:27:26 +0530741 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700742 ARRAY_SIZE(ar5416Common_9100), 2);
Sujith2660b812009-02-09 13:27:26 +0530743 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700744 ARRAY_SIZE(ar5416Bank0_9100), 2);
Sujith2660b812009-02-09 13:27:26 +0530745 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700746 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
Sujith2660b812009-02-09 13:27:26 +0530747 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700748 ARRAY_SIZE(ar5416Bank1_9100), 2);
Sujith2660b812009-02-09 13:27:26 +0530749 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700750 ARRAY_SIZE(ar5416Bank2_9100), 2);
Sujith2660b812009-02-09 13:27:26 +0530751 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700752 ARRAY_SIZE(ar5416Bank3_9100), 3);
Sujith2660b812009-02-09 13:27:26 +0530753 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700754 ARRAY_SIZE(ar5416Bank6_9100), 3);
Sujith2660b812009-02-09 13:27:26 +0530755 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700756 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
Sujith2660b812009-02-09 13:27:26 +0530757 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700758 ARRAY_SIZE(ar5416Bank7_9100), 2);
Sujith2660b812009-02-09 13:27:26 +0530759 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700760 ARRAY_SIZE(ar5416Addac_9100), 2);
761 } else {
Sujith2660b812009-02-09 13:27:26 +0530762 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700763 ARRAY_SIZE(ar5416Modes), 6);
Sujith2660b812009-02-09 13:27:26 +0530764 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700765 ARRAY_SIZE(ar5416Common), 2);
Sujith2660b812009-02-09 13:27:26 +0530766 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700767 ARRAY_SIZE(ar5416Bank0), 2);
Sujith2660b812009-02-09 13:27:26 +0530768 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700769 ARRAY_SIZE(ar5416BB_RfGain), 3);
Sujith2660b812009-02-09 13:27:26 +0530770 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700771 ARRAY_SIZE(ar5416Bank1), 2);
Sujith2660b812009-02-09 13:27:26 +0530772 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700773 ARRAY_SIZE(ar5416Bank2), 2);
Sujith2660b812009-02-09 13:27:26 +0530774 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700775 ARRAY_SIZE(ar5416Bank3), 3);
Sujith2660b812009-02-09 13:27:26 +0530776 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700777 ARRAY_SIZE(ar5416Bank6), 3);
Sujith2660b812009-02-09 13:27:26 +0530778 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700779 ARRAY_SIZE(ar5416Bank6TPC), 3);
Sujith2660b812009-02-09 13:27:26 +0530780 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700781 ARRAY_SIZE(ar5416Bank7), 2);
Sujith2660b812009-02-09 13:27:26 +0530782 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700783 ARRAY_SIZE(ar5416Addac), 2);
784 }
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700785}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700786
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700787static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
788{
Vivek Natarajanb37fa872009-09-23 16:27:27 +0530789 if (AR_SREV_9287_11_OR_LATER(ah))
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530790 INIT_INI_ARRAY(&ah->iniModesRxGain,
791 ar9287Modes_rx_gain_9287_1_1,
792 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
793 else if (AR_SREV_9287_10(ah))
794 INIT_INI_ARRAY(&ah->iniModesRxGain,
795 ar9287Modes_rx_gain_9287_1_0,
796 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
797 else if (AR_SREV_9280_20(ah))
798 ath9k_hw_init_rxgain_ini(ah);
799
Vivek Natarajanb37fa872009-09-23 16:27:27 +0530800 if (AR_SREV_9287_11_OR_LATER(ah)) {
Vivek Natarajanac88b6e2009-07-23 10:59:57 +0530801 INIT_INI_ARRAY(&ah->iniModesTxGain,
802 ar9287Modes_tx_gain_9287_1_1,
803 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
804 } else if (AR_SREV_9287_10(ah)) {
805 INIT_INI_ARRAY(&ah->iniModesTxGain,
806 ar9287Modes_tx_gain_9287_1_0,
807 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
808 } else if (AR_SREV_9280_20(ah)) {
809 ath9k_hw_init_txgain_ini(ah);
810 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530811 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
812
813 /* txgain table */
814 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
Vivek Natarajan53bc7aa2010-04-05 14:48:04 +0530815 if (AR_SREV_9285E_20(ah)) {
816 INIT_INI_ARRAY(&ah->iniModesTxGain,
817 ar9285Modes_XE2_0_high_power,
818 ARRAY_SIZE(
819 ar9285Modes_XE2_0_high_power), 6);
820 } else {
821 INIT_INI_ARRAY(&ah->iniModesTxGain,
822 ar9285Modes_high_power_tx_gain_9285_1_2,
823 ARRAY_SIZE(
824 ar9285Modes_high_power_tx_gain_9285_1_2), 6);
825 }
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530826 } else {
Vivek Natarajan53bc7aa2010-04-05 14:48:04 +0530827 if (AR_SREV_9285E_20(ah)) {
828 INIT_INI_ARRAY(&ah->iniModesTxGain,
829 ar9285Modes_XE2_0_normal_power,
830 ARRAY_SIZE(
831 ar9285Modes_XE2_0_normal_power), 6);
832 } else {
833 INIT_INI_ARRAY(&ah->iniModesTxGain,
834 ar9285Modes_original_tx_gain_9285_1_2,
835 ARRAY_SIZE(
836 ar9285Modes_original_tx_gain_9285_1_2), 6);
837 }
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530838 }
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530839 }
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700840}
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530841
Felix Fietkauaa8bc9e2010-01-23 20:04:18 +0100842static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700843{
Pavel Roskin2eb46d92010-04-07 01:33:33 -0400844 struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
845 struct ath_common *common = ath9k_hw_common(ah);
Sujith06d0f062009-02-12 10:06:45 +0530846
Pavel Roskin2eb46d92010-04-07 01:33:33 -0400847 ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
848 (ah->eep_map != EEP_MAP_4KBITS) &&
849 ((pBase->version & 0xff) > 0x0a) &&
850 (pBase->pwdclkind == 0);
Sujith06d0f062009-02-12 10:06:45 +0530851
Pavel Roskin2eb46d92010-04-07 01:33:33 -0400852 if (ah->need_an_top2_fixup)
853 ath_print(common, ATH_DBG_EEPROM,
854 "needs fixup for AR_AN_TOP2 register\n");
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700855}
856
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700857int ath9k_hw_init(struct ath_hw *ah)
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700858{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700859 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700860 int r = 0;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700861
Sujithffa49f82010-04-01 10:28:23 +0530862 if (common->bus_ops->ath_bus_type != ATH_USB) {
863 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
864 ath_print(common, ATH_DBG_FATAL,
865 "Unsupported device ID: 0x%0x\n",
866 ah->hw_version.devid);
867 return -EOPNOTSUPP;
868 }
Luis R. Rodriguez3ca34032009-09-23 23:07:01 -0400869 }
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700870
871 ath9k_hw_init_defaults(ah);
872 ath9k_hw_init_config(ah);
873
874 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700875 ath_print(common, ATH_DBG_FATAL,
876 "Couldn't reset chip\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700877 return -EIO;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700878 }
879
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -0700880 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700881 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700882 return -EIO;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700883 }
884
885 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
886 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
887 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
888 ah->config.serialize_regmode =
889 SER_REG_MODE_ON;
890 } else {
891 ah->config.serialize_regmode =
892 SER_REG_MODE_OFF;
893 }
894 }
895
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700896 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700897 ah->config.serialize_regmode);
898
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -0500899 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
900 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
901 else
902 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
903
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700904 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700905 ath_print(common, ATH_DBG_FATAL,
906 "Mac Chip Rev 0x%02x.%x is not supported by "
907 "this driver\n", ah->hw_version.macVersion,
908 ah->hw_version.macRev);
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700909 return -EOPNOTSUPP;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700910 }
911
912 if (AR_SREV_9100(ah)) {
913 ah->iq_caldata.calData = &iq_cal_multi_sample;
914 ah->supp_cals = IQ_MISMATCH_CAL;
915 ah->is_pciexpress = false;
916 }
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400917
918 if (AR_SREV_9271(ah))
919 ah->is_pciexpress = false;
920
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700921 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
922
923 ath9k_hw_init_cal_settings(ah);
924
925 ah->ani_function = ATH9K_ANI_ALL;
Luis R. Rodrigueze68a0602009-10-19 02:33:41 -0400926 if (AR_SREV_9280_10_OR_LATER(ah)) {
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700927 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
Luis R. Rodrigueze68a0602009-10-19 02:33:41 -0400928 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
Luis R. Rodriguezae478cf2009-10-19 02:33:43 -0400929 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
930 } else {
Luis R. Rodrigueze68a0602009-10-19 02:33:41 -0400931 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
Luis R. Rodriguezae478cf2009-10-19 02:33:43 -0400932 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
933 }
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700934
935 ath9k_hw_init_mode_regs(ah);
936
937 if (ah->is_pciexpress)
Vivek Natarajan93b1b372009-09-17 09:24:58 +0530938 ath9k_hw_configpcipowersave(ah, 0, 0);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700939 else
940 ath9k_hw_disablepcie(ah);
941
Sujith193cd452009-09-18 15:04:07 +0530942 /* Support for Japan ch.14 (2484) spread */
943 if (AR_SREV_9287_11_OR_LATER(ah)) {
944 INIT_INI_ARRAY(&ah->iniCckfirNormal,
945 ar9287Common_normal_cck_fir_coeff_92871_1,
946 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
947 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
948 ar9287Common_japan_2484_cck_fir_coeff_92871_1,
949 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
950 }
951
Luis R. Rodriguezf637cfd2009-08-03 12:24:46 -0700952 r = ath9k_hw_post_init(ah);
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700953 if (r)
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700954 return r;
Luis R. Rodriguezaa4058a2009-08-03 12:24:45 -0700955
956 ath9k_hw_init_mode_gain_regs(ah);
Gabor Juhosa9a29ce2009-11-27 12:01:35 +0100957 r = ath9k_hw_fill_cap_info(ah);
958 if (r)
959 return r;
960
Felix Fietkauaa8bc9e2010-01-23 20:04:18 +0100961 ath9k_hw_init_eeprom_fix(ah);
Sujithf6688cd2008-12-07 21:43:10 +0530962
Luis R. Rodriguez4f3acf82009-08-03 12:24:36 -0700963 r = ath9k_hw_init_macaddr(ah);
964 if (r) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700965 ath_print(common, ATH_DBG_FATAL,
966 "Failed to initialize MAC address\n");
Luis R. Rodriguez95fafca2009-08-03 12:24:54 -0700967 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700968 }
969
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400970 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
Sujith2660b812009-02-09 13:27:26 +0530971 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700972 else
Sujith2660b812009-02-09 13:27:26 +0530973 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700974
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700975 ath9k_init_nfcal_hist_buffer(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700976
Luis R. Rodriguez211f5852009-10-06 21:19:07 -0400977 common->state = ATH_HW_INITIALIZED;
978
Luis R. Rodriguez4f3acf82009-08-03 12:24:36 -0700979 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -0700980}
981
Sujithcbe61d82009-02-09 13:27:12 +0530982static void ath9k_hw_init_bb(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530983 struct ath9k_channel *chan)
984{
985 u32 synthDelay;
986
987 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
Sujith788a3d62008-11-18 09:09:54 +0530988 if (IS_CHAN_B(chan))
Sujithf1dc5602008-10-29 10:16:30 +0530989 synthDelay = (4 * synthDelay) / 22;
990 else
991 synthDelay /= 10;
992
993 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
994
995 udelay(synthDelay + BASE_ACTIVATE_DELAY);
996}
997
Sujithcbe61d82009-02-09 13:27:12 +0530998static void ath9k_hw_init_qos(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530999{
1000 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1001 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1002
1003 REG_WRITE(ah, AR_QOS_NO_ACK,
1004 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1005 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1006 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1007
1008 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1009 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1010 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1011 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1012 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1013}
1014
Sujithcbe61d82009-02-09 13:27:12 +05301015static void ath9k_hw_init_pll(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05301016 struct ath9k_channel *chan)
1017{
1018 u32 pll;
1019
1020 if (AR_SREV_9100(ah)) {
1021 if (chan && IS_CHAN_5GHZ(chan))
1022 pll = 0x1450;
1023 else
1024 pll = 0x1458;
1025 } else {
1026 if (AR_SREV_9280_10_OR_LATER(ah)) {
1027 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1028
1029 if (chan && IS_CHAN_HALF_RATE(chan))
1030 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1031 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1032 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1033
1034 if (chan && IS_CHAN_5GHZ(chan)) {
1035 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1036
1037
1038 if (AR_SREV_9280_20(ah)) {
1039 if (((chan->channel % 20) == 0)
1040 || ((chan->channel % 10) == 0))
1041 pll = 0x2850;
1042 else
1043 pll = 0x142c;
1044 }
1045 } else {
1046 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1047 }
1048
1049 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1050
1051 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1052
1053 if (chan && IS_CHAN_HALF_RATE(chan))
1054 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1055 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1056 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1057
1058 if (chan && IS_CHAN_5GHZ(chan))
1059 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1060 else
1061 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1062 } else {
1063 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1064
1065 if (chan && IS_CHAN_HALF_RATE(chan))
1066 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1067 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1068 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1069
1070 if (chan && IS_CHAN_5GHZ(chan))
1071 pll |= SM(0xa, AR_RTC_PLL_DIV);
1072 else
1073 pll |= SM(0xb, AR_RTC_PLL_DIV);
1074 }
1075 }
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001076 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
Sujithf1dc5602008-10-29 10:16:30 +05301077
Luis R. Rodriguezc75724d2009-10-19 02:33:34 -04001078 /* Switch the core clock for ar9271 to 117Mhz */
1079 if (AR_SREV_9271(ah)) {
Sujith25e2ab12010-03-17 14:25:22 +05301080 udelay(500);
1081 REG_WRITE(ah, 0x50040, 0x304);
Luis R. Rodriguezc75724d2009-10-19 02:33:34 -04001082 }
1083
Sujithf1dc5602008-10-29 10:16:30 +05301084 udelay(RTC_PLL_SETTLE_DELAY);
1085
1086 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1087}
1088
Sujithcbe61d82009-02-09 13:27:12 +05301089static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301090{
Sujithf1dc5602008-10-29 10:16:30 +05301091 int rx_chainmask, tx_chainmask;
1092
Sujith2660b812009-02-09 13:27:26 +05301093 rx_chainmask = ah->rxchainmask;
1094 tx_chainmask = ah->txchainmask;
Sujithf1dc5602008-10-29 10:16:30 +05301095
1096 switch (rx_chainmask) {
1097 case 0x5:
1098 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1099 AR_PHY_SWAP_ALT_CHAIN);
1100 case 0x3:
Sujithcb53a152009-11-16 11:40:57 +05301101 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
Sujithf1dc5602008-10-29 10:16:30 +05301102 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1103 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1104 break;
1105 }
1106 case 0x1:
1107 case 0x2:
Sujithf1dc5602008-10-29 10:16:30 +05301108 case 0x7:
1109 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1110 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1111 break;
1112 default:
1113 break;
1114 }
1115
1116 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1117 if (tx_chainmask == 0x5) {
1118 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1119 AR_PHY_SWAP_ALT_CHAIN);
1120 }
1121 if (AR_SREV_9100(ah))
1122 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1123 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1124}
1125
Sujithcbe61d82009-02-09 13:27:12 +05301126static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
Colin McCabed97809d2008-12-01 13:38:55 -08001127 enum nl80211_iftype opmode)
Sujithf1dc5602008-10-29 10:16:30 +05301128{
Pavel Roskin152d5302010-03-31 18:05:37 -04001129 u32 imr_reg = AR_IMR_TXERR |
Sujithf1dc5602008-10-29 10:16:30 +05301130 AR_IMR_TXURN |
1131 AR_IMR_RXERR |
1132 AR_IMR_RXORN |
1133 AR_IMR_BCNMISC;
1134
Sujith0ce024c2009-12-14 14:57:00 +05301135 if (ah->config.rx_intr_mitigation)
Pavel Roskin152d5302010-03-31 18:05:37 -04001136 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
Sujithf1dc5602008-10-29 10:16:30 +05301137 else
Pavel Roskin152d5302010-03-31 18:05:37 -04001138 imr_reg |= AR_IMR_RXOK;
Sujithf1dc5602008-10-29 10:16:30 +05301139
Pavel Roskin152d5302010-03-31 18:05:37 -04001140 imr_reg |= AR_IMR_TXOK;
Sujithf1dc5602008-10-29 10:16:30 +05301141
Colin McCabed97809d2008-12-01 13:38:55 -08001142 if (opmode == NL80211_IFTYPE_AP)
Pavel Roskin152d5302010-03-31 18:05:37 -04001143 imr_reg |= AR_IMR_MIB;
Sujithf1dc5602008-10-29 10:16:30 +05301144
Pavel Roskin152d5302010-03-31 18:05:37 -04001145 REG_WRITE(ah, AR_IMR, imr_reg);
Pavel Roskin74bad5c2010-02-23 18:15:27 -05001146 ah->imrs2_reg |= AR_IMR_S2_GTT;
1147 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
Sujithf1dc5602008-10-29 10:16:30 +05301148
1149 if (!AR_SREV_9100(ah)) {
1150 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1151 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1152 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1153 }
1154}
1155
Felix Fietkau0005baf2010-01-15 02:33:40 +01001156static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
Sujithf1dc5602008-10-29 10:16:30 +05301157{
Felix Fietkau0005baf2010-01-15 02:33:40 +01001158 u32 val = ath9k_hw_mac_to_clks(ah, us);
1159 val = min(val, (u32) 0xFFFF);
1160 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
Sujithf1dc5602008-10-29 10:16:30 +05301161}
1162
Felix Fietkau0005baf2010-01-15 02:33:40 +01001163static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
Sujithf1dc5602008-10-29 10:16:30 +05301164{
Felix Fietkau0005baf2010-01-15 02:33:40 +01001165 u32 val = ath9k_hw_mac_to_clks(ah, us);
1166 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1167 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1168}
1169
1170static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1171{
1172 u32 val = ath9k_hw_mac_to_clks(ah, us);
1173 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1174 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
Sujithf1dc5602008-10-29 10:16:30 +05301175}
1176
Sujithcbe61d82009-02-09 13:27:12 +05301177static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
Sujithf1dc5602008-10-29 10:16:30 +05301178{
Sujithf1dc5602008-10-29 10:16:30 +05301179 if (tu > 0xFFFF) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001180 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1181 "bad global tx timeout %u\n", tu);
Sujith2660b812009-02-09 13:27:26 +05301182 ah->globaltxtimeout = (u32) -1;
Sujithf1dc5602008-10-29 10:16:30 +05301183 return false;
1184 } else {
1185 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
Sujith2660b812009-02-09 13:27:26 +05301186 ah->globaltxtimeout = tu;
Sujithf1dc5602008-10-29 10:16:30 +05301187 return true;
1188 }
1189}
1190
Felix Fietkau0005baf2010-01-15 02:33:40 +01001191void ath9k_hw_init_global_settings(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301192{
Felix Fietkau0005baf2010-01-15 02:33:40 +01001193 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1194 int acktimeout;
Felix Fietkaue239d852010-01-15 02:34:58 +01001195 int slottime;
Felix Fietkau0005baf2010-01-15 02:33:40 +01001196 int sifstime;
1197
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001198 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1199 ah->misc_mode);
Sujithf1dc5602008-10-29 10:16:30 +05301200
Sujith2660b812009-02-09 13:27:26 +05301201 if (ah->misc_mode != 0)
Sujithf1dc5602008-10-29 10:16:30 +05301202 REG_WRITE(ah, AR_PCU_MISC,
Sujith2660b812009-02-09 13:27:26 +05301203 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
Felix Fietkau0005baf2010-01-15 02:33:40 +01001204
1205 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1206 sifstime = 16;
1207 else
1208 sifstime = 10;
1209
Felix Fietkaue239d852010-01-15 02:34:58 +01001210 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1211 slottime = ah->slottime + 3 * ah->coverage_class;
1212 acktimeout = slottime + sifstime;
Felix Fietkau42c45682010-02-11 18:07:19 +01001213
1214 /*
1215 * Workaround for early ACK timeouts, add an offset to match the
1216 * initval's 64us ack timeout value.
1217 * This was initially only meant to work around an issue with delayed
1218 * BA frames in some implementations, but it has been found to fix ACK
1219 * timeout issues in other cases as well.
1220 */
1221 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1222 acktimeout += 64 - sifstime - ah->slottime;
1223
Felix Fietkaue239d852010-01-15 02:34:58 +01001224 ath9k_hw_setslottime(ah, slottime);
Felix Fietkau0005baf2010-01-15 02:33:40 +01001225 ath9k_hw_set_ack_timeout(ah, acktimeout);
1226 ath9k_hw_set_cts_timeout(ah, acktimeout);
Sujith2660b812009-02-09 13:27:26 +05301227 if (ah->globaltxtimeout != (u32) -1)
1228 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
Sujithf1dc5602008-10-29 10:16:30 +05301229}
Felix Fietkau0005baf2010-01-15 02:33:40 +01001230EXPORT_SYMBOL(ath9k_hw_init_global_settings);
Sujithf1dc5602008-10-29 10:16:30 +05301231
Sujith285f2dd2010-01-08 10:36:07 +05301232void ath9k_hw_deinit(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001233{
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001234 struct ath_common *common = ath9k_hw_common(ah);
1235
Sujith736b3a22010-03-17 14:25:24 +05301236 if (common->state < ATH_HW_INITIALIZED)
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001237 goto free_hw;
1238
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001239 if (!AR_SREV_9100(ah))
Luis R. Rodrigueze70c0cf2009-08-03 12:24:51 -07001240 ath9k_hw_ani_disable(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001241
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001242 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
Luis R. Rodriguez211f5852009-10-06 21:19:07 -04001243
1244free_hw:
Luis R. Rodriguezdc51dd52009-10-19 02:33:39 -04001245 if (!AR_SREV_9280_10_OR_LATER(ah))
1246 ath9k_hw_rf_free_ext_banks(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001247}
Sujith285f2dd2010-01-08 10:36:07 +05301248EXPORT_SYMBOL(ath9k_hw_deinit);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001249
Sujithf1dc5602008-10-29 10:16:30 +05301250/*******/
1251/* INI */
1252/*******/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001253
Sujithcbe61d82009-02-09 13:27:12 +05301254static void ath9k_hw_override_ini(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05301255 struct ath9k_channel *chan)
1256{
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001257 u32 val;
1258
Senthil Balasubramanian8aa15e12008-12-08 19:43:50 +05301259 /*
1260 * Set the RX_ABORT and RX_DIS and clear if off only after
1261 * RXE is set for MAC. This prevents frames with corrupted
1262 * descriptor status.
1263 */
1264 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1265
Vasanthakumar Thiagarajan204d7942009-09-17 09:26:14 +05301266 if (AR_SREV_9280_10_OR_LATER(ah)) {
Sujith70807e92010-03-17 14:25:14 +05301267 val = REG_READ(ah, AR_PCU_MISC_MODE2);
1268
1269 if (!AR_SREV_9271(ah))
1270 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
Vasanthakumar Thiagarajan204d7942009-09-17 09:26:14 +05301271
1272 if (AR_SREV_9287_10_OR_LATER(ah))
1273 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1274
1275 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1276 }
Senthil Balasubramanian8aa15e12008-12-08 19:43:50 +05301277
Gabor Juhosa8c96d32009-03-06 09:08:51 +01001278 if (!AR_SREV_5416_20_OR_LATER(ah) ||
Sujithf1dc5602008-10-29 10:16:30 +05301279 AR_SREV_9280_10_OR_LATER(ah))
1280 return;
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001281 /*
1282 * Disable BB clock gating
1283 * Necessary to avoid issues on AR5416 2.0
1284 */
Sujithf1dc5602008-10-29 10:16:30 +05301285 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
Felix Fietkau7bfbae12010-02-24 04:43:05 +01001286
1287 /*
1288 * Disable RIFS search on some chips to avoid baseband
1289 * hang issues.
1290 */
1291 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1292 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1293 val &= ~AR_PHY_RIFS_INIT_DELAY;
1294 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1295 }
Sujithf1dc5602008-10-29 10:16:30 +05301296}
1297
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +05301298static void ath9k_olc_init(struct ath_hw *ah)
1299{
1300 u32 i;
1301
Vivek Natarajandb91f2e2009-08-14 11:27:16 +05301302 if (OLC_FOR_AR9287_10_LATER) {
1303 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1304 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1305 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1306 AR9287_AN_TXPC0_TXPCMODE,
1307 AR9287_AN_TXPC0_TXPCMODE_S,
1308 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1309 udelay(100);
1310 } else {
1311 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1312 ah->originalGain[i] =
1313 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1314 AR_PHY_TX_GAIN);
1315 ah->PDADCdelta = 0;
1316 }
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +05301317}
1318
Bob Copeland3a702e42009-03-30 22:30:29 -04001319static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1320 struct ath9k_channel *chan)
1321{
1322 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1323
1324 if (IS_CHAN_B(chan))
1325 ctl |= CTL_11B;
1326 else if (IS_CHAN_G(chan))
1327 ctl |= CTL_11G;
1328 else
1329 ctl |= CTL_11A;
1330
1331 return ctl;
1332}
1333
Sujithcbe61d82009-02-09 13:27:12 +05301334static int ath9k_hw_process_ini(struct ath_hw *ah,
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001335 struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05301336{
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07001337 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301338 int i, regWrites = 0;
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001339 struct ieee80211_channel *channel = chan->chan;
Sujithf1dc5602008-10-29 10:16:30 +05301340 u32 modesIndex, freqIndex;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001341
Sujithf1dc5602008-10-29 10:16:30 +05301342 switch (chan->chanmode) {
1343 case CHANNEL_A:
1344 case CHANNEL_A_HT20:
1345 modesIndex = 1;
1346 freqIndex = 1;
1347 break;
1348 case CHANNEL_A_HT40PLUS:
1349 case CHANNEL_A_HT40MINUS:
1350 modesIndex = 2;
1351 freqIndex = 1;
1352 break;
1353 case CHANNEL_G:
1354 case CHANNEL_G_HT20:
1355 case CHANNEL_B:
1356 modesIndex = 4;
1357 freqIndex = 2;
1358 break;
1359 case CHANNEL_G_HT40PLUS:
1360 case CHANNEL_G_HT40MINUS:
1361 modesIndex = 3;
1362 freqIndex = 2;
1363 break;
1364
1365 default:
1366 return -EINVAL;
1367 }
1368
Sujith70807e92010-03-17 14:25:14 +05301369 /* Set correct baseband to analog shift setting to access analog chips */
Sujithf1dc5602008-10-29 10:16:30 +05301370 REG_WRITE(ah, AR_PHY(0), 0x00000007);
Sujith70807e92010-03-17 14:25:14 +05301371
1372 /* Write ADDAC shifts */
Sujithf1dc5602008-10-29 10:16:30 +05301373 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
Sujithf74df6f2009-02-09 13:27:24 +05301374 ah->eep_ops->set_addac(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301375
Gabor Juhosa8c96d32009-03-06 09:08:51 +01001376 if (AR_SREV_5416_22_OR_LATER(ah)) {
Sujith2660b812009-02-09 13:27:26 +05301377 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
Sujithf1dc5602008-10-29 10:16:30 +05301378 } else {
1379 struct ar5416IniArray temp;
1380 u32 addacSize =
Sujith2660b812009-02-09 13:27:26 +05301381 sizeof(u32) * ah->iniAddac.ia_rows *
1382 ah->iniAddac.ia_columns;
Sujithf1dc5602008-10-29 10:16:30 +05301383
Sujith70807e92010-03-17 14:25:14 +05301384 /* For AR5416 2.0/2.1 */
Sujith2660b812009-02-09 13:27:26 +05301385 memcpy(ah->addac5416_21,
1386 ah->iniAddac.ia_array, addacSize);
Sujithf1dc5602008-10-29 10:16:30 +05301387
Sujith70807e92010-03-17 14:25:14 +05301388 /* override CLKDRV value at [row, column] = [31, 1] */
Sujith2660b812009-02-09 13:27:26 +05301389 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
Sujithf1dc5602008-10-29 10:16:30 +05301390
Sujith2660b812009-02-09 13:27:26 +05301391 temp.ia_array = ah->addac5416_21;
1392 temp.ia_columns = ah->iniAddac.ia_columns;
1393 temp.ia_rows = ah->iniAddac.ia_rows;
Sujithf1dc5602008-10-29 10:16:30 +05301394 REG_WRITE_ARRAY(&temp, 1, regWrites);
1395 }
1396
1397 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1398
Sujith2660b812009-02-09 13:27:26 +05301399 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1400 u32 reg = INI_RA(&ah->iniModes, i, 0);
1401 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
Sujithf1dc5602008-10-29 10:16:30 +05301402
Pavel Roskin2eb46d92010-04-07 01:33:33 -04001403 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
1404 val &= ~AR_AN_TOP2_PWDCLKIND;
1405
Sujithf1dc5602008-10-29 10:16:30 +05301406 REG_WRITE(ah, reg, val);
1407
1408 if (reg >= 0x7800 && reg < 0x78a0
Sujith2660b812009-02-09 13:27:26 +05301409 && ah->config.analog_shiftreg) {
Sujithf1dc5602008-10-29 10:16:30 +05301410 udelay(100);
1411 }
1412
1413 DO_DELAY(regWrites);
1414 }
1415
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05301416 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
Sujith2660b812009-02-09 13:27:26 +05301417 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
Senthil Balasubramanian9f804202008-11-13 17:58:41 +05301418
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05301419 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1420 AR_SREV_9287_10_OR_LATER(ah))
Sujith2660b812009-02-09 13:27:26 +05301421 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
Senthil Balasubramanian9f804202008-11-13 17:58:41 +05301422
Sujith70807e92010-03-17 14:25:14 +05301423 if (AR_SREV_9271_10(ah))
1424 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1425 modesIndex, regWrites);
1426
1427 /* Write common array parameters */
Sujith2660b812009-02-09 13:27:26 +05301428 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1429 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1430 u32 val = INI_RA(&ah->iniCommon, i, 1);
Sujithf1dc5602008-10-29 10:16:30 +05301431
1432 REG_WRITE(ah, reg, val);
1433
1434 if (reg >= 0x7800 && reg < 0x78a0
Sujith2660b812009-02-09 13:27:26 +05301435 && ah->config.analog_shiftreg) {
Sujithf1dc5602008-10-29 10:16:30 +05301436 udelay(100);
1437 }
1438
1439 DO_DELAY(regWrites);
1440 }
1441
Sujith70807e92010-03-17 14:25:14 +05301442 if (AR_SREV_9271(ah)) {
1443 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1444 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1445 modesIndex, regWrites);
1446 else
1447 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1448 modesIndex, regWrites);
1449 }
Sujithf1dc5602008-10-29 10:16:30 +05301450
Sujith70807e92010-03-17 14:25:14 +05301451 ath9k_hw_write_regs(ah, freqIndex, regWrites);
Luis R. Rodriguez85643282009-10-19 02:33:33 -04001452
Sujithf1dc5602008-10-29 10:16:30 +05301453 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
Sujith2660b812009-02-09 13:27:26 +05301454 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
Sujithf1dc5602008-10-29 10:16:30 +05301455 regWrites);
1456 }
1457
1458 ath9k_hw_override_ini(ah, chan);
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001459 ath9k_hw_set_regs(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301460 ath9k_hw_init_chain_masks(ah);
1461
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +05301462 if (OLC_FOR_AR9280_20_LATER)
1463 ath9k_olc_init(ah);
1464
Sujith70807e92010-03-17 14:25:14 +05301465 /* Set TX power */
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -07001466 ah->eep_ops->set_txpower(ah, chan,
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07001467 ath9k_regd_get_ctl(regulatory, chan),
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -07001468 channel->max_antenna_gain * 2,
1469 channel->max_power * 2,
1470 min((u32) MAX_RATE_POWER,
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07001471 (u32) regulatory->power_limit));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001472
Sujith70807e92010-03-17 14:25:14 +05301473 /* Write analog registers */
Sujithf1dc5602008-10-29 10:16:30 +05301474 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001475 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1476 "ar5416SetRfRegs failed\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001477 return -EIO;
1478 }
1479
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001480 return 0;
1481}
1482
Sujithf1dc5602008-10-29 10:16:30 +05301483/****************************************/
1484/* Reset and Channel Switching Routines */
1485/****************************************/
1486
Sujithcbe61d82009-02-09 13:27:12 +05301487static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05301488{
1489 u32 rfMode = 0;
1490
1491 if (chan == NULL)
1492 return;
1493
1494 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1495 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1496
1497 if (!AR_SREV_9280_10_OR_LATER(ah))
1498 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1499 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1500
1501 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1502 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1503
1504 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1505}
1506
Sujithcbe61d82009-02-09 13:27:12 +05301507static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301508{
1509 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1510}
1511
Sujithcbe61d82009-02-09 13:27:12 +05301512static inline void ath9k_hw_set_dma(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301513{
1514 u32 regval;
1515
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001516 /*
1517 * set AHB_MODE not to do cacheline prefetches
1518 */
Sujithf1dc5602008-10-29 10:16:30 +05301519 regval = REG_READ(ah, AR_AHB_MODE);
1520 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1521
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001522 /*
1523 * let mac dma reads be in 128 byte chunks
1524 */
Sujithf1dc5602008-10-29 10:16:30 +05301525 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1526 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1527
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001528 /*
1529 * Restore TX Trigger Level to its pre-reset value.
1530 * The initial value depends on whether aggregation is enabled, and is
1531 * adjusted whenever underruns are detected.
1532 */
Sujith2660b812009-02-09 13:27:26 +05301533 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
Sujithf1dc5602008-10-29 10:16:30 +05301534
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001535 /*
1536 * let mac dma writes be in 128 byte chunks
1537 */
Sujithf1dc5602008-10-29 10:16:30 +05301538 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1539 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1540
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001541 /*
1542 * Setup receive FIFO threshold to hold off TX activities
1543 */
Sujithf1dc5602008-10-29 10:16:30 +05301544 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1545
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001546 /*
1547 * reduce the number of usable entries in PCU TXBUF to avoid
1548 * wrap around issues.
1549 */
Sujithf1dc5602008-10-29 10:16:30 +05301550 if (AR_SREV_9285(ah)) {
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001551 /* For AR9285 the number of Fifos are reduced to half.
1552 * So set the usable tx buf size also to half to
1553 * avoid data/delimiter underruns
1554 */
Sujithf1dc5602008-10-29 10:16:30 +05301555 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1556 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001557 } else if (!AR_SREV_9271(ah)) {
Sujithf1dc5602008-10-29 10:16:30 +05301558 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1559 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1560 }
1561}
1562
Sujithcbe61d82009-02-09 13:27:12 +05301563static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
Sujithf1dc5602008-10-29 10:16:30 +05301564{
1565 u32 val;
1566
1567 val = REG_READ(ah, AR_STA_ID1);
1568 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1569 switch (opmode) {
Colin McCabed97809d2008-12-01 13:38:55 -08001570 case NL80211_IFTYPE_AP:
Sujithf1dc5602008-10-29 10:16:30 +05301571 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1572 | AR_STA_ID1_KSRCH_MODE);
1573 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1574 break;
Colin McCabed97809d2008-12-01 13:38:55 -08001575 case NL80211_IFTYPE_ADHOC:
Pat Erley9cb54122009-03-20 22:59:59 -04001576 case NL80211_IFTYPE_MESH_POINT:
Sujithf1dc5602008-10-29 10:16:30 +05301577 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1578 | AR_STA_ID1_KSRCH_MODE);
1579 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1580 break;
Colin McCabed97809d2008-12-01 13:38:55 -08001581 case NL80211_IFTYPE_STATION:
1582 case NL80211_IFTYPE_MONITOR:
Sujithf1dc5602008-10-29 10:16:30 +05301583 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1584 break;
1585 }
1586}
1587
Sujithcbe61d82009-02-09 13:27:12 +05301588static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001589 u32 coef_scaled,
1590 u32 *coef_mantissa,
1591 u32 *coef_exponent)
1592{
1593 u32 coef_exp, coef_man;
1594
1595 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1596 if ((coef_scaled >> coef_exp) & 0x1)
1597 break;
1598
1599 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1600
1601 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1602
1603 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1604 *coef_exponent = coef_exp - 16;
1605}
1606
Sujithcbe61d82009-02-09 13:27:12 +05301607static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05301608 struct ath9k_channel *chan)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001609{
1610 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1611 u32 clockMhzScaled = 0x64000000;
1612 struct chan_centers centers;
1613
1614 if (IS_CHAN_HALF_RATE(chan))
1615 clockMhzScaled = clockMhzScaled >> 1;
1616 else if (IS_CHAN_QUARTER_RATE(chan))
1617 clockMhzScaled = clockMhzScaled >> 2;
1618
1619 ath9k_hw_get_channel_centers(ah, chan, &centers);
1620 coef_scaled = clockMhzScaled / centers.synth_center;
1621
1622 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1623 &ds_coef_exp);
1624
1625 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1626 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1627 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1628 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1629
1630 coef_scaled = (9 * coef_scaled) / 10;
1631
1632 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1633 &ds_coef_exp);
1634
1635 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1636 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1637 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1638 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1639}
1640
Sujithcbe61d82009-02-09 13:27:12 +05301641static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
Sujithf1dc5602008-10-29 10:16:30 +05301642{
1643 u32 rst_flags;
1644 u32 tmpReg;
1645
Sujith70768492009-02-16 13:23:12 +05301646 if (AR_SREV_9100(ah)) {
1647 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1648 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1649 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1650 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1651 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1652 }
1653
Sujithf1dc5602008-10-29 10:16:30 +05301654 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1655 AR_RTC_FORCE_WAKE_ON_INT);
1656
1657 if (AR_SREV_9100(ah)) {
1658 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1659 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1660 } else {
1661 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1662 if (tmpReg &
1663 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1664 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1665 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1666 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1667 } else {
1668 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1669 }
1670
1671 rst_flags = AR_RTC_RC_MAC_WARM;
1672 if (type == ATH9K_RESET_COLD)
1673 rst_flags |= AR_RTC_RC_MAC_COLD;
1674 }
1675
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001676 REG_WRITE(ah, AR_RTC_RC, rst_flags);
Sujithf1dc5602008-10-29 10:16:30 +05301677 udelay(50);
1678
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001679 REG_WRITE(ah, AR_RTC_RC, 0);
Sujith0caa7b12009-02-16 13:23:20 +05301680 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001681 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1682 "RTC stuck in MAC reset\n");
Sujithf1dc5602008-10-29 10:16:30 +05301683 return false;
1684 }
1685
1686 if (!AR_SREV_9100(ah))
1687 REG_WRITE(ah, AR_RC, 0);
1688
Sujithf1dc5602008-10-29 10:16:30 +05301689 if (AR_SREV_9100(ah))
1690 udelay(50);
1691
1692 return true;
1693}
1694
Sujithcbe61d82009-02-09 13:27:12 +05301695static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05301696{
1697 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1698 AR_RTC_FORCE_WAKE_ON_INT);
1699
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301700 if (!AR_SREV_9100(ah))
1701 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1702
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001703 REG_WRITE(ah, AR_RTC_RESET, 0);
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +05301704 udelay(2);
Vasanthakumar Thiagarajan1c29ce62009-08-31 17:48:36 +05301705
1706 if (!AR_SREV_9100(ah))
1707 REG_WRITE(ah, AR_RC, 0);
1708
Gabor Juhosd03a66c2009-01-14 20:17:09 +01001709 REG_WRITE(ah, AR_RTC_RESET, 1);
Sujithf1dc5602008-10-29 10:16:30 +05301710
1711 if (!ath9k_hw_wait(ah,
1712 AR_RTC_STATUS,
1713 AR_RTC_STATUS_M,
Sujith0caa7b12009-02-16 13:23:20 +05301714 AR_RTC_STATUS_ON,
1715 AH_WAIT_TIMEOUT)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001716 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1717 "RTC not waking up\n");
Sujithf1dc5602008-10-29 10:16:30 +05301718 return false;
1719 }
1720
1721 ath9k_hw_read_revisions(ah);
1722
1723 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1724}
1725
Sujithcbe61d82009-02-09 13:27:12 +05301726static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
Sujithf1dc5602008-10-29 10:16:30 +05301727{
1728 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1729 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1730
1731 switch (type) {
1732 case ATH9K_RESET_POWER_ON:
1733 return ath9k_hw_set_reset_power_on(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301734 case ATH9K_RESET_WARM:
1735 case ATH9K_RESET_COLD:
1736 return ath9k_hw_set_reset(ah, type);
Sujithf1dc5602008-10-29 10:16:30 +05301737 default:
1738 return false;
1739 }
1740}
1741
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001742static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05301743{
1744 u32 phymode;
Senthil Balasubramaniane7594072008-12-08 19:43:48 +05301745 u32 enableDacFifo = 0;
Sujithf1dc5602008-10-29 10:16:30 +05301746
Senthil Balasubramaniane7594072008-12-08 19:43:48 +05301747 if (AR_SREV_9285_10_OR_LATER(ah))
1748 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1749 AR_PHY_FC_ENABLE_DAC_FIFO);
1750
Sujithf1dc5602008-10-29 10:16:30 +05301751 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
Senthil Balasubramaniane7594072008-12-08 19:43:48 +05301752 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
Sujithf1dc5602008-10-29 10:16:30 +05301753
1754 if (IS_CHAN_HT40(chan)) {
1755 phymode |= AR_PHY_FC_DYN2040_EN;
1756
1757 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1758 (chan->chanmode == CHANNEL_G_HT40PLUS))
1759 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1760
Sujithf1dc5602008-10-29 10:16:30 +05301761 }
1762 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1763
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001764 ath9k_hw_set11nmac2040(ah);
Sujithf1dc5602008-10-29 10:16:30 +05301765
1766 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1767 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1768}
1769
Sujithcbe61d82009-02-09 13:27:12 +05301770static bool ath9k_hw_chip_reset(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05301771 struct ath9k_channel *chan)
1772{
Vivek Natarajan42abfbe2009-09-17 09:27:59 +05301773 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +05301774 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1775 return false;
1776 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
Sujithf1dc5602008-10-29 10:16:30 +05301777 return false;
1778
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001779 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Sujithf1dc5602008-10-29 10:16:30 +05301780 return false;
1781
Sujith2660b812009-02-09 13:27:26 +05301782 ah->chip_fullsleep = false;
Sujithf1dc5602008-10-29 10:16:30 +05301783 ath9k_hw_init_pll(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301784 ath9k_hw_set_rfmode(ah, chan);
1785
1786 return true;
1787}
1788
Sujithcbe61d82009-02-09 13:27:12 +05301789static bool ath9k_hw_channel_change(struct ath_hw *ah,
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001790 struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05301791{
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07001792 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001793 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001794 struct ieee80211_channel *channel = chan->chan;
Sujithf1dc5602008-10-29 10:16:30 +05301795 u32 synthDelay, qnum;
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001796 int r;
Sujithf1dc5602008-10-29 10:16:30 +05301797
1798 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1799 if (ath9k_hw_numtxpending(ah, qnum)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001800 ath_print(common, ATH_DBG_QUEUE,
1801 "Transmit frames pending on "
1802 "queue %d\n", qnum);
Sujithf1dc5602008-10-29 10:16:30 +05301803 return false;
1804 }
1805 }
1806
1807 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1808 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
Sujith0caa7b12009-02-16 13:23:20 +05301809 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001810 ath_print(common, ATH_DBG_FATAL,
1811 "Could not kill baseband RX\n");
Sujithf1dc5602008-10-29 10:16:30 +05301812 return false;
1813 }
1814
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001815 ath9k_hw_set_regs(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301816
Luis R. Rodrigueze68a0602009-10-19 02:33:41 -04001817 r = ah->ath9k_hw_rf_set_freq(ah, chan);
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04001818 if (r) {
1819 ath_print(common, ATH_DBG_FATAL,
1820 "Failed to set channel\n");
1821 return false;
Sujithf1dc5602008-10-29 10:16:30 +05301822 }
1823
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -07001824 ah->eep_ops->set_txpower(ah, chan,
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07001825 ath9k_regd_get_ctl(regulatory, chan),
Sujithf74df6f2009-02-09 13:27:24 +05301826 channel->max_antenna_gain * 2,
1827 channel->max_power * 2,
1828 min((u32) MAX_RATE_POWER,
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07001829 (u32) regulatory->power_limit));
Sujithf1dc5602008-10-29 10:16:30 +05301830
1831 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
Sujith788a3d62008-11-18 09:09:54 +05301832 if (IS_CHAN_B(chan))
Sujithf1dc5602008-10-29 10:16:30 +05301833 synthDelay = (4 * synthDelay) / 22;
1834 else
1835 synthDelay /= 10;
1836
1837 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1838
1839 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1840
1841 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1842 ath9k_hw_set_delta_slope(ah, chan);
1843
Luis R. Rodriguezae478cf2009-10-19 02:33:43 -04001844 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
Sujithf1dc5602008-10-29 10:16:30 +05301845
1846 if (!chan->oneTimeCalsDone)
1847 chan->oneTimeCalsDone = true;
1848
1849 return true;
1850}
1851
Johannes Berg3b319aa2009-06-13 14:50:26 +05301852static void ath9k_enable_rfkill(struct ath_hw *ah)
1853{
1854 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1855 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1856
1857 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1858 AR_GPIO_INPUT_MUX2_RFSILENT);
1859
1860 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1861 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1862}
1863
Sujithcbe61d82009-02-09 13:27:12 +05301864int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001865 bool bChannelChange)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001866{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07001867 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001868 u32 saveLedState;
Sujith2660b812009-02-09 13:27:26 +05301869 struct ath9k_channel *curchan = ah->curchan;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001870 u32 saveDefAntenna;
1871 u32 macStaId1;
Sujith46fe7822009-09-17 09:25:25 +05301872 u64 tsf = 0;
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001873 int i, rx_chainmask, r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001874
Luis R. Rodriguez43c27612009-09-13 21:07:07 -07001875 ah->txchainmask = common->tx_chainmask;
1876 ah->rxchainmask = common->rx_chainmask;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001877
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07001878 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001879 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001880
Vasanthakumar Thiagarajan9ebef792009-09-17 09:26:44 +05301881 if (curchan && !ah->chip_fullsleep)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001882 ath9k_hw_getnf(ah, curchan);
1883
1884 if (bChannelChange &&
Sujith2660b812009-02-09 13:27:26 +05301885 (ah->chip_fullsleep != true) &&
1886 (ah->curchan != NULL) &&
1887 (chan->channel != ah->curchan->channel) &&
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001888 ((chan->channelFlags & CHANNEL_ALL) ==
Sujith2660b812009-02-09 13:27:26 +05301889 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
Vasanthakumar Thiagarajan0a475cc2009-09-17 09:27:10 +05301890 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1891 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001892
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001893 if (ath9k_hw_channel_change(ah, chan)) {
Sujith2660b812009-02-09 13:27:26 +05301894 ath9k_hw_loadnf(ah, ah->curchan);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001895 ath9k_hw_start_nfcal(ah);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001896 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001897 }
1898 }
1899
1900 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1901 if (saveDefAntenna == 0)
1902 saveDefAntenna = 1;
1903
1904 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1905
Sujith46fe7822009-09-17 09:25:25 +05301906 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1907 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1908 tsf = ath9k_hw_gettsf64(ah);
1909
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001910 saveLedState = REG_READ(ah, AR_CFG_LED) &
1911 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1912 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1913
1914 ath9k_hw_mark_phy_inactive(ah);
1915
Sujith05020d22010-03-17 14:25:23 +05301916 /* Only required on the first reset */
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001917 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1918 REG_WRITE(ah,
1919 AR9271_RESET_POWER_DOWN_CONTROL,
1920 AR9271_RADIO_RF_RST);
1921 udelay(50);
1922 }
1923
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001924 if (!ath9k_hw_chip_reset(ah, chan)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001925 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001926 return -EINVAL;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001927 }
1928
Sujith05020d22010-03-17 14:25:23 +05301929 /* Only required on the first reset */
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001930 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1931 ah->htc_reset_init = false;
1932 REG_WRITE(ah,
1933 AR9271_RESET_POWER_DOWN_CONTROL,
1934 AR9271_GATE_MAC_CTL);
1935 udelay(50);
1936 }
1937
Sujith46fe7822009-09-17 09:25:25 +05301938 /* Restore TSF */
1939 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1940 ath9k_hw_settsf64(ah, tsf);
1941
Vasanthakumar Thiagarajan369391d2009-01-21 19:24:13 +05301942 if (AR_SREV_9280_10_OR_LATER(ah))
1943 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001944
Vivek Natarajan326bebb2009-08-14 11:33:36 +05301945 if (AR_SREV_9287_12_OR_LATER(ah)) {
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05301946 /* Enable ASYNC FIFO */
1947 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1948 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1949 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1950 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1951 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1952 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1953 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1954 }
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07001955 r = ath9k_hw_process_ini(ah, chan);
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08001956 if (r)
1957 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001958
Jouni Malinen0ced0e12009-01-08 13:32:13 +02001959 /* Setup MFP options for CCMP */
1960 if (AR_SREV_9280_20_OR_LATER(ah)) {
1961 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1962 * frames when constructing CCMP AAD. */
1963 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1964 0xc7ff);
1965 ah->sw_mgmt_crypto = false;
1966 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1967 /* Disable hardware crypto for management frames */
1968 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1969 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1970 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1971 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1972 ah->sw_mgmt_crypto = true;
1973 } else
1974 ah->sw_mgmt_crypto = true;
1975
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001976 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1977 ath9k_hw_set_delta_slope(ah, chan);
1978
Luis R. Rodriguezae478cf2009-10-19 02:33:43 -04001979 ah->ath9k_hw_spur_mitigate_freq(ah, chan);
Sujithd6509152009-03-13 08:56:05 +05301980 ah->eep_ops->set_board_values(ah, chan);
Luis R. Rodrigueza7765822009-10-19 02:33:45 -04001981
Luis R. Rodriguez15107182009-09-10 09:22:37 -07001982 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1983 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001984 | macStaId1
1985 | AR_STA_ID1_RTS_USE_DEF
Sujith2660b812009-02-09 13:27:26 +05301986 | (ah->config.
Sujith60b67f52008-08-07 10:52:38 +05301987 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
Sujith2660b812009-02-09 13:27:26 +05301988 | ah->sta_id1_defaults);
1989 ath9k_hw_set_operating_mode(ah, ah->opmode);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001990
Luis R. Rodriguez13b81552009-09-10 17:52:45 -07001991 ath_hw_setbssidmask(common);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001992
1993 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1994
Luis R. Rodriguez3453ad82009-09-10 08:57:00 -07001995 ath9k_hw_write_associd(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07001996
1997 REG_WRITE(ah, AR_ISR, ~0);
1998
1999 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2000
Luis R. Rodrigueze68a0602009-10-19 02:33:41 -04002001 r = ah->ath9k_hw_rf_set_freq(ah, chan);
Luis R. Rodriguez0a3b7ba2009-10-19 02:33:40 -04002002 if (r)
2003 return r;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002004
2005 for (i = 0; i < AR_NUM_DCU; i++)
2006 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2007
Sujith2660b812009-02-09 13:27:26 +05302008 ah->intr_txqs = 0;
2009 for (i = 0; i < ah->caps.total_queues; i++)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002010 ath9k_hw_resettxqueue(ah, i);
2011
Sujith2660b812009-02-09 13:27:26 +05302012 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002013 ath9k_hw_init_qos(ah);
2014
Sujith2660b812009-02-09 13:27:26 +05302015 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
Vasanthakumar Thiagarajan500c0642008-09-10 18:50:17 +05302016 ath9k_enable_rfkill(ah);
Johannes Berg3b319aa2009-06-13 14:50:26 +05302017
Felix Fietkau0005baf2010-01-15 02:33:40 +01002018 ath9k_hw_init_global_settings(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002019
Vivek Natarajan326bebb2009-08-14 11:33:36 +05302020 if (AR_SREV_9287_12_OR_LATER(ah)) {
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05302021 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2022 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2023 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2024 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2025 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2026 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2027
2028 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2029 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2030
2031 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2032 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2033 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2034 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2035 }
Vivek Natarajan326bebb2009-08-14 11:33:36 +05302036 if (AR_SREV_9287_12_OR_LATER(ah)) {
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05302037 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2038 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2039 }
2040
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002041 REG_WRITE(ah, AR_STA_ID1,
2042 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2043
2044 ath9k_hw_set_dma(ah);
2045
2046 REG_WRITE(ah, AR_OBS, 8);
2047
Sujith0ce024c2009-12-14 14:57:00 +05302048 if (ah->config.rx_intr_mitigation) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002049 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2050 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2051 }
2052
2053 ath9k_hw_init_bb(ah, chan);
2054
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08002055 if (!ath9k_hw_init_cal(ah, chan))
Joe Perches6badaaf2009-06-28 09:26:32 -07002056 return -EIO;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002057
Sujith2660b812009-02-09 13:27:26 +05302058 rx_chainmask = ah->rxchainmask;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002059 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2060 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2061 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2062 }
2063
2064 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2065
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002066 /*
2067 * For big endian systems turn on swapping for descriptors
2068 */
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002069 if (AR_SREV_9100(ah)) {
2070 u32 mask;
2071 mask = REG_READ(ah, AR_CFG);
2072 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002073 ath_print(common, ATH_DBG_RESET,
Sujith04bd4632008-11-28 22:18:05 +05302074 "CFG Byte Swap Set 0x%x\n", mask);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002075 } else {
2076 mask =
2077 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2078 REG_WRITE(ah, AR_CFG, mask);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002079 ath_print(common, ATH_DBG_RESET,
Sujith04bd4632008-11-28 22:18:05 +05302080 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002081 }
2082 } else {
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002083 /* Configure AR9271 target WLAN */
2084 if (AR_SREV_9271(ah))
2085 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002086#ifdef __BIG_ENDIAN
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04002087 else
2088 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002089#endif
2090 }
2091
Luis R. Rodriguez766ec4a2009-09-09 14:52:02 -07002092 if (ah->btcoex_hw.enabled)
Vasanthakumar Thiagarajan42cc41e2009-08-26 21:08:45 +05302093 ath9k_hw_btcoex_enable(ah);
2094
Luis R. Rodriguezae8d2852008-12-23 15:58:40 -08002095 return 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002096}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002097EXPORT_SYMBOL(ath9k_hw_reset);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002098
Sujithf1dc5602008-10-29 10:16:30 +05302099/************************/
2100/* Key Cache Management */
2101/************************/
2102
Sujithcbe61d82009-02-09 13:27:12 +05302103bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002104{
Sujithf1dc5602008-10-29 10:16:30 +05302105 u32 keyType;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002106
Sujith2660b812009-02-09 13:27:26 +05302107 if (entry >= ah->caps.keycache_size) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002108 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2109 "keychache entry %u out of range\n", entry);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002110 return false;
2111 }
2112
Sujithf1dc5602008-10-29 10:16:30 +05302113 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002114
Sujithf1dc5602008-10-29 10:16:30 +05302115 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2116 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2117 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2118 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2119 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2120 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2121 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2122 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2123
2124 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2125 u16 micentry = entry + 64;
2126
2127 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2128 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2129 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2130 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2131
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002132 }
2133
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002134 return true;
2135}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002136EXPORT_SYMBOL(ath9k_hw_keyreset);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002137
Sujithcbe61d82009-02-09 13:27:12 +05302138bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002139{
Sujithf1dc5602008-10-29 10:16:30 +05302140 u32 macHi, macLo;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002141
Sujith2660b812009-02-09 13:27:26 +05302142 if (entry >= ah->caps.keycache_size) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002143 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2144 "keychache entry %u out of range\n", entry);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002145 return false;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002146 }
2147
Sujithf1dc5602008-10-29 10:16:30 +05302148 if (mac != NULL) {
2149 macHi = (mac[5] << 8) | mac[4];
2150 macLo = (mac[3] << 24) |
2151 (mac[2] << 16) |
2152 (mac[1] << 8) |
2153 mac[0];
2154 macLo >>= 1;
2155 macLo |= (macHi & 1) << 31;
2156 macHi >>= 1;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002157 } else {
Sujithf1dc5602008-10-29 10:16:30 +05302158 macLo = macHi = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002159 }
Sujithf1dc5602008-10-29 10:16:30 +05302160 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2161 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002162
2163 return true;
2164}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002165EXPORT_SYMBOL(ath9k_hw_keysetmac);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002166
Sujithcbe61d82009-02-09 13:27:12 +05302167bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
Sujithf1dc5602008-10-29 10:16:30 +05302168 const struct ath9k_keyval *k,
Jouni Malinene0caf9e2009-03-02 18:15:53 +02002169 const u8 *mac)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002170{
Sujith2660b812009-02-09 13:27:26 +05302171 const struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002172 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +05302173 u32 key0, key1, key2, key3, key4;
2174 u32 keyType;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002175
Sujithf1dc5602008-10-29 10:16:30 +05302176 if (entry >= pCap->keycache_size) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002177 ath_print(common, ATH_DBG_FATAL,
2178 "keycache entry %u out of range\n", entry);
Sujithf1dc5602008-10-29 10:16:30 +05302179 return false;
2180 }
2181
2182 switch (k->kv_type) {
2183 case ATH9K_CIPHER_AES_OCB:
2184 keyType = AR_KEYTABLE_TYPE_AES;
2185 break;
2186 case ATH9K_CIPHER_AES_CCM:
2187 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002188 ath_print(common, ATH_DBG_ANY,
2189 "AES-CCM not supported by mac rev 0x%x\n",
2190 ah->hw_version.macRev);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002191 return false;
2192 }
Sujithf1dc5602008-10-29 10:16:30 +05302193 keyType = AR_KEYTABLE_TYPE_CCM;
2194 break;
2195 case ATH9K_CIPHER_TKIP:
2196 keyType = AR_KEYTABLE_TYPE_TKIP;
2197 if (ATH9K_IS_MIC_ENABLED(ah)
2198 && entry + 64 >= pCap->keycache_size) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002199 ath_print(common, ATH_DBG_ANY,
2200 "entry %u inappropriate for TKIP\n", entry);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002201 return false;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002202 }
Sujithf1dc5602008-10-29 10:16:30 +05302203 break;
2204 case ATH9K_CIPHER_WEP:
Zhu Yie31a16d2009-05-21 21:47:03 +08002205 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002206 ath_print(common, ATH_DBG_ANY,
2207 "WEP key length %u too small\n", k->kv_len);
Sujithf1dc5602008-10-29 10:16:30 +05302208 return false;
2209 }
Zhu Yie31a16d2009-05-21 21:47:03 +08002210 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
Sujithf1dc5602008-10-29 10:16:30 +05302211 keyType = AR_KEYTABLE_TYPE_40;
Zhu Yie31a16d2009-05-21 21:47:03 +08002212 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
Sujithf1dc5602008-10-29 10:16:30 +05302213 keyType = AR_KEYTABLE_TYPE_104;
2214 else
2215 keyType = AR_KEYTABLE_TYPE_128;
2216 break;
2217 case ATH9K_CIPHER_CLR:
2218 keyType = AR_KEYTABLE_TYPE_CLR;
2219 break;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002220 default:
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002221 ath_print(common, ATH_DBG_FATAL,
2222 "cipher %u not supported\n", k->kv_type);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002223 return false;
2224 }
Sujithf1dc5602008-10-29 10:16:30 +05302225
Jouni Malinene0caf9e2009-03-02 18:15:53 +02002226 key0 = get_unaligned_le32(k->kv_val + 0);
2227 key1 = get_unaligned_le16(k->kv_val + 4);
2228 key2 = get_unaligned_le32(k->kv_val + 6);
2229 key3 = get_unaligned_le16(k->kv_val + 10);
2230 key4 = get_unaligned_le32(k->kv_val + 12);
Zhu Yie31a16d2009-05-21 21:47:03 +08002231 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
Sujithf1dc5602008-10-29 10:16:30 +05302232 key4 &= 0xff;
2233
Jouni Malinen672903b2009-03-02 15:06:31 +02002234 /*
2235 * Note: Key cache registers access special memory area that requires
2236 * two 32-bit writes to actually update the values in the internal
2237 * memory. Consequently, the exact order and pairs used here must be
2238 * maintained.
2239 */
2240
Sujithf1dc5602008-10-29 10:16:30 +05302241 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2242 u16 micentry = entry + 64;
2243
Jouni Malinen672903b2009-03-02 15:06:31 +02002244 /*
2245 * Write inverted key[47:0] first to avoid Michael MIC errors
2246 * on frames that could be sent or received at the same time.
2247 * The correct key will be written in the end once everything
2248 * else is ready.
2249 */
Sujithf1dc5602008-10-29 10:16:30 +05302250 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2251 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
Jouni Malinen672903b2009-03-02 15:06:31 +02002252
2253 /* Write key[95:48] */
Sujithf1dc5602008-10-29 10:16:30 +05302254 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2255 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
Jouni Malinen672903b2009-03-02 15:06:31 +02002256
2257 /* Write key[127:96] and key type */
Sujithf1dc5602008-10-29 10:16:30 +05302258 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2259 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
Jouni Malinen672903b2009-03-02 15:06:31 +02002260
2261 /* Write MAC address for the entry */
Sujithf1dc5602008-10-29 10:16:30 +05302262 (void) ath9k_hw_keysetmac(ah, entry, mac);
2263
Sujith2660b812009-02-09 13:27:26 +05302264 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
Jouni Malinen672903b2009-03-02 15:06:31 +02002265 /*
2266 * TKIP uses two key cache entries:
2267 * Michael MIC TX/RX keys in the same key cache entry
2268 * (idx = main index + 64):
2269 * key0 [31:0] = RX key [31:0]
2270 * key1 [15:0] = TX key [31:16]
2271 * key1 [31:16] = reserved
2272 * key2 [31:0] = RX key [63:32]
2273 * key3 [15:0] = TX key [15:0]
2274 * key3 [31:16] = reserved
2275 * key4 [31:0] = TX key [63:32]
2276 */
Sujithf1dc5602008-10-29 10:16:30 +05302277 u32 mic0, mic1, mic2, mic3, mic4;
2278
2279 mic0 = get_unaligned_le32(k->kv_mic + 0);
2280 mic2 = get_unaligned_le32(k->kv_mic + 4);
2281 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2282 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2283 mic4 = get_unaligned_le32(k->kv_txmic + 4);
Jouni Malinen672903b2009-03-02 15:06:31 +02002284
2285 /* Write RX[31:0] and TX[31:16] */
Sujithf1dc5602008-10-29 10:16:30 +05302286 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2287 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
Jouni Malinen672903b2009-03-02 15:06:31 +02002288
2289 /* Write RX[63:32] and TX[15:0] */
Sujithf1dc5602008-10-29 10:16:30 +05302290 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2291 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
Jouni Malinen672903b2009-03-02 15:06:31 +02002292
2293 /* Write TX[63:32] and keyType(reserved) */
Sujithf1dc5602008-10-29 10:16:30 +05302294 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2295 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2296 AR_KEYTABLE_TYPE_CLR);
2297
2298 } else {
Jouni Malinen672903b2009-03-02 15:06:31 +02002299 /*
2300 * TKIP uses four key cache entries (two for group
2301 * keys):
2302 * Michael MIC TX/RX keys are in different key cache
2303 * entries (idx = main index + 64 for TX and
2304 * main index + 32 + 96 for RX):
2305 * key0 [31:0] = TX/RX MIC key [31:0]
2306 * key1 [31:0] = reserved
2307 * key2 [31:0] = TX/RX MIC key [63:32]
2308 * key3 [31:0] = reserved
2309 * key4 [31:0] = reserved
2310 *
2311 * Upper layer code will call this function separately
2312 * for TX and RX keys when these registers offsets are
2313 * used.
2314 */
Sujithf1dc5602008-10-29 10:16:30 +05302315 u32 mic0, mic2;
2316
2317 mic0 = get_unaligned_le32(k->kv_mic + 0);
2318 mic2 = get_unaligned_le32(k->kv_mic + 4);
Jouni Malinen672903b2009-03-02 15:06:31 +02002319
2320 /* Write MIC key[31:0] */
Sujithf1dc5602008-10-29 10:16:30 +05302321 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2322 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
Jouni Malinen672903b2009-03-02 15:06:31 +02002323
2324 /* Write MIC key[63:32] */
Sujithf1dc5602008-10-29 10:16:30 +05302325 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2326 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
Jouni Malinen672903b2009-03-02 15:06:31 +02002327
2328 /* Write TX[63:32] and keyType(reserved) */
Sujithf1dc5602008-10-29 10:16:30 +05302329 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2330 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2331 AR_KEYTABLE_TYPE_CLR);
2332 }
Jouni Malinen672903b2009-03-02 15:06:31 +02002333
2334 /* MAC address registers are reserved for the MIC entry */
Sujithf1dc5602008-10-29 10:16:30 +05302335 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2336 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
Jouni Malinen672903b2009-03-02 15:06:31 +02002337
2338 /*
2339 * Write the correct (un-inverted) key[47:0] last to enable
2340 * TKIP now that all other registers are set with correct
2341 * values.
2342 */
Sujithf1dc5602008-10-29 10:16:30 +05302343 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2344 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2345 } else {
Jouni Malinen672903b2009-03-02 15:06:31 +02002346 /* Write key[47:0] */
Sujithf1dc5602008-10-29 10:16:30 +05302347 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2348 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
Jouni Malinen672903b2009-03-02 15:06:31 +02002349
2350 /* Write key[95:48] */
Sujithf1dc5602008-10-29 10:16:30 +05302351 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2352 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
Jouni Malinen672903b2009-03-02 15:06:31 +02002353
2354 /* Write key[127:96] and key type */
Sujithf1dc5602008-10-29 10:16:30 +05302355 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2356 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2357
Jouni Malinen672903b2009-03-02 15:06:31 +02002358 /* Write MAC address for the entry */
Sujithf1dc5602008-10-29 10:16:30 +05302359 (void) ath9k_hw_keysetmac(ah, entry, mac);
2360 }
2361
Sujithf1dc5602008-10-29 10:16:30 +05302362 return true;
2363}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002364EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
Sujithf1dc5602008-10-29 10:16:30 +05302365
Sujithcbe61d82009-02-09 13:27:12 +05302366bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
Sujithf1dc5602008-10-29 10:16:30 +05302367{
Sujith2660b812009-02-09 13:27:26 +05302368 if (entry < ah->caps.keycache_size) {
Sujithf1dc5602008-10-29 10:16:30 +05302369 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2370 if (val & AR_KEYTABLE_VALID)
2371 return true;
2372 }
2373 return false;
2374}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002375EXPORT_SYMBOL(ath9k_hw_keyisvalid);
Sujithf1dc5602008-10-29 10:16:30 +05302376
2377/******************************/
2378/* Power Management (Chipset) */
2379/******************************/
2380
Sujithcbe61d82009-02-09 13:27:12 +05302381static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
Sujithf1dc5602008-10-29 10:16:30 +05302382{
2383 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2384 if (setChip) {
2385 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2386 AR_RTC_FORCE_WAKE_EN);
2387 if (!AR_SREV_9100(ah))
2388 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2389
Sujith14b3af32010-03-17 14:25:18 +05302390 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
Sujith4921be82009-09-18 15:04:27 +05302391 REG_CLR_BIT(ah, (AR_RTC_RESET),
2392 AR_RTC_RESET_EN);
Sujithf1dc5602008-10-29 10:16:30 +05302393 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002394}
2395
Sujithcbe61d82009-02-09 13:27:12 +05302396static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002397{
Sujithf1dc5602008-10-29 10:16:30 +05302398 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2399 if (setChip) {
Sujith2660b812009-02-09 13:27:26 +05302400 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002401
Sujithf1dc5602008-10-29 10:16:30 +05302402 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2403 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2404 AR_RTC_FORCE_WAKE_ON_INT);
2405 } else {
2406 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2407 AR_RTC_FORCE_WAKE_EN);
2408 }
2409 }
2410}
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002411
Sujithcbe61d82009-02-09 13:27:12 +05302412static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
Sujithf1dc5602008-10-29 10:16:30 +05302413{
2414 u32 val;
2415 int i;
2416
2417 if (setChip) {
2418 if ((REG_READ(ah, AR_RTC_STATUS) &
2419 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2420 if (ath9k_hw_set_reset_reg(ah,
2421 ATH9K_RESET_POWER_ON) != true) {
2422 return false;
2423 }
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05302424 ath9k_hw_init_pll(ah, NULL);
Sujithf1dc5602008-10-29 10:16:30 +05302425 }
2426 if (AR_SREV_9100(ah))
2427 REG_SET_BIT(ah, AR_RTC_RESET,
2428 AR_RTC_RESET_EN);
2429
2430 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2431 AR_RTC_FORCE_WAKE_EN);
2432 udelay(50);
2433
2434 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2435 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2436 if (val == AR_RTC_STATUS_ON)
2437 break;
2438 udelay(50);
2439 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2440 AR_RTC_FORCE_WAKE_EN);
2441 }
2442 if (i == 0) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002443 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2444 "Failed to wakeup in %uus\n",
2445 POWER_UP_TIME / 20);
Sujithf1dc5602008-10-29 10:16:30 +05302446 return false;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002447 }
2448 }
2449
Sujithf1dc5602008-10-29 10:16:30 +05302450 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2451
2452 return true;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002453}
2454
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07002455bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
Sujithf1dc5602008-10-29 10:16:30 +05302456{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002457 struct ath_common *common = ath9k_hw_common(ah);
Sujithcbe61d82009-02-09 13:27:12 +05302458 int status = true, setChip = true;
Sujithf1dc5602008-10-29 10:16:30 +05302459 static const char *modes[] = {
2460 "AWAKE",
2461 "FULL-SLEEP",
2462 "NETWORK SLEEP",
2463 "UNDEFINED"
2464 };
Sujithf1dc5602008-10-29 10:16:30 +05302465
Gabor Juhoscbdec972009-07-24 17:27:22 +02002466 if (ah->power_mode == mode)
2467 return status;
2468
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002469 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2470 modes[ah->power_mode], modes[mode]);
Sujithf1dc5602008-10-29 10:16:30 +05302471
2472 switch (mode) {
2473 case ATH9K_PM_AWAKE:
2474 status = ath9k_hw_set_power_awake(ah, setChip);
2475 break;
2476 case ATH9K_PM_FULL_SLEEP:
2477 ath9k_set_power_sleep(ah, setChip);
Sujith2660b812009-02-09 13:27:26 +05302478 ah->chip_fullsleep = true;
Sujithf1dc5602008-10-29 10:16:30 +05302479 break;
2480 case ATH9K_PM_NETWORK_SLEEP:
2481 ath9k_set_power_network_sleep(ah, setChip);
2482 break;
2483 default:
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002484 ath_print(common, ATH_DBG_FATAL,
2485 "Unknown power mode %u\n", mode);
Sujithf1dc5602008-10-29 10:16:30 +05302486 return false;
2487 }
Sujith2660b812009-02-09 13:27:26 +05302488 ah->power_mode = mode;
Sujithf1dc5602008-10-29 10:16:30 +05302489
2490 return status;
2491}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002492EXPORT_SYMBOL(ath9k_hw_setpower);
Sujithf1dc5602008-10-29 10:16:30 +05302493
Luis R. Rodriguez24c1a282009-02-10 15:35:22 -08002494/*
2495 * Helper for ASPM support.
2496 *
2497 * Disable PLL when in L0s as well as receiver clock when in L1.
2498 * This power saving option must be enabled through the SerDes.
2499 *
2500 * Programming the SerDes must go through the same 288 bit serial shift
2501 * register as the other analog registers. Hence the 9 writes.
2502 */
Vivek Natarajan93b1b372009-09-17 09:24:58 +05302503void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
Sujithf1dc5602008-10-29 10:16:30 +05302504{
Sujithf1dc5602008-10-29 10:16:30 +05302505 u8 i;
Vivek Natarajan93b1b372009-09-17 09:24:58 +05302506 u32 val;
Sujithf1dc5602008-10-29 10:16:30 +05302507
Sujith2660b812009-02-09 13:27:26 +05302508 if (ah->is_pciexpress != true)
Sujithf1dc5602008-10-29 10:16:30 +05302509 return;
2510
Luis R. Rodriguez24c1a282009-02-10 15:35:22 -08002511 /* Do not touch SerDes registers */
Sujith2660b812009-02-09 13:27:26 +05302512 if (ah->config.pcie_powersave_enable == 2)
Sujithf1dc5602008-10-29 10:16:30 +05302513 return;
2514
Luis R. Rodriguez24c1a282009-02-10 15:35:22 -08002515 /* Nothing to do on restore for 11N */
Vivek Natarajan93b1b372009-09-17 09:24:58 +05302516 if (!restore) {
2517 if (AR_SREV_9280_20_OR_LATER(ah)) {
2518 /*
2519 * AR9280 2.0 or later chips use SerDes values from the
2520 * initvals.h initialized depending on chipset during
2521 * ath9k_hw_init()
2522 */
2523 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2524 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2525 INI_RA(&ah->iniPcieSerdes, i, 1));
2526 }
2527 } else if (AR_SREV_9280(ah) &&
2528 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2529 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2530 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
Sujithf1dc5602008-10-29 10:16:30 +05302531
Vivek Natarajan93b1b372009-09-17 09:24:58 +05302532 /* RX shut off when elecidle is asserted */
2533 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2534 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2535 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2536
2537 /* Shut off CLKREQ active in L1 */
2538 if (ah->config.pcie_clock_req)
2539 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2540 else
2541 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2542
2543 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2544 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2545 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2546
2547 /* Load the new settings */
2548 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2549
2550 } else {
2551 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2552 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2553
2554 /* RX shut off when elecidle is asserted */
2555 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2556 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2557 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2558
2559 /*
2560 * Ignore ah->ah_config.pcie_clock_req setting for
2561 * pre-AR9280 11n
2562 */
2563 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2564
2565 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2566 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2567 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2568
2569 /* Load the new settings */
2570 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
Sujithf1dc5602008-10-29 10:16:30 +05302571 }
Sujithf1dc5602008-10-29 10:16:30 +05302572
Vivek Natarajan93b1b372009-09-17 09:24:58 +05302573 udelay(1000);
Sujithf1dc5602008-10-29 10:16:30 +05302574
Vivek Natarajan93b1b372009-09-17 09:24:58 +05302575 /* set bit 19 to allow forcing of pcie core into L1 state */
2576 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
Sujithf1dc5602008-10-29 10:16:30 +05302577
Vivek Natarajan93b1b372009-09-17 09:24:58 +05302578 /* Several PCIe massages to ensure proper behaviour */
2579 if (ah->config.pcie_waen) {
2580 val = ah->config.pcie_waen;
2581 if (!power_off)
2582 val &= (~AR_WA_D3_L1_DISABLE);
2583 } else {
2584 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2585 AR_SREV_9287(ah)) {
2586 val = AR9285_WA_DEFAULT;
2587 if (!power_off)
2588 val &= (~AR_WA_D3_L1_DISABLE);
2589 } else if (AR_SREV_9280(ah)) {
2590 /*
2591 * On AR9280 chips bit 22 of 0x4004 needs to be
2592 * set otherwise card may disappear.
2593 */
2594 val = AR9280_WA_DEFAULT;
2595 if (!power_off)
2596 val &= (~AR_WA_D3_L1_DISABLE);
2597 } else
2598 val = AR_WA_DEFAULT;
2599 }
Sujithf1dc5602008-10-29 10:16:30 +05302600
Vivek Natarajan93b1b372009-09-17 09:24:58 +05302601 REG_WRITE(ah, AR_WA, val);
Sujithf1dc5602008-10-29 10:16:30 +05302602 }
2603
Vivek Natarajan93b1b372009-09-17 09:24:58 +05302604 if (power_off) {
Luis R. Rodriguez24c1a282009-02-10 15:35:22 -08002605 /*
Vivek Natarajan93b1b372009-09-17 09:24:58 +05302606 * Set PCIe workaround bits
2607 * bit 14 in WA register (disable L1) should only
2608 * be set when device enters D3 and be cleared
2609 * when device comes back to D0.
Luis R. Rodriguez24c1a282009-02-10 15:35:22 -08002610 */
Vivek Natarajan93b1b372009-09-17 09:24:58 +05302611 if (ah->config.pcie_waen) {
2612 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2613 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2614 } else {
2615 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2616 AR_SREV_9287(ah)) &&
2617 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2618 (AR_SREV_9280(ah) &&
2619 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2620 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2621 }
2622 }
Sujithf1dc5602008-10-29 10:16:30 +05302623 }
2624}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002625EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
Sujithf1dc5602008-10-29 10:16:30 +05302626
2627/**********************/
2628/* Interrupt Handling */
2629/**********************/
2630
Sujithcbe61d82009-02-09 13:27:12 +05302631bool ath9k_hw_intrpend(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002632{
2633 u32 host_isr;
2634
2635 if (AR_SREV_9100(ah))
2636 return true;
2637
2638 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2639 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2640 return true;
2641
2642 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2643 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2644 && (host_isr != AR_INTR_SPURIOUS))
2645 return true;
2646
2647 return false;
2648}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002649EXPORT_SYMBOL(ath9k_hw_intrpend);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002650
Sujithcbe61d82009-02-09 13:27:12 +05302651bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002652{
2653 u32 isr = 0;
2654 u32 mask2 = 0;
Sujith2660b812009-02-09 13:27:26 +05302655 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002656 u32 sync_cause = 0;
2657 bool fatal_int = false;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002658 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002659
2660 if (!AR_SREV_9100(ah)) {
2661 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2662 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2663 == AR_RTC_STATUS_ON) {
2664 isr = REG_READ(ah, AR_ISR);
2665 }
2666 }
2667
Sujithf1dc5602008-10-29 10:16:30 +05302668 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2669 AR_INTR_SYNC_DEFAULT;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002670
2671 *masked = 0;
2672
2673 if (!isr && !sync_cause)
2674 return false;
2675 } else {
2676 *masked = 0;
2677 isr = REG_READ(ah, AR_ISR);
2678 }
2679
2680 if (isr) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002681 if (isr & AR_ISR_BCNMISC) {
2682 u32 isr2;
2683 isr2 = REG_READ(ah, AR_ISR_S2);
2684 if (isr2 & AR_ISR_S2_TIM)
2685 mask2 |= ATH9K_INT_TIM;
2686 if (isr2 & AR_ISR_S2_DTIM)
2687 mask2 |= ATH9K_INT_DTIM;
2688 if (isr2 & AR_ISR_S2_DTIMSYNC)
2689 mask2 |= ATH9K_INT_DTIMSYNC;
2690 if (isr2 & (AR_ISR_S2_CABEND))
2691 mask2 |= ATH9K_INT_CABEND;
2692 if (isr2 & AR_ISR_S2_GTT)
2693 mask2 |= ATH9K_INT_GTT;
2694 if (isr2 & AR_ISR_S2_CST)
2695 mask2 |= ATH9K_INT_CST;
Sujith4af9cf42009-02-12 10:06:47 +05302696 if (isr2 & AR_ISR_S2_TSFOOR)
2697 mask2 |= ATH9K_INT_TSFOOR;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002698 }
2699
2700 isr = REG_READ(ah, AR_ISR_RAC);
2701 if (isr == 0xffffffff) {
2702 *masked = 0;
2703 return false;
2704 }
2705
2706 *masked = isr & ATH9K_INT_COMMON;
2707
Sujith0ce024c2009-12-14 14:57:00 +05302708 if (ah->config.rx_intr_mitigation) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002709 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2710 *masked |= ATH9K_INT_RX;
2711 }
2712
2713 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2714 *masked |= ATH9K_INT_RX;
2715 if (isr &
2716 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2717 AR_ISR_TXEOL)) {
2718 u32 s0_s, s1_s;
2719
2720 *masked |= ATH9K_INT_TX;
2721
2722 s0_s = REG_READ(ah, AR_ISR_S0_S);
Sujith2660b812009-02-09 13:27:26 +05302723 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2724 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002725
2726 s1_s = REG_READ(ah, AR_ISR_S1_S);
Sujith2660b812009-02-09 13:27:26 +05302727 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2728 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002729 }
2730
2731 if (isr & AR_ISR_RXORN) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002732 ath_print(common, ATH_DBG_INTERRUPT,
2733 "receive FIFO overrun interrupt\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002734 }
2735
2736 if (!AR_SREV_9100(ah)) {
Sujith60b67f52008-08-07 10:52:38 +05302737 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002738 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2739 if (isr5 & AR_ISR_S5_TIM_TIMER)
2740 *masked |= ATH9K_INT_TIM_TIMER;
2741 }
2742 }
2743
2744 *masked |= mask2;
2745 }
Sujithf1dc5602008-10-29 10:16:30 +05302746
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002747 if (AR_SREV_9100(ah))
2748 return true;
Sujithf1dc5602008-10-29 10:16:30 +05302749
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05302750 if (isr & AR_ISR_GENTMR) {
2751 u32 s5_s;
2752
2753 s5_s = REG_READ(ah, AR_ISR_S5_S);
2754 if (isr & AR_ISR_GENTMR) {
2755 ah->intr_gen_timer_trigger =
2756 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2757
2758 ah->intr_gen_timer_thresh =
2759 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2760
2761 if (ah->intr_gen_timer_trigger)
2762 *masked |= ATH9K_INT_GENTIMER;
2763
2764 }
2765 }
2766
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002767 if (sync_cause) {
2768 fatal_int =
2769 (sync_cause &
2770 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2771 ? true : false;
2772
2773 if (fatal_int) {
2774 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002775 ath_print(common, ATH_DBG_ANY,
2776 "received PCI FATAL interrupt\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002777 }
2778 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002779 ath_print(common, ATH_DBG_ANY,
2780 "received PCI PERR interrupt\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002781 }
Steven Luoa89bff92009-04-12 02:57:54 -07002782 *masked |= ATH9K_INT_FATAL;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002783 }
2784 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002785 ath_print(common, ATH_DBG_INTERRUPT,
2786 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002787 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2788 REG_WRITE(ah, AR_RC, 0);
2789 *masked |= ATH9K_INT_FATAL;
2790 }
2791 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002792 ath_print(common, ATH_DBG_INTERRUPT,
2793 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002794 }
2795
2796 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2797 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2798 }
Sujithf1dc5602008-10-29 10:16:30 +05302799
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002800 return true;
2801}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002802EXPORT_SYMBOL(ath9k_hw_getisr);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002803
Sujithcbe61d82009-02-09 13:27:12 +05302804enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002805{
Pavel Roskin152d5302010-03-31 18:05:37 -04002806 enum ath9k_int omask = ah->imask;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002807 u32 mask, mask2;
Sujith2660b812009-02-09 13:27:26 +05302808 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002809 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002810
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002811 ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002812
2813 if (omask & ATH9K_INT_GLOBAL) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002814 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002815 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2816 (void) REG_READ(ah, AR_IER);
2817 if (!AR_SREV_9100(ah)) {
2818 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2819 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2820
2821 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2822 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2823 }
2824 }
2825
2826 mask = ints & ATH9K_INT_COMMON;
2827 mask2 = 0;
2828
2829 if (ints & ATH9K_INT_TX) {
Sujith2660b812009-02-09 13:27:26 +05302830 if (ah->txok_interrupt_mask)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002831 mask |= AR_IMR_TXOK;
Sujith2660b812009-02-09 13:27:26 +05302832 if (ah->txdesc_interrupt_mask)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002833 mask |= AR_IMR_TXDESC;
Sujith2660b812009-02-09 13:27:26 +05302834 if (ah->txerr_interrupt_mask)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002835 mask |= AR_IMR_TXERR;
Sujith2660b812009-02-09 13:27:26 +05302836 if (ah->txeol_interrupt_mask)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002837 mask |= AR_IMR_TXEOL;
2838 }
2839 if (ints & ATH9K_INT_RX) {
2840 mask |= AR_IMR_RXERR;
Sujith0ce024c2009-12-14 14:57:00 +05302841 if (ah->config.rx_intr_mitigation)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002842 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2843 else
2844 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
Sujith60b67f52008-08-07 10:52:38 +05302845 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002846 mask |= AR_IMR_GENTMR;
2847 }
2848
2849 if (ints & (ATH9K_INT_BMISC)) {
2850 mask |= AR_IMR_BCNMISC;
2851 if (ints & ATH9K_INT_TIM)
2852 mask2 |= AR_IMR_S2_TIM;
2853 if (ints & ATH9K_INT_DTIM)
2854 mask2 |= AR_IMR_S2_DTIM;
2855 if (ints & ATH9K_INT_DTIMSYNC)
2856 mask2 |= AR_IMR_S2_DTIMSYNC;
2857 if (ints & ATH9K_INT_CABEND)
Sujith4af9cf42009-02-12 10:06:47 +05302858 mask2 |= AR_IMR_S2_CABEND;
2859 if (ints & ATH9K_INT_TSFOOR)
2860 mask2 |= AR_IMR_S2_TSFOOR;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002861 }
2862
2863 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2864 mask |= AR_IMR_BCNMISC;
2865 if (ints & ATH9K_INT_GTT)
2866 mask2 |= AR_IMR_S2_GTT;
2867 if (ints & ATH9K_INT_CST)
2868 mask2 |= AR_IMR_S2_CST;
2869 }
2870
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002871 ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002872 REG_WRITE(ah, AR_IMR, mask);
Pavel Roskin74bad5c2010-02-23 18:15:27 -05002873 ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2874 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2875 AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2876 ah->imrs2_reg |= mask2;
2877 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002878
Sujith60b67f52008-08-07 10:52:38 +05302879 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002880 if (ints & ATH9K_INT_TIM_TIMER)
2881 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2882 else
2883 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2884 }
2885
2886 if (ints & ATH9K_INT_GLOBAL) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002887 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002888 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2889 if (!AR_SREV_9100(ah)) {
2890 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2891 AR_INTR_MAC_IRQ);
2892 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2893
2894
2895 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2896 AR_INTR_SYNC_DEFAULT);
2897 REG_WRITE(ah, AR_INTR_SYNC_MASK,
2898 AR_INTR_SYNC_DEFAULT);
2899 }
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002900 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2901 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002902 }
2903
2904 return omask;
2905}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002906EXPORT_SYMBOL(ath9k_hw_set_interrupts);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002907
Sujithf1dc5602008-10-29 10:16:30 +05302908/*******************/
2909/* Beacon Handling */
2910/*******************/
2911
Sujithcbe61d82009-02-09 13:27:12 +05302912void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002913{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002914 int flags = 0;
2915
Sujith2660b812009-02-09 13:27:26 +05302916 ah->beacon_interval = beacon_period;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002917
Sujith2660b812009-02-09 13:27:26 +05302918 switch (ah->opmode) {
Colin McCabed97809d2008-12-01 13:38:55 -08002919 case NL80211_IFTYPE_STATION:
2920 case NL80211_IFTYPE_MONITOR:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002921 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2922 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2923 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2924 flags |= AR_TBTT_TIMER_EN;
2925 break;
Colin McCabed97809d2008-12-01 13:38:55 -08002926 case NL80211_IFTYPE_ADHOC:
Pat Erley9cb54122009-03-20 22:59:59 -04002927 case NL80211_IFTYPE_MESH_POINT:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002928 REG_SET_BIT(ah, AR_TXCFG,
2929 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2930 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2931 TU_TO_USEC(next_beacon +
Sujith2660b812009-02-09 13:27:26 +05302932 (ah->atim_window ? ah->
2933 atim_window : 1)));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002934 flags |= AR_NDP_TIMER_EN;
Colin McCabed97809d2008-12-01 13:38:55 -08002935 case NL80211_IFTYPE_AP:
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002936 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2937 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
2938 TU_TO_USEC(next_beacon -
Sujith2660b812009-02-09 13:27:26 +05302939 ah->config.
Sujith60b67f52008-08-07 10:52:38 +05302940 dma_beacon_response_time));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002941 REG_WRITE(ah, AR_NEXT_SWBA,
2942 TU_TO_USEC(next_beacon -
Sujith2660b812009-02-09 13:27:26 +05302943 ah->config.
Sujith60b67f52008-08-07 10:52:38 +05302944 sw_beacon_response_time));
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002945 flags |=
2946 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2947 break;
Colin McCabed97809d2008-12-01 13:38:55 -08002948 default:
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002949 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
2950 "%s: unsupported opmode: %d\n",
2951 __func__, ah->opmode);
Colin McCabed97809d2008-12-01 13:38:55 -08002952 return;
2953 break;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002954 }
2955
2956 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2957 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
2958 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
2959 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
2960
2961 beacon_period &= ~ATH9K_BEACON_ENA;
2962 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002963 ath9k_hw_reset_tsf(ah);
2964 }
2965
2966 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2967}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04002968EXPORT_SYMBOL(ath9k_hw_beaconinit);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002969
Sujithcbe61d82009-02-09 13:27:12 +05302970void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05302971 const struct ath9k_beacon_state *bs)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002972{
2973 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
Sujith2660b812009-02-09 13:27:26 +05302974 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07002975 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07002976
2977 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
2978
2979 REG_WRITE(ah, AR_BEACON_PERIOD,
2980 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2981 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
2982 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
2983
2984 REG_RMW_FIELD(ah, AR_RSSI_THR,
2985 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2986
2987 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
2988
2989 if (bs->bs_sleepduration > beaconintval)
2990 beaconintval = bs->bs_sleepduration;
2991
2992 dtimperiod = bs->bs_dtimperiod;
2993 if (bs->bs_sleepduration > dtimperiod)
2994 dtimperiod = bs->bs_sleepduration;
2995
2996 if (beaconintval == dtimperiod)
2997 nextTbtt = bs->bs_nextdtim;
2998 else
2999 nextTbtt = bs->bs_nexttbtt;
3000
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07003001 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3002 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3003 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3004 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003005
3006 REG_WRITE(ah, AR_NEXT_DTIM,
3007 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3008 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3009
3010 REG_WRITE(ah, AR_SLEEP1,
3011 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3012 | AR_SLEEP1_ASSUME_DTIM);
3013
Sujith60b67f52008-08-07 10:52:38 +05303014 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003015 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3016 else
3017 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3018
3019 REG_WRITE(ah, AR_SLEEP2,
3020 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3021
3022 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3023 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3024
3025 REG_SET_BIT(ah, AR_TIMER_MODE,
3026 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3027 AR_DTIM_TIMER_EN);
3028
Sujith4af9cf42009-02-12 10:06:47 +05303029 /* TSF Out of Range Threshold */
3030 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003031}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003032EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003033
Sujithf1dc5602008-10-29 10:16:30 +05303034/*******************/
3035/* HW Capabilities */
3036/*******************/
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003037
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01003038int ath9k_hw_fill_cap_info(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003039{
Sujith2660b812009-02-09 13:27:26 +05303040 struct ath9k_hw_capabilities *pCap = &ah->caps;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07003041 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07003042 struct ath_common *common = ath9k_hw_common(ah);
Luis R. Rodriguez766ec4a2009-09-09 14:52:02 -07003043 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07003044
Sujithf1dc5602008-10-29 10:16:30 +05303045 u16 capField = 0, eeval;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003046
Sujithf74df6f2009-02-09 13:27:24 +05303047 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07003048 regulatory->current_rd = eeval;
Sujithf1dc5602008-10-29 10:16:30 +05303049
Sujithf74df6f2009-02-09 13:27:24 +05303050 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
Sujithfec0de12009-02-12 10:06:43 +05303051 if (AR_SREV_9285_10_OR_LATER(ah))
3052 eeval |= AR9285_RDEXT_DEFAULT;
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07003053 regulatory->current_rd_ext = eeval;
Sujithf1dc5602008-10-29 10:16:30 +05303054
Sujithf74df6f2009-02-09 13:27:24 +05303055 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
Sujithf1dc5602008-10-29 10:16:30 +05303056
Sujith2660b812009-02-09 13:27:26 +05303057 if (ah->opmode != NL80211_IFTYPE_AP &&
Sujithd535a422009-02-09 13:27:06 +05303058 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07003059 if (regulatory->current_rd == 0x64 ||
3060 regulatory->current_rd == 0x65)
3061 regulatory->current_rd += 5;
3062 else if (regulatory->current_rd == 0x41)
3063 regulatory->current_rd = 0x43;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07003064 ath_print(common, ATH_DBG_REGULATORY,
3065 "regdomain mapped to 0x%x\n", regulatory->current_rd);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003066 }
Sujithdc2222a2008-08-14 13:26:55 +05303067
Sujithf74df6f2009-02-09 13:27:24 +05303068 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01003069 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3070 ath_print(common, ATH_DBG_FATAL,
3071 "no band has been marked as supported in EEPROM.\n");
3072 return -EINVAL;
3073 }
3074
Sujithf1dc5602008-10-29 10:16:30 +05303075 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003076
Sujithf1dc5602008-10-29 10:16:30 +05303077 if (eeval & AR5416_OPFLAGS_11A) {
3078 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
Sujith2660b812009-02-09 13:27:26 +05303079 if (ah->config.ht_enable) {
Sujithf1dc5602008-10-29 10:16:30 +05303080 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3081 set_bit(ATH9K_MODE_11NA_HT20,
3082 pCap->wireless_modes);
3083 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3084 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3085 pCap->wireless_modes);
3086 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3087 pCap->wireless_modes);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003088 }
3089 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003090 }
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003091
Sujithf1dc5602008-10-29 10:16:30 +05303092 if (eeval & AR5416_OPFLAGS_11G) {
Sujithf1dc5602008-10-29 10:16:30 +05303093 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
Sujith2660b812009-02-09 13:27:26 +05303094 if (ah->config.ht_enable) {
Sujithf1dc5602008-10-29 10:16:30 +05303095 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3096 set_bit(ATH9K_MODE_11NG_HT20,
3097 pCap->wireless_modes);
3098 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3099 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3100 pCap->wireless_modes);
3101 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3102 pCap->wireless_modes);
3103 }
3104 }
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07003105 }
Sujithf1dc5602008-10-29 10:16:30 +05303106
Sujithf74df6f2009-02-09 13:27:24 +05303107 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04003108 /*
3109 * For AR9271 we will temporarilly uses the rx chainmax as read from
3110 * the EEPROM.
3111 */
Sujith8147f5d2009-02-20 15:13:23 +05303112 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04003113 !(eeval & AR5416_OPFLAGS_11A) &&
3114 !(AR_SREV_9271(ah)))
3115 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
Sujith8147f5d2009-02-20 15:13:23 +05303116 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3117 else
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04003118 /* Use rx_chainmask from EEPROM. */
Sujith8147f5d2009-02-20 15:13:23 +05303119 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
Sujithf1dc5602008-10-29 10:16:30 +05303120
Sujithd535a422009-02-09 13:27:06 +05303121 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
Sujith2660b812009-02-09 13:27:26 +05303122 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
Sujithf1dc5602008-10-29 10:16:30 +05303123
3124 pCap->low_2ghz_chan = 2312;
3125 pCap->high_2ghz_chan = 2732;
3126
3127 pCap->low_5ghz_chan = 4920;
3128 pCap->high_5ghz_chan = 6100;
3129
3130 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3131 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3132 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3133
3134 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3135 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3136 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3137
Sujith2660b812009-02-09 13:27:26 +05303138 if (ah->config.ht_enable)
Sujithf1dc5602008-10-29 10:16:30 +05303139 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3140 else
3141 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3142
3143 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3144 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3145 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3146 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3147
3148 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3149 pCap->total_queues =
3150 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3151 else
3152 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3153
3154 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3155 pCap->keycache_size =
3156 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3157 else
3158 pCap->keycache_size = AR_KEYTABLE_SIZE;
3159
3160 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -05003161
3162 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3163 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3164 else
3165 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
Sujithf1dc5602008-10-29 10:16:30 +05303166
Sujith5b5fa352010-03-17 14:25:15 +05303167 if (AR_SREV_9271(ah))
3168 pCap->num_gpio_pins = AR9271_NUM_GPIO;
3169 else if (AR_SREV_9285_10_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05303170 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3171 else if (AR_SREV_9280_10_OR_LATER(ah))
Sujithf1dc5602008-10-29 10:16:30 +05303172 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3173 else
3174 pCap->num_gpio_pins = AR_NUM_GPIO;
3175
Sujithf1dc5602008-10-29 10:16:30 +05303176 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3177 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3178 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3179 } else {
3180 pCap->rts_aggr_limit = (8 * 1024);
3181 }
3182
3183 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3184
Senthil Balasubramaniane97275c2008-11-13 18:00:02 +05303185#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
Sujith2660b812009-02-09 13:27:26 +05303186 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3187 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3188 ah->rfkill_gpio =
3189 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3190 ah->rfkill_polarity =
3191 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
Sujithf1dc5602008-10-29 10:16:30 +05303192
3193 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3194 }
3195#endif
Vivek Natarajanbde748a2010-04-05 14:48:05 +05303196 if (AR_SREV_9271(ah))
3197 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3198 else
3199 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
Sujithf1dc5602008-10-29 10:16:30 +05303200
Senthil Balasubramaniane7594072008-12-08 19:43:48 +05303201 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
Sujithf1dc5602008-10-29 10:16:30 +05303202 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3203 else
3204 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3205
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07003206 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
Sujithf1dc5602008-10-29 10:16:30 +05303207 pCap->reg_cap =
3208 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3209 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3210 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3211 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3212 } else {
3213 pCap->reg_cap =
3214 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3215 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3216 }
3217
Senthil Balasubramanianebb90cf2009-09-18 15:07:33 +05303218 /* Advertise midband for AR5416 with FCC midband set in eeprom */
3219 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3220 AR_SREV_5416(ah))
3221 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
Sujithf1dc5602008-10-29 10:16:30 +05303222
3223 pCap->num_antcfg_5ghz =
Sujithf74df6f2009-02-09 13:27:24 +05303224 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
Sujithf1dc5602008-10-29 10:16:30 +05303225 pCap->num_antcfg_2ghz =
Sujithf74df6f2009-02-09 13:27:24 +05303226 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
Sujithf1dc5602008-10-29 10:16:30 +05303227
Vasanthakumar Thiagarajanfe129462009-09-09 15:25:50 +05303228 if (AR_SREV_9280_10_OR_LATER(ah) &&
Luis R. Rodrigueza36cfbc2009-09-09 16:05:32 -07003229 ath9k_hw_btcoex_supported(ah)) {
Luis R. Rodriguez766ec4a2009-09-09 14:52:02 -07003230 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3231 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
Vasanthakumar Thiagarajan22f25d02009-08-26 21:08:47 +05303232
Vasanthakumar Thiagarajan8c8f9ba2009-09-09 15:25:52 +05303233 if (AR_SREV_9285(ah)) {
Luis R. Rodriguez766ec4a2009-09-09 14:52:02 -07003234 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3235 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
Vasanthakumar Thiagarajan8c8f9ba2009-09-09 15:25:52 +05303236 } else {
Luis R. Rodriguez766ec4a2009-09-09 14:52:02 -07003237 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
Vasanthakumar Thiagarajan8c8f9ba2009-09-09 15:25:52 +05303238 }
Vasanthakumar Thiagarajan22f25d02009-08-26 21:08:47 +05303239 } else {
Luis R. Rodriguez766ec4a2009-09-09 14:52:02 -07003240 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
Vasanthakumar Thiagarajanc97c92d2009-01-02 15:35:46 +05303241 }
Gabor Juhosa9a29ce2009-11-27 12:01:35 +01003242
3243 return 0;
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07003244}
3245
Sujithcbe61d82009-02-09 13:27:12 +05303246bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
Sujithf1dc5602008-10-29 10:16:30 +05303247 u32 capability, u32 *result)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003248{
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07003249 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Sujithf1dc5602008-10-29 10:16:30 +05303250 switch (type) {
3251 case ATH9K_CAP_CIPHER:
3252 switch (capability) {
3253 case ATH9K_CIPHER_AES_CCM:
3254 case ATH9K_CIPHER_AES_OCB:
3255 case ATH9K_CIPHER_TKIP:
3256 case ATH9K_CIPHER_WEP:
3257 case ATH9K_CIPHER_MIC:
3258 case ATH9K_CIPHER_CLR:
3259 return true;
3260 default:
3261 return false;
3262 }
3263 case ATH9K_CAP_TKIP_MIC:
3264 switch (capability) {
3265 case 0:
3266 return true;
3267 case 1:
Sujith2660b812009-02-09 13:27:26 +05303268 return (ah->sta_id1_defaults &
Sujithf1dc5602008-10-29 10:16:30 +05303269 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3270 false;
3271 }
3272 case ATH9K_CAP_TKIP_SPLIT:
Sujith2660b812009-02-09 13:27:26 +05303273 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
Sujithf1dc5602008-10-29 10:16:30 +05303274 false : true;
Sujithf1dc5602008-10-29 10:16:30 +05303275 case ATH9K_CAP_DIVERSITY:
3276 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3277 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3278 true : false;
Sujithf1dc5602008-10-29 10:16:30 +05303279 case ATH9K_CAP_MCAST_KEYSRCH:
3280 switch (capability) {
3281 case 0:
3282 return true;
3283 case 1:
3284 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3285 return false;
3286 } else {
Sujith2660b812009-02-09 13:27:26 +05303287 return (ah->sta_id1_defaults &
Sujithf1dc5602008-10-29 10:16:30 +05303288 AR_STA_ID1_MCAST_KSRCH) ? true :
3289 false;
3290 }
3291 }
3292 return false;
Sujithf1dc5602008-10-29 10:16:30 +05303293 case ATH9K_CAP_TXPOW:
3294 switch (capability) {
3295 case 0:
3296 return 0;
3297 case 1:
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07003298 *result = regulatory->power_limit;
Sujithf1dc5602008-10-29 10:16:30 +05303299 return 0;
3300 case 2:
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07003301 *result = regulatory->max_power_level;
Sujithf1dc5602008-10-29 10:16:30 +05303302 return 0;
3303 case 3:
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07003304 *result = regulatory->tp_scale;
Sujithf1dc5602008-10-29 10:16:30 +05303305 return 0;
3306 }
3307 return false;
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +05303308 case ATH9K_CAP_DS:
3309 return (AR_SREV_9280_20_OR_LATER(ah) &&
3310 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3311 ? false : true;
Sujithf1dc5602008-10-29 10:16:30 +05303312 default:
3313 return false;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003314 }
Sujithf1dc5602008-10-29 10:16:30 +05303315}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003316EXPORT_SYMBOL(ath9k_hw_getcapability);
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07003317
Sujithcbe61d82009-02-09 13:27:12 +05303318bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
Sujithf1dc5602008-10-29 10:16:30 +05303319 u32 capability, u32 setting, int *status)
3320{
Sujithf1dc5602008-10-29 10:16:30 +05303321 u32 v;
Luis R. Rodriguez6f255422008-10-03 15:45:27 -07003322
Sujithf1dc5602008-10-29 10:16:30 +05303323 switch (type) {
3324 case ATH9K_CAP_TKIP_MIC:
3325 if (setting)
Sujith2660b812009-02-09 13:27:26 +05303326 ah->sta_id1_defaults |=
Sujithf1dc5602008-10-29 10:16:30 +05303327 AR_STA_ID1_CRPT_MIC_ENABLE;
3328 else
Sujith2660b812009-02-09 13:27:26 +05303329 ah->sta_id1_defaults &=
Sujithf1dc5602008-10-29 10:16:30 +05303330 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3331 return true;
3332 case ATH9K_CAP_DIVERSITY:
3333 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3334 if (setting)
3335 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3336 else
3337 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3338 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3339 return true;
3340 case ATH9K_CAP_MCAST_KEYSRCH:
3341 if (setting)
Sujith2660b812009-02-09 13:27:26 +05303342 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
Sujithf1dc5602008-10-29 10:16:30 +05303343 else
Sujith2660b812009-02-09 13:27:26 +05303344 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
Sujithf1dc5602008-10-29 10:16:30 +05303345 return true;
Sujithf1dc5602008-10-29 10:16:30 +05303346 default:
3347 return false;
3348 }
3349}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003350EXPORT_SYMBOL(ath9k_hw_setcapability);
Sujithf1dc5602008-10-29 10:16:30 +05303351
3352/****************************/
3353/* GPIO / RFKILL / Antennae */
3354/****************************/
3355
Sujithcbe61d82009-02-09 13:27:12 +05303356static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +05303357 u32 gpio, u32 type)
3358{
3359 int addr;
3360 u32 gpio_shift, tmp;
3361
3362 if (gpio > 11)
3363 addr = AR_GPIO_OUTPUT_MUX3;
3364 else if (gpio > 5)
3365 addr = AR_GPIO_OUTPUT_MUX2;
3366 else
3367 addr = AR_GPIO_OUTPUT_MUX1;
3368
3369 gpio_shift = (gpio % 6) * 5;
3370
3371 if (AR_SREV_9280_20_OR_LATER(ah)
3372 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3373 REG_RMW(ah, addr, (type << gpio_shift),
3374 (0x1f << gpio_shift));
3375 } else {
3376 tmp = REG_READ(ah, addr);
3377 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3378 tmp &= ~(0x1f << gpio_shift);
3379 tmp |= (type << gpio_shift);
3380 REG_WRITE(ah, addr, tmp);
3381 }
3382}
3383
Sujithcbe61d82009-02-09 13:27:12 +05303384void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
Sujithf1dc5602008-10-29 10:16:30 +05303385{
3386 u32 gpio_shift;
3387
Luis R. Rodriguez9680e8a2009-09-13 23:28:00 -07003388 BUG_ON(gpio >= ah->caps.num_gpio_pins);
Sujithf1dc5602008-10-29 10:16:30 +05303389
3390 gpio_shift = gpio << 1;
3391
3392 REG_RMW(ah,
3393 AR_GPIO_OE_OUT,
3394 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3395 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3396}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003397EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
Sujithf1dc5602008-10-29 10:16:30 +05303398
Sujithcbe61d82009-02-09 13:27:12 +05303399u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
Sujithf1dc5602008-10-29 10:16:30 +05303400{
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05303401#define MS_REG_READ(x, y) \
3402 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3403
Sujith2660b812009-02-09 13:27:26 +05303404 if (gpio >= ah->caps.num_gpio_pins)
Sujithf1dc5602008-10-29 10:16:30 +05303405 return 0xffffffff;
3406
Sujith5b5fa352010-03-17 14:25:15 +05303407 if (AR_SREV_9271(ah))
3408 return MS_REG_READ(AR9271, gpio) != 0;
3409 else if (AR_SREV_9287_10_OR_LATER(ah))
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05303410 return MS_REG_READ(AR9287, gpio) != 0;
3411 else if (AR_SREV_9285_10_OR_LATER(ah))
Senthil Balasubramaniancb33c412008-12-24 18:03:58 +05303412 return MS_REG_READ(AR9285, gpio) != 0;
3413 else if (AR_SREV_9280_10_OR_LATER(ah))
3414 return MS_REG_READ(AR928X, gpio) != 0;
3415 else
3416 return MS_REG_READ(AR, gpio) != 0;
Sujithf1dc5602008-10-29 10:16:30 +05303417}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003418EXPORT_SYMBOL(ath9k_hw_gpio_get);
Sujithf1dc5602008-10-29 10:16:30 +05303419
Sujithcbe61d82009-02-09 13:27:12 +05303420void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
Sujithf1dc5602008-10-29 10:16:30 +05303421 u32 ah_signal_type)
3422{
3423 u32 gpio_shift;
3424
3425 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3426
3427 gpio_shift = 2 * gpio;
3428
3429 REG_RMW(ah,
3430 AR_GPIO_OE_OUT,
3431 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3432 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3433}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003434EXPORT_SYMBOL(ath9k_hw_cfg_output);
Sujithf1dc5602008-10-29 10:16:30 +05303435
Sujithcbe61d82009-02-09 13:27:12 +05303436void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
Sujithf1dc5602008-10-29 10:16:30 +05303437{
Sujith5b5fa352010-03-17 14:25:15 +05303438 if (AR_SREV_9271(ah))
3439 val = ~val;
3440
Sujithf1dc5602008-10-29 10:16:30 +05303441 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3442 AR_GPIO_BIT(gpio));
3443}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003444EXPORT_SYMBOL(ath9k_hw_set_gpio);
Sujithf1dc5602008-10-29 10:16:30 +05303445
Sujithcbe61d82009-02-09 13:27:12 +05303446u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05303447{
3448 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3449}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003450EXPORT_SYMBOL(ath9k_hw_getdefantenna);
Sujithf1dc5602008-10-29 10:16:30 +05303451
Sujithcbe61d82009-02-09 13:27:12 +05303452void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
Sujithf1dc5602008-10-29 10:16:30 +05303453{
3454 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3455}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003456EXPORT_SYMBOL(ath9k_hw_setantenna);
Sujithf1dc5602008-10-29 10:16:30 +05303457
Sujithf1dc5602008-10-29 10:16:30 +05303458/*********************/
3459/* General Operation */
3460/*********************/
3461
Sujithcbe61d82009-02-09 13:27:12 +05303462u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05303463{
3464 u32 bits = REG_READ(ah, AR_RX_FILTER);
3465 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3466
3467 if (phybits & AR_PHY_ERR_RADAR)
3468 bits |= ATH9K_RX_FILTER_PHYRADAR;
3469 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3470 bits |= ATH9K_RX_FILTER_PHYERR;
3471
3472 return bits;
3473}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003474EXPORT_SYMBOL(ath9k_hw_getrxfilter);
Sujithf1dc5602008-10-29 10:16:30 +05303475
Sujithcbe61d82009-02-09 13:27:12 +05303476void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
Sujithf1dc5602008-10-29 10:16:30 +05303477{
3478 u32 phybits;
3479
Sujith7ea310b2009-09-03 12:08:43 +05303480 REG_WRITE(ah, AR_RX_FILTER, bits);
3481
Sujithf1dc5602008-10-29 10:16:30 +05303482 phybits = 0;
3483 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3484 phybits |= AR_PHY_ERR_RADAR;
3485 if (bits & ATH9K_RX_FILTER_PHYERR)
3486 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3487 REG_WRITE(ah, AR_PHY_ERR, phybits);
3488
3489 if (phybits)
3490 REG_WRITE(ah, AR_RXCFG,
3491 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3492 else
3493 REG_WRITE(ah, AR_RXCFG,
3494 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3495}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003496EXPORT_SYMBOL(ath9k_hw_setrxfilter);
Sujithf1dc5602008-10-29 10:16:30 +05303497
Sujithcbe61d82009-02-09 13:27:12 +05303498bool ath9k_hw_phy_disable(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05303499{
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05303500 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3501 return false;
3502
3503 ath9k_hw_init_pll(ah, NULL);
3504 return true;
Sujithf1dc5602008-10-29 10:16:30 +05303505}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003506EXPORT_SYMBOL(ath9k_hw_phy_disable);
Sujithf1dc5602008-10-29 10:16:30 +05303507
Sujithcbe61d82009-02-09 13:27:12 +05303508bool ath9k_hw_disable(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05303509{
Luis R. Rodriguez9ecdef42009-09-09 21:10:09 -07003510 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
Sujithf1dc5602008-10-29 10:16:30 +05303511 return false;
3512
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +05303513 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3514 return false;
3515
3516 ath9k_hw_init_pll(ah, NULL);
3517 return true;
Sujithf1dc5602008-10-29 10:16:30 +05303518}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003519EXPORT_SYMBOL(ath9k_hw_disable);
Sujithf1dc5602008-10-29 10:16:30 +05303520
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -07003521void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
Sujithf1dc5602008-10-29 10:16:30 +05303522{
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07003523 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Sujith2660b812009-02-09 13:27:26 +05303524 struct ath9k_channel *chan = ah->curchan;
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08003525 struct ieee80211_channel *channel = chan->chan;
Sujithf1dc5602008-10-29 10:16:30 +05303526
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07003527 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
Sujithf1dc5602008-10-29 10:16:30 +05303528
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -07003529 ah->eep_ops->set_txpower(ah, chan,
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07003530 ath9k_regd_get_ctl(regulatory, chan),
Vasanthakumar Thiagarajan8fbff4b2009-05-08 17:54:51 -07003531 channel->max_antenna_gain * 2,
3532 channel->max_power * 2,
3533 min((u32) MAX_RATE_POWER,
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -07003534 (u32) regulatory->power_limit));
Sujithf1dc5602008-10-29 10:16:30 +05303535}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003536EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
Sujithf1dc5602008-10-29 10:16:30 +05303537
Sujithcbe61d82009-02-09 13:27:12 +05303538void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
Sujithf1dc5602008-10-29 10:16:30 +05303539{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07003540 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
Sujithf1dc5602008-10-29 10:16:30 +05303541}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003542EXPORT_SYMBOL(ath9k_hw_setmac);
Sujithf1dc5602008-10-29 10:16:30 +05303543
Sujithcbe61d82009-02-09 13:27:12 +05303544void ath9k_hw_setopmode(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05303545{
Sujith2660b812009-02-09 13:27:26 +05303546 ath9k_hw_set_operating_mode(ah, ah->opmode);
Sujithf1dc5602008-10-29 10:16:30 +05303547}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003548EXPORT_SYMBOL(ath9k_hw_setopmode);
Sujithf1dc5602008-10-29 10:16:30 +05303549
Sujithcbe61d82009-02-09 13:27:12 +05303550void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
Sujithf1dc5602008-10-29 10:16:30 +05303551{
3552 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3553 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3554}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003555EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
Sujithf1dc5602008-10-29 10:16:30 +05303556
Luis R. Rodriguezf2b21432009-09-10 08:50:20 -07003557void ath9k_hw_write_associd(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05303558{
Luis R. Rodriguez15107182009-09-10 09:22:37 -07003559 struct ath_common *common = ath9k_hw_common(ah);
3560
3561 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3562 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3563 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
Sujithf1dc5602008-10-29 10:16:30 +05303564}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003565EXPORT_SYMBOL(ath9k_hw_write_associd);
Sujithf1dc5602008-10-29 10:16:30 +05303566
Sujithcbe61d82009-02-09 13:27:12 +05303567u64 ath9k_hw_gettsf64(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05303568{
3569 u64 tsf;
3570
3571 tsf = REG_READ(ah, AR_TSF_U32);
3572 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3573
3574 return tsf;
3575}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003576EXPORT_SYMBOL(ath9k_hw_gettsf64);
Sujithf1dc5602008-10-29 10:16:30 +05303577
Sujithcbe61d82009-02-09 13:27:12 +05303578void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
Alina Friedrichsen27abe062009-01-23 05:44:21 +01003579{
Alina Friedrichsen27abe062009-01-23 05:44:21 +01003580 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
Alina Friedrichsenb9a16192009-03-02 23:28:38 +01003581 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
Alina Friedrichsen27abe062009-01-23 05:44:21 +01003582}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003583EXPORT_SYMBOL(ath9k_hw_settsf64);
Alina Friedrichsen27abe062009-01-23 05:44:21 +01003584
Sujithcbe61d82009-02-09 13:27:12 +05303585void ath9k_hw_reset_tsf(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +05303586{
Gabor Juhosf9b604f2009-06-21 00:02:15 +02003587 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3588 AH_TSF_WRITE_TIMEOUT))
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07003589 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3590 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
Gabor Juhosf9b604f2009-06-21 00:02:15 +02003591
Sujithf1dc5602008-10-29 10:16:30 +05303592 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003593}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003594EXPORT_SYMBOL(ath9k_hw_reset_tsf);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003595
Sujith54e4cec2009-08-07 09:45:09 +05303596void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003597{
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003598 if (setting)
Sujith2660b812009-02-09 13:27:26 +05303599 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003600 else
Sujith2660b812009-02-09 13:27:26 +05303601 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003602}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003603EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003604
Luis R. Rodriguez30cbd422009-11-03 16:10:46 -08003605/*
3606 * Extend 15-bit time stamp from rx descriptor to
3607 * a full 64-bit TSF using the current h/w TSF.
3608*/
3609u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3610{
3611 u64 tsf;
3612
3613 tsf = ath9k_hw_gettsf64(ah);
3614 if ((tsf & 0x7fff) < rstamp)
3615 tsf -= 0x8000;
3616 return (tsf & ~0x7fff) | rstamp;
3617}
3618EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3619
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07003620void ath9k_hw_set11nmac2040(struct ath_hw *ah)
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003621{
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07003622 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
Sujithf1dc5602008-10-29 10:16:30 +05303623 u32 macmode;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003624
Luis R. Rodriguez25c56ee2009-09-13 23:04:44 -07003625 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
Sujithf1dc5602008-10-29 10:16:30 +05303626 macmode = AR_2040_JOINED_RX_CLEAR;
3627 else
3628 macmode = 0;
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003629
Sujithf1dc5602008-10-29 10:16:30 +05303630 REG_WRITE(ah, AR_2040_MODE, macmode);
Luis R. Rodriguezf078f202008-08-04 00:16:41 -07003631}
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303632
3633/* HW Generic timers configuration */
3634
3635static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3636{
3637 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3638 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3639 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3640 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3641 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3642 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3643 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3644 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3645 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3646 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3647 AR_NDP2_TIMER_MODE, 0x0002},
3648 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3649 AR_NDP2_TIMER_MODE, 0x0004},
3650 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3651 AR_NDP2_TIMER_MODE, 0x0008},
3652 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3653 AR_NDP2_TIMER_MODE, 0x0010},
3654 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3655 AR_NDP2_TIMER_MODE, 0x0020},
3656 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3657 AR_NDP2_TIMER_MODE, 0x0040},
3658 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3659 AR_NDP2_TIMER_MODE, 0x0080}
3660};
3661
3662/* HW generic timer primitives */
3663
3664/* compute and clear index of rightmost 1 */
3665static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3666{
3667 u32 b;
3668
3669 b = *mask;
3670 b &= (0-b);
3671 *mask &= ~b;
3672 b *= debruijn32;
3673 b >>= 27;
3674
3675 return timer_table->gen_timer_index[b];
3676}
3677
Vasanthakumar Thiagarajan17739122009-08-26 21:08:50 +05303678u32 ath9k_hw_gettsf32(struct ath_hw *ah)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303679{
3680 return REG_READ(ah, AR_TSF_L32);
3681}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003682EXPORT_SYMBOL(ath9k_hw_gettsf32);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303683
3684struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3685 void (*trigger)(void *),
3686 void (*overflow)(void *),
3687 void *arg,
3688 u8 timer_index)
3689{
3690 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3691 struct ath_gen_timer *timer;
3692
3693 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3694
3695 if (timer == NULL) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07003696 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3697 "Failed to allocate memory"
3698 "for hw timer[%d]\n", timer_index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303699 return NULL;
3700 }
3701
3702 /* allocate a hardware generic timer slot */
3703 timer_table->timers[timer_index] = timer;
3704 timer->index = timer_index;
3705 timer->trigger = trigger;
3706 timer->overflow = overflow;
3707 timer->arg = arg;
3708
3709 return timer;
3710}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003711EXPORT_SYMBOL(ath_gen_timer_alloc);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303712
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07003713void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3714 struct ath_gen_timer *timer,
3715 u32 timer_next,
3716 u32 timer_period)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303717{
3718 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3719 u32 tsf;
3720
3721 BUG_ON(!timer_period);
3722
3723 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3724
3725 tsf = ath9k_hw_gettsf32(ah);
3726
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07003727 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3728 "curent tsf %x period %x"
3729 "timer_next %x\n", tsf, timer_period, timer_next);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303730
3731 /*
3732 * Pull timer_next forward if the current TSF already passed it
3733 * because of software latency
3734 */
3735 if (timer_next < tsf)
3736 timer_next = tsf + timer_period;
3737
3738 /*
3739 * Program generic timer registers
3740 */
3741 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3742 timer_next);
3743 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3744 timer_period);
3745 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3746 gen_tmr_configuration[timer->index].mode_mask);
3747
3748 /* Enable both trigger and thresh interrupt masks */
3749 REG_SET_BIT(ah, AR_IMR_S5,
3750 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3751 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303752}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003753EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303754
Luis R. Rodriguezcd9bf682009-09-13 02:08:34 -07003755void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303756{
3757 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3758
3759 if ((timer->index < AR_FIRST_NDP_TIMER) ||
3760 (timer->index >= ATH_MAX_GEN_TIMER)) {
3761 return;
3762 }
3763
3764 /* Clear generic timer enable bits. */
3765 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3766 gen_tmr_configuration[timer->index].mode_mask);
3767
3768 /* Disable both trigger and thresh interrupt masks */
3769 REG_CLR_BIT(ah, AR_IMR_S5,
3770 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3771 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3772
3773 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303774}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003775EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303776
3777void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3778{
3779 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3780
3781 /* free the hardware generic timer slot */
3782 timer_table->timers[timer->index] = NULL;
3783 kfree(timer);
3784}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003785EXPORT_SYMBOL(ath_gen_timer_free);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303786
3787/*
3788 * Generic Timer Interrupts handling
3789 */
3790void ath_gen_timer_isr(struct ath_hw *ah)
3791{
3792 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3793 struct ath_gen_timer *timer;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07003794 struct ath_common *common = ath9k_hw_common(ah);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303795 u32 trigger_mask, thresh_mask, index;
3796
3797 /* get hardware generic timer interrupt status */
3798 trigger_mask = ah->intr_gen_timer_trigger;
3799 thresh_mask = ah->intr_gen_timer_thresh;
3800 trigger_mask &= timer_table->timer_mask.val;
3801 thresh_mask &= timer_table->timer_mask.val;
3802
3803 trigger_mask &= ~thresh_mask;
3804
3805 while (thresh_mask) {
3806 index = rightmost_index(timer_table, &thresh_mask);
3807 timer = timer_table->timers[index];
3808 BUG_ON(!timer);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07003809 ath_print(common, ATH_DBG_HWTIMER,
3810 "TSF overflow for Gen timer %d\n", index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303811 timer->overflow(timer->arg);
3812 }
3813
3814 while (trigger_mask) {
3815 index = rightmost_index(timer_table, &trigger_mask);
3816 timer = timer_table->timers[index];
3817 BUG_ON(!timer);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07003818 ath_print(common, ATH_DBG_HWTIMER,
3819 "Gen timer[%d] trigger\n", index);
Vasanthakumar Thiagarajanff155a42009-08-26 21:08:49 +05303820 timer->trigger(timer->arg);
3821 }
3822}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04003823EXPORT_SYMBOL(ath_gen_timer_isr);
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003824
Sujith05020d22010-03-17 14:25:23 +05303825/********/
3826/* HTC */
3827/********/
3828
3829void ath9k_hw_htc_resetinit(struct ath_hw *ah)
3830{
3831 ah->htc_reset_init = true;
3832}
3833EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
3834
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003835static struct {
3836 u32 version;
3837 const char * name;
3838} ath_mac_bb_names[] = {
3839 /* Devices with external radios */
3840 { AR_SREV_VERSION_5416_PCI, "5416" },
3841 { AR_SREV_VERSION_5416_PCIE, "5418" },
3842 { AR_SREV_VERSION_9100, "9100" },
3843 { AR_SREV_VERSION_9160, "9160" },
3844 /* Single-chip solutions */
3845 { AR_SREV_VERSION_9280, "9280" },
3846 { AR_SREV_VERSION_9285, "9285" },
Luis R. Rodriguez11158472009-10-27 12:59:35 -04003847 { AR_SREV_VERSION_9287, "9287" },
3848 { AR_SREV_VERSION_9271, "9271" },
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003849};
3850
3851/* For devices with external radios */
3852static struct {
3853 u16 version;
3854 const char * name;
3855} ath_rf_names[] = {
3856 { 0, "5133" },
3857 { AR_RAD5133_SREV_MAJOR, "5133" },
3858 { AR_RAD5122_SREV_MAJOR, "5122" },
3859 { AR_RAD2133_SREV_MAJOR, "2133" },
3860 { AR_RAD2122_SREV_MAJOR, "2122" }
3861};
3862
3863/*
3864 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3865 */
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003866static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003867{
3868 int i;
3869
3870 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3871 if (ath_mac_bb_names[i].version == mac_bb_version) {
3872 return ath_mac_bb_names[i].name;
3873 }
3874 }
3875
3876 return "????";
3877}
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003878
3879/*
3880 * Return the RF name. "????" is returned if the RF is unknown.
3881 * Used for devices with external radios.
3882 */
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003883static const char *ath9k_hw_rf_name(u16 rf_version)
Luis R. Rodriguez2da4f012009-10-27 12:59:33 -04003884{
3885 int i;
3886
3887 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3888 if (ath_rf_names[i].version == rf_version) {
3889 return ath_rf_names[i].name;
3890 }
3891 }
3892
3893 return "????";
3894}
Luis R. Rodriguezf934c4d2009-10-27 12:59:34 -04003895
3896void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3897{
3898 int used;
3899
3900 /* chipsets >= AR9280 are single-chip */
3901 if (AR_SREV_9280_10_OR_LATER(ah)) {
3902 used = snprintf(hw_name, len,
3903 "Atheros AR%s Rev:%x",
3904 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3905 ah->hw_version.macRev);
3906 }
3907 else {
3908 used = snprintf(hw_name, len,
3909 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3910 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3911 ah->hw_version.macRev,
3912 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3913 AR_RADIO_SREV_MAJOR)),
3914 ah->hw_version.phyRev);
3915 }
3916
3917 hw_name[used] = '\0';
3918}
3919EXPORT_SYMBOL(ath9k_hw_name);