Patrick Daly | 20eb696 | 2014-01-17 15:22:16 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/err.h> |
| 16 | #include <linux/ctype.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/spinlock.h> |
| 19 | #include <linux/delay.h> |
| 20 | #include <linux/clk.h> |
| 21 | #include <linux/iopoll.h> |
Patrick Daly | 48e00f3 | 2013-01-28 19:13:47 -0800 | [diff] [blame] | 22 | #include <linux/regulator/consumer.h> |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 23 | |
| 24 | #include <mach/rpm-regulator-smd.h> |
| 25 | #include <mach/socinfo.h> |
| 26 | #include <mach/rpm-smd.h> |
Aravind Venkateswaran | 78b7325 | 2013-05-08 18:25:21 -0700 | [diff] [blame] | 27 | #include <mach/clock-generic.h> |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 28 | |
| 29 | #include "clock-local2.h" |
| 30 | #include "clock-pll.h" |
| 31 | #include "clock-rpm.h" |
| 32 | #include "clock-voter.h" |
| 33 | #include "clock-mdss-8974.h" |
| 34 | #include "clock.h" |
| 35 | |
| 36 | enum { |
| 37 | GCC_BASE, |
| 38 | MMSS_BASE, |
| 39 | LPASS_BASE, |
| 40 | APCS_BASE, |
| 41 | APCS_PLL_BASE, |
| 42 | N_BASES, |
| 43 | }; |
| 44 | |
| 45 | static void __iomem *virt_bases[N_BASES]; |
| 46 | |
| 47 | #define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x)) |
| 48 | #define MMSS_REG_BASE(x) (void __iomem *)(virt_bases[MMSS_BASE] + (x)) |
| 49 | #define LPASS_REG_BASE(x) (void __iomem *)(virt_bases[LPASS_BASE] + (x)) |
| 50 | #define APCS_REG_BASE(x) (void __iomem *)(virt_bases[APCS_BASE] + (x)) |
| 51 | |
| 52 | /* Mux source select values */ |
| 53 | #define xo_source_val 0 |
Patrick Daly | 01d4c1d | 2013-05-22 19:10:55 -0700 | [diff] [blame] | 54 | #define xo_a_clk_source_val 0 |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 55 | #define gpll0_source_val 1 |
| 56 | #define gpll1_source_val 2 |
| 57 | |
| 58 | #define xo_mm_source_val 0 |
| 59 | #define mmpll0_pll_mm_source_val 1 |
| 60 | #define mmpll1_pll_mm_source_val 2 |
| 61 | #define mmpll2_pll_mm_source_val 3 |
| 62 | #define gpll0_mm_source_val 5 |
| 63 | #define dsipll_750_mm_source_val 1 |
| 64 | #define dsipll_667_mm_source_val 1 |
Patrick Daly | 5555c2c | 2013-03-06 21:25:26 -0800 | [diff] [blame] | 65 | #define dsipll0_byte_mm_source_val 1 |
| 66 | #define dsipll0_pixel_mm_source_val 1 |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 67 | |
| 68 | #define gpll1_hsic_source_val 4 |
| 69 | |
| 70 | #define xo_lpass_source_val 0 |
| 71 | #define lpaaudio_pll_lpass_source_val 1 |
| 72 | #define gpll0_lpass_source_val 5 |
| 73 | |
| 74 | /* Prevent a divider of -1 */ |
| 75 | #define FIXDIV(div) (div ? (2 * (div) - 1) : (0)) |
| 76 | |
| 77 | #define F_GCC(f, s, div, m, n) \ |
| 78 | { \ |
| 79 | .freq_hz = (f), \ |
| 80 | .src_clk = &s.c, \ |
| 81 | .m_val = (m), \ |
| 82 | .n_val = ~((n)-(m)) * !!(n), \ |
| 83 | .d_val = ~(n),\ |
| 84 | .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \ |
| 85 | | BVAL(10, 8, s##_source_val), \ |
| 86 | } |
| 87 | |
| 88 | #define F_MMSS(f, s, div, m, n) \ |
| 89 | { \ |
| 90 | .freq_hz = (f), \ |
| 91 | .src_clk = &s.c, \ |
| 92 | .m_val = (m), \ |
| 93 | .n_val = ~((n)-(m)) * !!(n), \ |
| 94 | .d_val = ~(n),\ |
| 95 | .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \ |
| 96 | | BVAL(10, 8, s##_mm_source_val), \ |
| 97 | } |
| 98 | |
| 99 | #define F_MDSS(f, s, div, m, n) \ |
| 100 | { \ |
| 101 | .freq_hz = (f), \ |
| 102 | .m_val = (m), \ |
| 103 | .n_val = ~((n)-(m)) * !!(n), \ |
| 104 | .d_val = ~(n),\ |
| 105 | .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \ |
| 106 | | BVAL(10, 8, s##_mm_source_val), \ |
| 107 | } |
| 108 | |
| 109 | #define F_HSIC(f, s, div, m, n) \ |
| 110 | { \ |
| 111 | .freq_hz = (f), \ |
| 112 | .src_clk = &s.c, \ |
| 113 | .m_val = (m), \ |
| 114 | .n_val = ~((n)-(m)) * !!(n), \ |
| 115 | .d_val = ~(n),\ |
| 116 | .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \ |
| 117 | | BVAL(10, 8, s##_hsic_source_val), \ |
| 118 | } |
| 119 | |
| 120 | #define F_LPASS(f, s, div, m, n) \ |
| 121 | { \ |
| 122 | .freq_hz = (f), \ |
| 123 | .src_clk = &s.c, \ |
| 124 | .m_val = (m), \ |
| 125 | .n_val = ~((n)-(m)) * !!(n), \ |
| 126 | .d_val = ~(n),\ |
| 127 | .div_src_val = BVAL(4, 0, (int)(FIXDIV(div))) \ |
| 128 | | BVAL(10, 8, s##_lpass_source_val), \ |
| 129 | } |
| 130 | |
| 131 | #define F_APCS_PLL(f, l, m, n, pre_div, post_div, vco) \ |
| 132 | { \ |
| 133 | .freq_hz = (f), \ |
| 134 | .l_val = (l), \ |
| 135 | .m_val = (m), \ |
| 136 | .n_val = (n), \ |
| 137 | .pre_div_val = BVAL(12, 12, (pre_div)), \ |
| 138 | .post_div_val = BVAL(9, 8, (post_div)), \ |
| 139 | .vco_val = BVAL(29, 28, (vco)), \ |
| 140 | } |
| 141 | |
| 142 | #define VDD_DIG_FMAX_MAP1(l1, f1) \ |
| 143 | .vdd_class = &vdd_dig, \ |
| 144 | .fmax = (unsigned long[VDD_DIG_NUM]) { \ |
| 145 | [VDD_DIG_##l1] = (f1), \ |
| 146 | }, \ |
| 147 | .num_fmax = VDD_DIG_NUM |
| 148 | |
| 149 | #define VDD_DIG_FMAX_MAP2(l1, f1, l2, f2) \ |
| 150 | .vdd_class = &vdd_dig, \ |
| 151 | .fmax = (unsigned long[VDD_DIG_NUM]) { \ |
| 152 | [VDD_DIG_##l1] = (f1), \ |
| 153 | [VDD_DIG_##l2] = (f2), \ |
| 154 | }, \ |
| 155 | .num_fmax = VDD_DIG_NUM |
| 156 | |
| 157 | #define VDD_DIG_FMAX_MAP3(l1, f1, l2, f2, l3, f3) \ |
| 158 | .vdd_class = &vdd_dig, \ |
| 159 | .fmax = (unsigned long[VDD_DIG_NUM]) { \ |
| 160 | [VDD_DIG_##l1] = (f1), \ |
| 161 | [VDD_DIG_##l2] = (f2), \ |
| 162 | [VDD_DIG_##l3] = (f3), \ |
| 163 | }, \ |
| 164 | .num_fmax = VDD_DIG_NUM |
| 165 | |
| 166 | enum vdd_dig_levels { |
| 167 | VDD_DIG_NONE, |
| 168 | VDD_DIG_LOW, |
| 169 | VDD_DIG_NOMINAL, |
| 170 | VDD_DIG_HIGH, |
| 171 | VDD_DIG_NUM |
| 172 | }; |
| 173 | |
Junjie Wu | bb5a79e | 2013-05-15 13:12:39 -0700 | [diff] [blame] | 174 | static int vdd_corner[] = { |
| 175 | RPM_REGULATOR_CORNER_NONE, /* VDD_DIG_NONE */ |
| 176 | RPM_REGULATOR_CORNER_SVS_SOC, /* VDD_DIG_LOW */ |
| 177 | RPM_REGULATOR_CORNER_NORMAL, /* VDD_DIG_NOMINAL */ |
| 178 | RPM_REGULATOR_CORNER_SUPER_TURBO, /* VDD_DIG_HIGH */ |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 179 | }; |
| 180 | |
Patrick Daly | 653c0b5 | 2013-04-16 17:18:28 -0700 | [diff] [blame] | 181 | static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL); |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 182 | |
| 183 | #define RPM_MISC_CLK_TYPE 0x306b6c63 |
| 184 | #define RPM_BUS_CLK_TYPE 0x316b6c63 |
| 185 | #define RPM_MEM_CLK_TYPE 0x326b6c63 |
| 186 | |
| 187 | #define RPM_SMD_KEY_ENABLE 0x62616E45 |
| 188 | |
| 189 | #define CXO_ID 0x0 |
| 190 | #define QDSS_ID 0x1 |
| 191 | |
| 192 | #define PNOC_ID 0x0 |
| 193 | #define SNOC_ID 0x1 |
| 194 | #define CNOC_ID 0x2 |
| 195 | #define MMSSNOC_AHB_ID 0x3 |
| 196 | |
| 197 | #define BIMC_ID 0x0 |
| 198 | #define OXILI_ID 0x1 |
| 199 | #define OCMEM_ID 0x2 |
| 200 | |
| 201 | #define D0_ID 1 |
| 202 | #define D1_ID 2 |
| 203 | #define A0_ID 4 |
| 204 | #define A1_ID 5 |
| 205 | #define A2_ID 6 |
| 206 | #define DIFF_CLK_ID 7 |
| 207 | #define DIV_CLK1_ID 11 |
| 208 | #define DIV_CLK2_ID 12 |
| 209 | |
| 210 | DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_ID, NULL); |
| 211 | DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_ID, NULL); |
| 212 | DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_ID, NULL); |
| 213 | DEFINE_CLK_RPM_SMD(mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, RPM_BUS_CLK_TYPE, |
| 214 | MMSSNOC_AHB_ID, NULL); |
| 215 | |
| 216 | DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_ID, NULL); |
| 217 | DEFINE_CLK_RPM_SMD(ocmemgx_clk, ocmemgx_a_clk, RPM_MEM_CLK_TYPE, OCMEM_ID, |
| 218 | NULL); |
| 219 | DEFINE_CLK_RPM_SMD(gfx3d_clk_src, gfx3d_a_clk_src, RPM_MEM_CLK_TYPE, OXILI_ID, |
| 220 | NULL); |
| 221 | |
| 222 | DEFINE_CLK_RPM_SMD_BRANCH(xo, xo_a_clk, |
| 223 | RPM_MISC_CLK_TYPE, CXO_ID, 19200000); |
| 224 | DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_ID); |
| 225 | |
| 226 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d0, cxo_d0_a, D0_ID); |
| 227 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_d1, cxo_d1_a, D1_ID); |
| 228 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a0, cxo_a0_a, A0_ID); |
| 229 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a1, cxo_a1_a, A1_ID); |
| 230 | DEFINE_CLK_RPM_SMD_XO_BUFFER(cxo_a2, cxo_a2_a, A2_ID); |
| 231 | DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk1, div_a_clk1, DIV_CLK1_ID); |
| 232 | DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_a_clk2, DIV_CLK2_ID); |
| 233 | DEFINE_CLK_RPM_SMD_XO_BUFFER(diff_clk, diff_a_clk, DIFF_CLK_ID); |
| 234 | |
| 235 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d0_pin, cxo_d0_a_pin, D0_ID); |
| 236 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_d1_pin, cxo_d1_a_pin, D1_ID); |
| 237 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a0_pin, cxo_a0_a_pin, A0_ID); |
| 238 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a1_pin, cxo_a1_a_pin, A1_ID); |
| 239 | DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(cxo_a2_pin, cxo_a2_a_pin, A2_ID); |
| 240 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 241 | static struct branch_clk oxilicx_axi_clk; |
| 242 | |
| 243 | #define MSS_DEBUG_CLOCK_CTL 0x0078 |
| 244 | #define LPASS_DEBUG_CLK_CTL 0x29000 |
| 245 | #define GLB_CLK_DIAG 0x01C |
| 246 | #define GLB_TEST_BUS_SEL 0x020 |
| 247 | |
| 248 | #define MMPLL0_PLL_MODE (0x0000) |
| 249 | #define MMPLL0_PLL_L_VAL (0x0004) |
| 250 | #define MMPLL0_PLL_M_VAL (0x0008) |
| 251 | #define MMPLL0_PLL_N_VAL (0x000C) |
| 252 | #define MMPLL0_PLL_USER_CTL (0x0010) |
| 253 | #define MMPLL0_PLL_STATUS (0x001C) |
| 254 | #define MMPLL1_PLL_MODE (0x0040) |
| 255 | #define MMPLL1_PLL_L_VAL (0x0044) |
| 256 | #define MMPLL1_PLL_M_VAL (0x0048) |
| 257 | #define MMPLL1_PLL_N_VAL (0x004C) |
| 258 | #define MMPLL1_PLL_USER_CTL (0x0050) |
| 259 | #define MMPLL1_PLL_STATUS (0x005C) |
| 260 | #define MMSS_PLL_VOTE_APCS (0x0100) |
| 261 | #define VCODEC0_CMD_RCGR (0x1000) |
Matt Wagantall | 57b7456 | 2013-07-03 19:24:53 -0700 | [diff] [blame] | 262 | #define VENUS0_BCR (0x1020) |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 263 | #define VENUS0_VCODEC0_CBCR (0x1028) |
| 264 | #define VENUS0_AHB_CBCR (0x1030) |
| 265 | #define VENUS0_AXI_CBCR (0x1034) |
| 266 | #define PCLK0_CMD_RCGR (0x2000) |
| 267 | #define MDP_CMD_RCGR (0x2040) |
| 268 | #define VSYNC_CMD_RCGR (0x2080) |
| 269 | #define BYTE0_CMD_RCGR (0x2120) |
| 270 | #define ESC0_CMD_RCGR (0x2160) |
| 271 | #define MDSS_AHB_CBCR (0x2308) |
Matt Wagantall | 57b7456 | 2013-07-03 19:24:53 -0700 | [diff] [blame] | 272 | #define MDSS_BCR (0x2300) |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 273 | #define MDSS_AXI_CBCR (0x2310) |
| 274 | #define MDSS_PCLK0_CBCR (0x2314) |
| 275 | #define MDSS_MDP_CBCR (0x231C) |
| 276 | #define MDSS_MDP_LUT_CBCR (0x2320) |
| 277 | #define MDSS_VSYNC_CBCR (0x2328) |
| 278 | #define MDSS_BYTE0_CBCR (0x233C) |
| 279 | #define MDSS_ESC0_CBCR (0x2344) |
| 280 | #define CSI0PHYTIMER_CMD_RCGR (0x3000) |
| 281 | #define CAMSS_PHY0_CSI0PHYTIMER_CBCR (0x3024) |
| 282 | #define CSI1PHYTIMER_CMD_RCGR (0x3030) |
| 283 | #define CAMSS_PHY1_CSI1PHYTIMER_CBCR (0x3054) |
| 284 | #define CSI0_CMD_RCGR (0x3090) |
| 285 | #define CAMSS_CSI0_CBCR (0x30B4) |
| 286 | #define CAMSS_CSI0_AHB_CBCR (0x30BC) |
| 287 | #define CAMSS_CSI0PHY_CBCR (0x30C4) |
| 288 | #define CAMSS_CSI0RDI_CBCR (0x30D4) |
| 289 | #define CAMSS_CSI0PIX_CBCR (0x30E4) |
| 290 | #define CSI1_CMD_RCGR (0x3100) |
| 291 | #define CAMSS_CSI1_CBCR (0x3124) |
| 292 | #define CAMSS_CSI1_AHB_CBCR (0x3128) |
| 293 | #define CAMSS_CSI1PHY_CBCR (0x3134) |
| 294 | #define CAMSS_CSI1RDI_CBCR (0x3144) |
| 295 | #define CAMSS_CSI1PIX_CBCR (0x3154) |
| 296 | #define CAMSS_ISPIF_AHB_CBCR (0x3224) |
| 297 | #define CCI_CMD_RCGR (0x3300) |
| 298 | #define CAMSS_CCI_CCI_CBCR (0x3344) |
| 299 | #define CAMSS_CCI_CCI_AHB_CBCR (0x3348) |
| 300 | #define MCLK0_CMD_RCGR (0x3360) |
| 301 | #define CAMSS_MCLK0_CBCR (0x3384) |
| 302 | #define MCLK1_CMD_RCGR (0x3390) |
| 303 | #define CAMSS_MCLK1_CBCR (0x33B4) |
| 304 | #define MMSS_GP0_CMD_RCGR (0x3420) |
| 305 | #define CAMSS_GP0_CBCR (0x3444) |
| 306 | #define MMSS_GP1_CMD_RCGR (0x3450) |
| 307 | #define CAMSS_GP1_CBCR (0x3474) |
| 308 | #define CAMSS_TOP_AHB_CBCR (0x3484) |
| 309 | #define CAMSS_MICRO_AHB_CBCR (0x3494) |
| 310 | #define JPEG0_CMD_RCGR (0x3500) |
Matt Wagantall | 57b7456 | 2013-07-03 19:24:53 -0700 | [diff] [blame] | 311 | #define CAMSS_JPEG_BCR (0x35A0) |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 312 | #define CAMSS_JPEG_JPEG0_CBCR (0x35A8) |
| 313 | #define CAMSS_JPEG_JPEG_AHB_CBCR (0x35B4) |
| 314 | #define CAMSS_JPEG_JPEG_AXI_CBCR (0x35B8) |
| 315 | #define VFE0_CMD_RCGR (0x3600) |
| 316 | #define CPP_CMD_RCGR (0x3640) |
Matt Wagantall | 57b7456 | 2013-07-03 19:24:53 -0700 | [diff] [blame] | 317 | #define CAMSS_VFE_BCR (0x36A0) |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 318 | #define CAMSS_VFE_VFE0_CBCR (0x36A8) |
| 319 | #define CAMSS_VFE_CPP_CBCR (0x36B0) |
| 320 | #define CAMSS_VFE_CPP_AHB_CBCR (0x36B4) |
| 321 | #define CAMSS_VFE_VFE_AHB_CBCR (0x36B8) |
| 322 | #define CAMSS_VFE_VFE_AXI_CBCR (0x36BC) |
Matt Wagantall | 57b7456 | 2013-07-03 19:24:53 -0700 | [diff] [blame] | 323 | #define CAMSS_CSI_VFE0_BCR (0x3700) |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 324 | #define CAMSS_CSI_VFE0_CBCR (0x3704) |
Rajakumar Govindaram | 4c2482b | 2013-09-05 19:45:01 -0700 | [diff] [blame] | 325 | #define CAMSS_MICRO_BCR (0x3490) |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 326 | #define OXILI_GFX3D_CBCR (0x4028) |
Matt Wagantall | 57b7456 | 2013-07-03 19:24:53 -0700 | [diff] [blame] | 327 | #define OXILICX_BCR (0x4030) |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 328 | #define OXILICX_AXI_CBCR (0x4038) |
| 329 | #define OXILICX_AHB_CBCR (0x403C) |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 330 | #define MMPLL2_PLL_MODE (0x4100) |
| 331 | #define MMPLL2_PLL_STATUS (0x411C) |
| 332 | #define MMSS_MMSSNOC_AHB_CBCR (0x5024) |
| 333 | #define MMSS_MMSSNOC_BTO_AHB_CBCR (0x5028) |
| 334 | #define MMSS_MISC_AHB_CBCR (0x502C) |
| 335 | #define AXI_CMD_RCGR (0x5040) |
| 336 | #define MMSS_S0_AXI_CBCR (0x5064) |
| 337 | #define MMSS_MMSSNOC_AXI_CBCR (0x506C) |
| 338 | #define MMSS_DEBUG_CLK_CTL (0x0900) |
| 339 | #define GPLL0_MODE (0x0000) |
| 340 | #define GPLL0_L_VAL (0x0004) |
| 341 | #define GPLL0_M_VAL (0x0008) |
| 342 | #define GPLL0_N_VAL (0x000C) |
| 343 | #define GPLL0_USER_CTL (0x0010) |
| 344 | #define GPLL0_STATUS (0x001C) |
| 345 | #define GPLL1_MODE (0x0040) |
| 346 | #define GPLL1_L_VAL (0x0044) |
| 347 | #define GPLL1_M_VAL (0x0048) |
| 348 | #define GPLL1_N_VAL (0x004C) |
| 349 | #define GPLL1_USER_CTL (0x0050) |
| 350 | #define GPLL1_STATUS (0x005C) |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 351 | #define NOC_CONF_XPU_AHB_CBCR (0x01C0) |
| 352 | #define MMSS_NOC_CFG_AHB_CBCR (0x024C) |
| 353 | #define MSS_CFG_AHB_CBCR (0x0280) |
| 354 | #define MSS_Q6_BIMC_AXI_CBCR (0x0284) |
| 355 | #define USB_HS_HSIC_BCR (0x0400) |
| 356 | #define USB_HSIC_AHB_CBCR (0x0408) |
| 357 | #define USB_HSIC_SYSTEM_CMD_RCGR (0x041C) |
| 358 | #define USB_HSIC_SYSTEM_CBCR (0x040C) |
| 359 | #define USB_HSIC_CMD_RCGR (0x0440) |
| 360 | #define USB_HSIC_CBCR (0x0410) |
| 361 | #define USB_HSIC_IO_CAL_CMD_RCGR (0x0458) |
| 362 | #define USB_HSIC_IO_CAL_CBCR (0x0414) |
| 363 | #define USB_HS_BCR (0x0480) |
| 364 | #define USB_HS_SYSTEM_CBCR (0x0484) |
| 365 | #define USB_HS_AHB_CBCR (0x0488) |
| 366 | #define USB_HS_SYSTEM_CMD_RCGR (0x0490) |
| 367 | #define USB2A_PHY_SLEEP_CBCR (0x04AC) |
| 368 | #define SDCC1_APPS_CMD_RCGR (0x04D0) |
| 369 | #define SDCC1_APPS_CBCR (0x04C4) |
| 370 | #define SDCC1_AHB_CBCR (0x04C8) |
| 371 | #define SDCC2_APPS_CMD_RCGR (0x0510) |
| 372 | #define SDCC2_APPS_CBCR (0x0504) |
| 373 | #define SDCC2_AHB_CBCR (0x0508) |
| 374 | #define SDCC3_APPS_CMD_RCGR (0x0550) |
| 375 | #define SDCC3_APPS_CBCR (0x0544) |
| 376 | #define SDCC3_AHB_CBCR (0x0548) |
| 377 | #define BLSP1_AHB_CBCR (0x05C4) |
| 378 | #define BLSP1_QUP1_SPI_APPS_CBCR (0x0644) |
| 379 | #define BLSP1_QUP1_I2C_APPS_CBCR (0x0648) |
| 380 | #define BLSP1_QUP1_I2C_APPS_CMD_RCGR (0x0660) |
| 381 | #define BLSP1_QUP2_I2C_APPS_CMD_RCGR (0x06E0) |
| 382 | #define BLSP1_QUP3_I2C_APPS_CMD_RCGR (0x0760) |
| 383 | #define BLSP1_QUP4_I2C_APPS_CMD_RCGR (0x07E0) |
| 384 | #define BLSP1_QUP5_I2C_APPS_CMD_RCGR (0x0860) |
| 385 | #define BLSP1_QUP6_I2C_APPS_CMD_RCGR (0x08E0) |
| 386 | #define BLSP1_QUP1_SPI_APPS_CMD_RCGR (0x064C) |
| 387 | #define BLSP1_UART1_APPS_CBCR (0x0684) |
| 388 | #define BLSP1_UART1_APPS_CMD_RCGR (0x068C) |
| 389 | #define BLSP1_QUP2_SPI_APPS_CBCR (0x06C4) |
| 390 | #define BLSP1_QUP2_I2C_APPS_CBCR (0x06C8) |
| 391 | #define BLSP1_QUP2_SPI_APPS_CMD_RCGR (0x06CC) |
| 392 | #define BLSP1_UART2_APPS_CBCR (0x0704) |
| 393 | #define BLSP1_UART2_APPS_CMD_RCGR (0x070C) |
| 394 | #define BLSP1_QUP3_SPI_APPS_CBCR (0x0744) |
| 395 | #define BLSP1_QUP3_I2C_APPS_CBCR (0x0748) |
| 396 | #define BLSP1_QUP3_SPI_APPS_CMD_RCGR (0x074C) |
| 397 | #define BLSP1_UART3_APPS_CBCR (0x0784) |
| 398 | #define BLSP1_UART3_APPS_CMD_RCGR (0x078C) |
| 399 | #define BLSP1_QUP4_SPI_APPS_CBCR (0x07C4) |
| 400 | #define BLSP1_QUP4_I2C_APPS_CBCR (0x07C8) |
| 401 | #define BLSP1_QUP4_SPI_APPS_CMD_RCGR (0x07CC) |
| 402 | #define BLSP1_UART4_APPS_CBCR (0x0804) |
| 403 | #define BLSP1_UART4_APPS_CMD_RCGR (0x080C) |
| 404 | #define BLSP1_QUP5_SPI_APPS_CBCR (0x0844) |
| 405 | #define BLSP1_QUP5_I2C_APPS_CBCR (0x0848) |
| 406 | #define BLSP1_QUP5_SPI_APPS_CMD_RCGR (0x084C) |
| 407 | #define BLSP1_UART5_APPS_CBCR (0x0884) |
| 408 | #define BLSP1_UART5_APPS_CMD_RCGR (0x088C) |
| 409 | #define BLSP1_QUP6_SPI_APPS_CBCR (0x08C4) |
| 410 | #define BLSP1_QUP6_I2C_APPS_CBCR (0x08C8) |
| 411 | #define BLSP1_QUP6_SPI_APPS_CMD_RCGR (0x08CC) |
| 412 | #define BLSP1_UART6_APPS_CBCR (0x0904) |
| 413 | #define BLSP1_UART6_APPS_CMD_RCGR (0x090C) |
| 414 | #define PDM_AHB_CBCR (0x0CC4) |
| 415 | #define PDM_XO4_CBCR (0x0CC8) |
| 416 | #define PDM2_CBCR (0x0CCC) |
| 417 | #define PDM2_CMD_RCGR (0x0CD0) |
| 418 | #define PRNG_AHB_CBCR (0x0D04) |
| 419 | #define BAM_DMA_AHB_CBCR (0x0D44) |
| 420 | #define BOOT_ROM_AHB_CBCR (0x0E04) |
| 421 | #define CE1_CMD_RCGR (0x1050) |
| 422 | #define CE1_CBCR (0x1044) |
| 423 | #define CE1_AXI_CBCR (0x1048) |
| 424 | #define CE1_AHB_CBCR (0x104C) |
| 425 | #define GCC_XO_DIV4_CBCR (0x10C8) |
| 426 | #define LPASS_Q6_AXI_CBCR (0x11C0) |
| 427 | #define APCS_GPLL_ENA_VOTE (0x1480) |
| 428 | #define APCS_CLOCK_BRANCH_ENA_VOTE (0x1484) |
| 429 | #define APCS_CLOCK_SLEEP_ENA_VOTE (0x1488) |
| 430 | #define GCC_DEBUG_CLK_CTL (0x1880) |
| 431 | #define CLOCK_FRQ_MEASURE_CTL (0x1884) |
| 432 | #define CLOCK_FRQ_MEASURE_STATUS (0x1888) |
| 433 | #define PLLTEST_PAD_CFG (0x188C) |
| 434 | #define GP1_CBCR (0x1900) |
| 435 | #define GP1_CMD_RCGR (0x1904) |
| 436 | #define GP2_CBCR (0x1940) |
| 437 | #define GP2_CMD_RCGR (0x1944) |
| 438 | #define GP3_CBCR (0x1980) |
| 439 | #define GP3_CMD_RCGR (0x1984) |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 440 | #define Q6SS_BCR (0x6000) |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 441 | #define Q6SS_AHB_LFABIF_CBCR (0x22000) |
| 442 | #define Q6SS_AHBM_CBCR (0x22004) |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 443 | #define Q6SS_XO_CBCR (0x26000) |
Patrick Daly | 01d4c1d | 2013-05-22 19:10:55 -0700 | [diff] [blame] | 444 | #define KPSS_AHB_CMD_RCGR (0x120C) |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 445 | |
| 446 | static unsigned int soft_vote_gpll0; |
| 447 | |
| 448 | static struct pll_vote_clk gpll0 = { |
| 449 | .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE, |
| 450 | .en_mask = BIT(0), |
| 451 | .status_reg = (void __iomem *)GPLL0_STATUS, |
| 452 | .status_mask = BIT(17), |
| 453 | .soft_vote = &soft_vote_gpll0, |
| 454 | .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY, |
| 455 | .base = &virt_bases[GCC_BASE], |
| 456 | .c = { |
| 457 | .rate = 600000000, |
| 458 | .parent = &xo.c, |
| 459 | .dbg_name = "gpll0", |
| 460 | .ops = &clk_ops_pll_acpu_vote, |
| 461 | CLK_INIT(gpll0.c), |
| 462 | }, |
| 463 | }; |
| 464 | |
| 465 | /*Don't vote for xo if using this clock to allow xo shutdown*/ |
| 466 | static struct pll_vote_clk gpll0_ao = { |
| 467 | .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE, |
| 468 | .en_mask = BIT(0), |
| 469 | .status_reg = (void __iomem *)GPLL0_STATUS, |
| 470 | .status_mask = BIT(17), |
| 471 | .soft_vote = &soft_vote_gpll0, |
| 472 | .soft_vote_mask = PLL_SOFT_VOTE_ACPU, |
| 473 | .base = &virt_bases[GCC_BASE], |
| 474 | .c = { |
| 475 | .rate = 600000000, |
| 476 | .dbg_name = "gpll0_ao", |
| 477 | .ops = &clk_ops_pll_acpu_vote, |
| 478 | CLK_INIT(gpll0_ao.c), |
| 479 | }, |
| 480 | }; |
| 481 | |
| 482 | static struct pll_vote_clk gpll1 = { |
| 483 | .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE, |
| 484 | .en_mask = BIT(1), |
| 485 | .status_reg = (void __iomem *)GPLL1_STATUS, |
| 486 | .status_mask = BIT(17), |
| 487 | .base = &virt_bases[GCC_BASE], |
| 488 | .c = { |
| 489 | .rate = 480000000, |
| 490 | .parent = &xo.c, |
| 491 | .dbg_name = "gpll1", |
| 492 | .ops = &clk_ops_pll_vote, |
| 493 | CLK_INIT(gpll1.c), |
| 494 | }, |
| 495 | }; |
| 496 | |
| 497 | static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = { |
Patrick Daly | 4f83243 | 2013-02-26 12:40:49 -0800 | [diff] [blame] | 498 | F_GCC( 19200000, xo, 1, 0, 0), |
| 499 | F_GCC( 50000000, gpll0, 12, 0, 0), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 500 | F_END |
| 501 | }; |
| 502 | |
| 503 | static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = { |
| 504 | .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR, |
| 505 | .set_rate = set_rate_hid, |
| 506 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
| 507 | .current_freq = &rcg_dummy_freq, |
| 508 | .base = &virt_bases[GCC_BASE], |
| 509 | .c = { |
| 510 | .dbg_name = "blsp1_qup1_i2c_apps_clk_src", |
| 511 | .ops = &clk_ops_rcg, |
| 512 | VDD_DIG_FMAX_MAP1(LOW, 50000000), |
| 513 | CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c), |
| 514 | }, |
| 515 | }; |
| 516 | |
| 517 | static struct clk_freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = { |
| 518 | F_GCC( 960000, xo, 10, 1, 2), |
| 519 | F_GCC( 4800000, xo, 4, 0, 0), |
| 520 | F_GCC( 9600000, xo, 2, 0, 0), |
| 521 | F_GCC( 15000000, gpll0, 10, 1, 4), |
| 522 | F_GCC( 19200000, xo, 1, 0, 0), |
| 523 | F_GCC( 25000000, gpll0, 12, 1, 2), |
| 524 | F_GCC( 50000000, gpll0, 12, 0, 0), |
| 525 | F_END |
| 526 | }; |
| 527 | |
| 528 | static struct rcg_clk blsp1_qup1_spi_apps_clk_src = { |
| 529 | .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR, |
| 530 | .set_rate = set_rate_mnd, |
| 531 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 532 | .current_freq = &rcg_dummy_freq, |
| 533 | .base = &virt_bases[GCC_BASE], |
| 534 | .c = { |
| 535 | .dbg_name = "blsp1_qup1_spi_apps_clk_src", |
| 536 | .ops = &clk_ops_rcg_mnd, |
| 537 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 538 | CLK_INIT(blsp1_qup1_spi_apps_clk_src.c), |
| 539 | }, |
| 540 | }; |
| 541 | |
| 542 | static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = { |
| 543 | .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR, |
| 544 | .set_rate = set_rate_hid, |
| 545 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
| 546 | .current_freq = &rcg_dummy_freq, |
| 547 | .base = &virt_bases[GCC_BASE], |
| 548 | .c = { |
| 549 | .dbg_name = "blsp1_qup2_i2c_apps_clk_src", |
| 550 | .ops = &clk_ops_rcg, |
| 551 | VDD_DIG_FMAX_MAP1(LOW, 50000000), |
| 552 | CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c), |
| 553 | }, |
| 554 | }; |
| 555 | |
| 556 | static struct rcg_clk blsp1_qup2_spi_apps_clk_src = { |
| 557 | .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR, |
| 558 | .set_rate = set_rate_mnd, |
| 559 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 560 | .current_freq = &rcg_dummy_freq, |
| 561 | .base = &virt_bases[GCC_BASE], |
| 562 | .c = { |
| 563 | .dbg_name = "blsp1_qup2_spi_apps_clk_src", |
| 564 | .ops = &clk_ops_rcg_mnd, |
| 565 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 566 | CLK_INIT(blsp1_qup2_spi_apps_clk_src.c), |
| 567 | }, |
| 568 | }; |
| 569 | |
| 570 | static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = { |
| 571 | .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR, |
| 572 | .set_rate = set_rate_hid, |
| 573 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
| 574 | .current_freq = &rcg_dummy_freq, |
| 575 | .base = &virt_bases[GCC_BASE], |
| 576 | .c = { |
| 577 | .dbg_name = "blsp1_qup3_i2c_apps_clk_src", |
| 578 | .ops = &clk_ops_rcg, |
| 579 | VDD_DIG_FMAX_MAP1(LOW, 50000000), |
| 580 | CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c), |
| 581 | }, |
| 582 | }; |
| 583 | |
| 584 | static struct rcg_clk blsp1_qup3_spi_apps_clk_src = { |
| 585 | .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR, |
| 586 | .set_rate = set_rate_mnd, |
| 587 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 588 | .current_freq = &rcg_dummy_freq, |
| 589 | .base = &virt_bases[GCC_BASE], |
| 590 | .c = { |
| 591 | .dbg_name = "blsp1_qup3_spi_apps_clk_src", |
| 592 | .ops = &clk_ops_rcg_mnd, |
| 593 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 594 | CLK_INIT(blsp1_qup3_spi_apps_clk_src.c), |
| 595 | }, |
| 596 | }; |
| 597 | |
| 598 | static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = { |
| 599 | .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR, |
| 600 | .set_rate = set_rate_hid, |
| 601 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
| 602 | .current_freq = &rcg_dummy_freq, |
| 603 | .base = &virt_bases[GCC_BASE], |
| 604 | .c = { |
| 605 | .dbg_name = "blsp1_qup4_i2c_apps_clk_src", |
| 606 | .ops = &clk_ops_rcg, |
| 607 | VDD_DIG_FMAX_MAP1(LOW, 50000000), |
| 608 | CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c), |
| 609 | }, |
| 610 | }; |
| 611 | |
| 612 | static struct rcg_clk blsp1_qup4_spi_apps_clk_src = { |
| 613 | .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR, |
| 614 | .set_rate = set_rate_mnd, |
| 615 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 616 | .current_freq = &rcg_dummy_freq, |
| 617 | .base = &virt_bases[GCC_BASE], |
| 618 | .c = { |
| 619 | .dbg_name = "blsp1_qup4_spi_apps_clk_src", |
| 620 | .ops = &clk_ops_rcg_mnd, |
| 621 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 622 | CLK_INIT(blsp1_qup4_spi_apps_clk_src.c), |
| 623 | }, |
| 624 | }; |
| 625 | |
| 626 | static struct rcg_clk blsp1_qup5_i2c_apps_clk_src = { |
| 627 | .cmd_rcgr_reg = BLSP1_QUP5_I2C_APPS_CMD_RCGR, |
| 628 | .set_rate = set_rate_hid, |
| 629 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
| 630 | .current_freq = &rcg_dummy_freq, |
| 631 | .base = &virt_bases[GCC_BASE], |
| 632 | .c = { |
| 633 | .dbg_name = "blsp1_qup5_i2c_apps_clk_src", |
| 634 | .ops = &clk_ops_rcg, |
| 635 | VDD_DIG_FMAX_MAP1(LOW, 50000000), |
| 636 | CLK_INIT(blsp1_qup5_i2c_apps_clk_src.c), |
| 637 | }, |
| 638 | }; |
| 639 | |
| 640 | static struct rcg_clk blsp1_qup5_spi_apps_clk_src = { |
| 641 | .cmd_rcgr_reg = BLSP1_QUP5_SPI_APPS_CMD_RCGR, |
| 642 | .set_rate = set_rate_mnd, |
| 643 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 644 | .current_freq = &rcg_dummy_freq, |
| 645 | .base = &virt_bases[GCC_BASE], |
| 646 | .c = { |
| 647 | .dbg_name = "blsp1_qup5_spi_apps_clk_src", |
| 648 | .ops = &clk_ops_rcg_mnd, |
| 649 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 650 | CLK_INIT(blsp1_qup5_spi_apps_clk_src.c), |
| 651 | }, |
| 652 | }; |
| 653 | |
| 654 | static struct rcg_clk blsp1_qup6_i2c_apps_clk_src = { |
| 655 | .cmd_rcgr_reg = BLSP1_QUP6_I2C_APPS_CMD_RCGR, |
| 656 | .set_rate = set_rate_hid, |
| 657 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk, |
| 658 | .current_freq = &rcg_dummy_freq, |
| 659 | .base = &virt_bases[GCC_BASE], |
| 660 | .c = { |
| 661 | .dbg_name = "blsp1_qup6_i2c_apps_clk_src", |
| 662 | .ops = &clk_ops_rcg, |
| 663 | VDD_DIG_FMAX_MAP1(LOW, 50000000), |
| 664 | CLK_INIT(blsp1_qup6_i2c_apps_clk_src.c), |
| 665 | }, |
| 666 | }; |
| 667 | |
| 668 | static struct rcg_clk blsp1_qup6_spi_apps_clk_src = { |
| 669 | .cmd_rcgr_reg = BLSP1_QUP6_SPI_APPS_CMD_RCGR, |
| 670 | .set_rate = set_rate_mnd, |
| 671 | .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk, |
| 672 | .current_freq = &rcg_dummy_freq, |
| 673 | .base = &virt_bases[GCC_BASE], |
| 674 | .c = { |
| 675 | .dbg_name = "blsp1_qup6_spi_apps_clk_src", |
| 676 | .ops = &clk_ops_rcg_mnd, |
| 677 | VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), |
| 678 | CLK_INIT(blsp1_qup6_spi_apps_clk_src.c), |
| 679 | }, |
| 680 | }; |
| 681 | |
| 682 | static struct clk_freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = { |
| 683 | F_GCC( 3686400, gpll0, 1, 96, 15625), |
| 684 | F_GCC( 7372800, gpll0, 1, 192, 15625), |
| 685 | F_GCC( 14745600, gpll0, 1, 384, 15625), |
| 686 | F_GCC( 16000000, gpll0, 5, 2, 15), |
| 687 | F_GCC( 19200000, xo, 1, 0, 0), |
| 688 | F_GCC( 24000000, gpll0, 5, 1, 5), |
| 689 | F_GCC( 32000000, gpll0, 1, 4, 75), |
| 690 | F_GCC( 40000000, gpll0, 15, 0, 0), |
| 691 | F_GCC( 46400000, gpll0, 1, 29, 375), |
| 692 | F_GCC( 48000000, gpll0, 12.5, 0, 0), |
| 693 | F_GCC( 51200000, gpll0, 1, 32, 375), |
| 694 | F_GCC( 56000000, gpll0, 1, 7, 75), |
| 695 | F_GCC( 58982400, gpll0, 1, 1536, 15625), |
| 696 | F_GCC( 60000000, gpll0, 10, 0, 0), |
Vikram Mulukutla | 0caccf9 | 2013-11-18 14:55:42 -0800 | [diff] [blame] | 697 | F_GCC( 63160000, gpll0, 9.5, 0, 0), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 698 | F_END |
| 699 | }; |
| 700 | |
| 701 | static struct rcg_clk blsp1_uart1_apps_clk_src = { |
| 702 | .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR, |
| 703 | .set_rate = set_rate_mnd, |
| 704 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 705 | .current_freq = &rcg_dummy_freq, |
| 706 | .base = &virt_bases[GCC_BASE], |
| 707 | .c = { |
| 708 | .dbg_name = "blsp1_uart1_apps_clk_src", |
| 709 | .ops = &clk_ops_rcg_mnd, |
| 710 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 711 | CLK_INIT(blsp1_uart1_apps_clk_src.c), |
| 712 | }, |
| 713 | }; |
| 714 | |
| 715 | static struct rcg_clk blsp1_uart2_apps_clk_src = { |
| 716 | .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR, |
| 717 | .set_rate = set_rate_mnd, |
| 718 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 719 | .current_freq = &rcg_dummy_freq, |
| 720 | .base = &virt_bases[GCC_BASE], |
| 721 | .c = { |
| 722 | .dbg_name = "blsp1_uart2_apps_clk_src", |
| 723 | .ops = &clk_ops_rcg_mnd, |
| 724 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 725 | CLK_INIT(blsp1_uart2_apps_clk_src.c), |
| 726 | }, |
| 727 | }; |
| 728 | |
| 729 | static struct rcg_clk blsp1_uart3_apps_clk_src = { |
| 730 | .cmd_rcgr_reg = BLSP1_UART3_APPS_CMD_RCGR, |
| 731 | .set_rate = set_rate_mnd, |
| 732 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 733 | .current_freq = &rcg_dummy_freq, |
| 734 | .base = &virt_bases[GCC_BASE], |
| 735 | .c = { |
| 736 | .dbg_name = "blsp1_uart3_apps_clk_src", |
| 737 | .ops = &clk_ops_rcg_mnd, |
| 738 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 739 | CLK_INIT(blsp1_uart3_apps_clk_src.c), |
| 740 | }, |
| 741 | }; |
| 742 | |
| 743 | static struct rcg_clk blsp1_uart4_apps_clk_src = { |
| 744 | .cmd_rcgr_reg = BLSP1_UART4_APPS_CMD_RCGR, |
| 745 | .set_rate = set_rate_mnd, |
| 746 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 747 | .current_freq = &rcg_dummy_freq, |
| 748 | .base = &virt_bases[GCC_BASE], |
| 749 | .c = { |
| 750 | .dbg_name = "blsp1_uart4_apps_clk_src", |
| 751 | .ops = &clk_ops_rcg_mnd, |
| 752 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 753 | CLK_INIT(blsp1_uart4_apps_clk_src.c), |
| 754 | }, |
| 755 | }; |
| 756 | |
| 757 | static struct rcg_clk blsp1_uart5_apps_clk_src = { |
| 758 | .cmd_rcgr_reg = BLSP1_UART5_APPS_CMD_RCGR, |
| 759 | .set_rate = set_rate_mnd, |
| 760 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 761 | .current_freq = &rcg_dummy_freq, |
| 762 | .base = &virt_bases[GCC_BASE], |
| 763 | .c = { |
| 764 | .dbg_name = "blsp1_uart5_apps_clk_src", |
| 765 | .ops = &clk_ops_rcg_mnd, |
| 766 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 767 | CLK_INIT(blsp1_uart5_apps_clk_src.c), |
| 768 | }, |
| 769 | }; |
| 770 | |
| 771 | static struct rcg_clk blsp1_uart6_apps_clk_src = { |
| 772 | .cmd_rcgr_reg = BLSP1_UART6_APPS_CMD_RCGR, |
| 773 | .set_rate = set_rate_mnd, |
| 774 | .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk, |
| 775 | .current_freq = &rcg_dummy_freq, |
| 776 | .base = &virt_bases[GCC_BASE], |
| 777 | .c = { |
| 778 | .dbg_name = "blsp1_uart6_apps_clk_src", |
| 779 | .ops = &clk_ops_rcg_mnd, |
| 780 | VDD_DIG_FMAX_MAP2(LOW, 31580000, NOMINAL, 63160000), |
| 781 | CLK_INIT(blsp1_uart6_apps_clk_src.c), |
| 782 | }, |
| 783 | }; |
| 784 | |
| 785 | static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = { |
| 786 | F_GCC( 50000000, gpll0, 12, 0, 0), |
| 787 | F_GCC( 100000000, gpll0, 6, 0, 0), |
| 788 | F_END |
| 789 | }; |
| 790 | |
| 791 | static struct rcg_clk ce1_clk_src = { |
| 792 | .cmd_rcgr_reg = CE1_CMD_RCGR, |
| 793 | .set_rate = set_rate_hid, |
| 794 | .freq_tbl = ftbl_gcc_ce1_clk, |
| 795 | .current_freq = &rcg_dummy_freq, |
| 796 | .base = &virt_bases[GCC_BASE], |
| 797 | .c = { |
| 798 | .dbg_name = "ce1_clk_src", |
| 799 | .ops = &clk_ops_rcg, |
| 800 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
| 801 | CLK_INIT(ce1_clk_src.c), |
| 802 | }, |
| 803 | }; |
| 804 | |
| 805 | static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = { |
| 806 | F_GCC( 19200000, xo, 1, 0, 0), |
| 807 | F_END |
| 808 | }; |
| 809 | |
| 810 | static struct rcg_clk gp1_clk_src = { |
| 811 | .cmd_rcgr_reg = GP1_CMD_RCGR, |
| 812 | .set_rate = set_rate_mnd, |
| 813 | .freq_tbl = ftbl_gcc_gp1_3_clk, |
| 814 | .current_freq = &rcg_dummy_freq, |
| 815 | .base = &virt_bases[GCC_BASE], |
| 816 | .c = { |
| 817 | .dbg_name = "gp1_clk_src", |
| 818 | .ops = &clk_ops_rcg_mnd, |
| 819 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 820 | CLK_INIT(gp1_clk_src.c), |
| 821 | }, |
| 822 | }; |
| 823 | |
| 824 | static struct rcg_clk gp2_clk_src = { |
| 825 | .cmd_rcgr_reg = GP2_CMD_RCGR, |
| 826 | .set_rate = set_rate_mnd, |
| 827 | .freq_tbl = ftbl_gcc_gp1_3_clk, |
| 828 | .current_freq = &rcg_dummy_freq, |
| 829 | .base = &virt_bases[GCC_BASE], |
| 830 | .c = { |
| 831 | .dbg_name = "gp2_clk_src", |
| 832 | .ops = &clk_ops_rcg_mnd, |
| 833 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 834 | CLK_INIT(gp2_clk_src.c), |
| 835 | }, |
| 836 | }; |
| 837 | |
| 838 | static struct rcg_clk gp3_clk_src = { |
| 839 | .cmd_rcgr_reg = GP3_CMD_RCGR, |
| 840 | .set_rate = set_rate_mnd, |
| 841 | .freq_tbl = ftbl_gcc_gp1_3_clk, |
| 842 | .current_freq = &rcg_dummy_freq, |
| 843 | .base = &virt_bases[GCC_BASE], |
| 844 | .c = { |
| 845 | .dbg_name = "gp3_clk_src", |
| 846 | .ops = &clk_ops_rcg_mnd, |
| 847 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 848 | CLK_INIT(gp3_clk_src.c), |
| 849 | }, |
| 850 | }; |
| 851 | |
| 852 | static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = { |
| 853 | F_GCC( 60000000, gpll0, 10, 0, 0), |
| 854 | F_END |
| 855 | }; |
| 856 | |
| 857 | static struct rcg_clk pdm2_clk_src = { |
| 858 | .cmd_rcgr_reg = PDM2_CMD_RCGR, |
| 859 | .set_rate = set_rate_hid, |
| 860 | .freq_tbl = ftbl_gcc_pdm2_clk, |
| 861 | .current_freq = &rcg_dummy_freq, |
| 862 | .base = &virt_bases[GCC_BASE], |
| 863 | .c = { |
| 864 | .dbg_name = "pdm2_clk_src", |
| 865 | .ops = &clk_ops_rcg, |
| 866 | VDD_DIG_FMAX_MAP1(LOW, 60000000), |
| 867 | CLK_INIT(pdm2_clk_src.c), |
| 868 | }, |
| 869 | }; |
| 870 | |
| 871 | static struct clk_freq_tbl ftbl_gcc_sdcc1_3_apps_clk[] = { |
| 872 | F_GCC( 144000, xo, 16, 3, 25), |
| 873 | F_GCC( 400000, xo, 12, 1, 4), |
| 874 | F_GCC( 20000000, gpll0, 15, 1, 2), |
| 875 | F_GCC( 25000000, gpll0, 12, 1, 2), |
| 876 | F_GCC( 50000000, gpll0, 12, 0, 0), |
| 877 | F_GCC( 100000000, gpll0, 6, 0, 0), |
| 878 | F_GCC( 200000000, gpll0, 3, 0, 0), |
| 879 | F_END |
| 880 | }; |
| 881 | |
| 882 | static struct rcg_clk sdcc1_apps_clk_src = { |
| 883 | .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR, |
| 884 | .set_rate = set_rate_mnd, |
| 885 | .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk, |
| 886 | .current_freq = &rcg_dummy_freq, |
| 887 | .base = &virt_bases[GCC_BASE], |
| 888 | .c = { |
| 889 | .dbg_name = "sdcc1_apps_clk_src", |
| 890 | .ops = &clk_ops_rcg_mnd, |
| 891 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 892 | CLK_INIT(sdcc1_apps_clk_src.c), |
| 893 | }, |
| 894 | }; |
| 895 | |
| 896 | static struct rcg_clk sdcc2_apps_clk_src = { |
| 897 | .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR, |
| 898 | .set_rate = set_rate_mnd, |
| 899 | .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk, |
| 900 | .current_freq = &rcg_dummy_freq, |
| 901 | .base = &virt_bases[GCC_BASE], |
| 902 | .c = { |
| 903 | .dbg_name = "sdcc2_apps_clk_src", |
| 904 | .ops = &clk_ops_rcg_mnd, |
| 905 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 906 | CLK_INIT(sdcc2_apps_clk_src.c), |
| 907 | }, |
| 908 | }; |
| 909 | |
| 910 | static struct rcg_clk sdcc3_apps_clk_src = { |
| 911 | .cmd_rcgr_reg = SDCC3_APPS_CMD_RCGR, |
| 912 | .set_rate = set_rate_mnd, |
| 913 | .freq_tbl = ftbl_gcc_sdcc1_3_apps_clk, |
| 914 | .current_freq = &rcg_dummy_freq, |
| 915 | .base = &virt_bases[GCC_BASE], |
| 916 | .c = { |
| 917 | .dbg_name = "sdcc3_apps_clk_src", |
| 918 | .ops = &clk_ops_rcg_mnd, |
| 919 | VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000), |
| 920 | CLK_INIT(sdcc3_apps_clk_src.c), |
| 921 | }, |
| 922 | }; |
| 923 | |
| 924 | static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = { |
| 925 | F_GCC( 75000000, gpll0, 8, 0, 0), |
| 926 | F_END |
| 927 | }; |
| 928 | |
| 929 | static struct rcg_clk usb_hs_system_clk_src = { |
| 930 | .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR, |
| 931 | .set_rate = set_rate_hid, |
| 932 | .freq_tbl = ftbl_gcc_usb_hs_system_clk, |
| 933 | .current_freq = &rcg_dummy_freq, |
| 934 | .base = &virt_bases[GCC_BASE], |
| 935 | .c = { |
| 936 | .dbg_name = "usb_hs_system_clk_src", |
| 937 | .ops = &clk_ops_rcg, |
| 938 | VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000), |
| 939 | CLK_INIT(usb_hs_system_clk_src.c), |
| 940 | }, |
| 941 | }; |
| 942 | |
| 943 | static struct clk_freq_tbl ftbl_gcc_usb_hsic_clk[] = { |
| 944 | F_HSIC( 480000000, gpll1, 0, 0, 0), |
| 945 | F_END |
| 946 | }; |
| 947 | |
| 948 | static struct rcg_clk usb_hsic_clk_src = { |
| 949 | .cmd_rcgr_reg = USB_HSIC_CMD_RCGR, |
| 950 | .set_rate = set_rate_hid, |
| 951 | .freq_tbl = ftbl_gcc_usb_hsic_clk, |
| 952 | .current_freq = &rcg_dummy_freq, |
| 953 | .base = &virt_bases[GCC_BASE], |
| 954 | .c = { |
| 955 | .dbg_name = "usb_hsic_clk_src", |
| 956 | .ops = &clk_ops_rcg, |
| 957 | VDD_DIG_FMAX_MAP1(LOW, 480000000), |
| 958 | CLK_INIT(usb_hsic_clk_src.c), |
| 959 | }, |
| 960 | }; |
| 961 | |
| 962 | static struct clk_freq_tbl ftbl_gcc_usb_hsic_io_cal_clk[] = { |
| 963 | F_GCC( 9600000, xo, 2, 0, 0), |
| 964 | F_END |
| 965 | }; |
| 966 | |
| 967 | static struct rcg_clk usb_hsic_io_cal_clk_src = { |
| 968 | .cmd_rcgr_reg = USB_HSIC_IO_CAL_CMD_RCGR, |
| 969 | .set_rate = set_rate_hid, |
| 970 | .freq_tbl = ftbl_gcc_usb_hsic_io_cal_clk, |
| 971 | .current_freq = &rcg_dummy_freq, |
| 972 | .base = &virt_bases[GCC_BASE], |
| 973 | .c = { |
| 974 | .dbg_name = "usb_hsic_io_cal_clk_src", |
| 975 | .ops = &clk_ops_rcg, |
| 976 | VDD_DIG_FMAX_MAP1(LOW, 9600000), |
| 977 | CLK_INIT(usb_hsic_io_cal_clk_src.c), |
| 978 | }, |
| 979 | }; |
| 980 | |
| 981 | static struct clk_freq_tbl ftbl_gcc_usb_hsic_system_clk[] = { |
| 982 | F_GCC( 75000000, gpll0, 8, 0, 0), |
| 983 | F_END |
| 984 | }; |
| 985 | |
| 986 | static struct rcg_clk usb_hsic_system_clk_src = { |
| 987 | .cmd_rcgr_reg = USB_HSIC_SYSTEM_CMD_RCGR, |
| 988 | .set_rate = set_rate_hid, |
| 989 | .freq_tbl = ftbl_gcc_usb_hsic_system_clk, |
| 990 | .current_freq = &rcg_dummy_freq, |
| 991 | .base = &virt_bases[GCC_BASE], |
| 992 | .c = { |
| 993 | .dbg_name = "usb_hsic_system_clk_src", |
| 994 | .ops = &clk_ops_rcg, |
| 995 | VDD_DIG_FMAX_MAP2(LOW, 37500000, NOMINAL, 75000000), |
| 996 | CLK_INIT(usb_hsic_system_clk_src.c), |
| 997 | }, |
| 998 | }; |
| 999 | |
| 1000 | static struct local_vote_clk gcc_bam_dma_ahb_clk = { |
| 1001 | .cbcr_reg = BAM_DMA_AHB_CBCR, |
| 1002 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1003 | .en_mask = BIT(12), |
| 1004 | .base = &virt_bases[GCC_BASE], |
| 1005 | .c = { |
| 1006 | .dbg_name = "gcc_bam_dma_ahb_clk", |
| 1007 | .ops = &clk_ops_vote, |
| 1008 | CLK_INIT(gcc_bam_dma_ahb_clk.c), |
| 1009 | }, |
| 1010 | }; |
| 1011 | |
| 1012 | static struct local_vote_clk gcc_blsp1_ahb_clk = { |
| 1013 | .cbcr_reg = BLSP1_AHB_CBCR, |
| 1014 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1015 | .en_mask = BIT(17), |
| 1016 | .base = &virt_bases[GCC_BASE], |
| 1017 | .c = { |
| 1018 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 1019 | .ops = &clk_ops_vote, |
| 1020 | CLK_INIT(gcc_blsp1_ahb_clk.c), |
| 1021 | }, |
| 1022 | }; |
| 1023 | |
| 1024 | static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = { |
| 1025 | .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR, |
| 1026 | .has_sibling = 0, |
| 1027 | .base = &virt_bases[GCC_BASE], |
| 1028 | .c = { |
| 1029 | .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk", |
| 1030 | .parent = &blsp1_qup1_i2c_apps_clk_src.c, |
| 1031 | .ops = &clk_ops_branch, |
| 1032 | CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c), |
| 1033 | }, |
| 1034 | }; |
| 1035 | |
| 1036 | static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = { |
| 1037 | .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR, |
| 1038 | .has_sibling = 0, |
| 1039 | .base = &virt_bases[GCC_BASE], |
| 1040 | .c = { |
| 1041 | .dbg_name = "gcc_blsp1_qup1_spi_apps_clk", |
| 1042 | .parent = &blsp1_qup1_spi_apps_clk_src.c, |
| 1043 | .ops = &clk_ops_branch, |
| 1044 | CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c), |
| 1045 | }, |
| 1046 | }; |
| 1047 | |
| 1048 | static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = { |
| 1049 | .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR, |
| 1050 | .has_sibling = 0, |
| 1051 | .base = &virt_bases[GCC_BASE], |
| 1052 | .c = { |
| 1053 | .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk", |
| 1054 | .parent = &blsp1_qup2_i2c_apps_clk_src.c, |
| 1055 | .ops = &clk_ops_branch, |
| 1056 | CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c), |
| 1057 | }, |
| 1058 | }; |
| 1059 | |
| 1060 | static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = { |
| 1061 | .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR, |
| 1062 | .has_sibling = 0, |
| 1063 | .base = &virt_bases[GCC_BASE], |
| 1064 | .c = { |
| 1065 | .dbg_name = "gcc_blsp1_qup2_spi_apps_clk", |
| 1066 | .parent = &blsp1_qup2_spi_apps_clk_src.c, |
| 1067 | .ops = &clk_ops_branch, |
| 1068 | CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c), |
| 1069 | }, |
| 1070 | }; |
| 1071 | |
| 1072 | static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = { |
| 1073 | .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR, |
| 1074 | .has_sibling = 0, |
| 1075 | .base = &virt_bases[GCC_BASE], |
| 1076 | .c = { |
| 1077 | .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk", |
| 1078 | .parent = &blsp1_qup3_i2c_apps_clk_src.c, |
| 1079 | .ops = &clk_ops_branch, |
| 1080 | CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c), |
| 1081 | }, |
| 1082 | }; |
| 1083 | |
| 1084 | static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = { |
| 1085 | .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR, |
| 1086 | .has_sibling = 0, |
| 1087 | .base = &virt_bases[GCC_BASE], |
| 1088 | .c = { |
| 1089 | .dbg_name = "gcc_blsp1_qup3_spi_apps_clk", |
| 1090 | .parent = &blsp1_qup3_spi_apps_clk_src.c, |
| 1091 | .ops = &clk_ops_branch, |
| 1092 | CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c), |
| 1093 | }, |
| 1094 | }; |
| 1095 | |
| 1096 | static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = { |
| 1097 | .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR, |
| 1098 | .has_sibling = 0, |
| 1099 | .base = &virt_bases[GCC_BASE], |
| 1100 | .c = { |
| 1101 | .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk", |
| 1102 | .parent = &blsp1_qup4_i2c_apps_clk_src.c, |
| 1103 | .ops = &clk_ops_branch, |
| 1104 | CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c), |
| 1105 | }, |
| 1106 | }; |
| 1107 | |
| 1108 | static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = { |
| 1109 | .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR, |
| 1110 | .has_sibling = 0, |
| 1111 | .base = &virt_bases[GCC_BASE], |
| 1112 | .c = { |
| 1113 | .dbg_name = "gcc_blsp1_qup4_spi_apps_clk", |
| 1114 | .parent = &blsp1_qup4_spi_apps_clk_src.c, |
| 1115 | .ops = &clk_ops_branch, |
| 1116 | CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c), |
| 1117 | }, |
| 1118 | }; |
| 1119 | |
| 1120 | static struct branch_clk gcc_blsp1_qup5_i2c_apps_clk = { |
| 1121 | .cbcr_reg = BLSP1_QUP5_I2C_APPS_CBCR, |
| 1122 | .has_sibling = 0, |
| 1123 | .base = &virt_bases[GCC_BASE], |
| 1124 | .c = { |
| 1125 | .dbg_name = "gcc_blsp1_qup5_i2c_apps_clk", |
| 1126 | .parent = &blsp1_qup5_i2c_apps_clk_src.c, |
| 1127 | .ops = &clk_ops_branch, |
| 1128 | CLK_INIT(gcc_blsp1_qup5_i2c_apps_clk.c), |
| 1129 | }, |
| 1130 | }; |
| 1131 | |
| 1132 | static struct branch_clk gcc_blsp1_qup5_spi_apps_clk = { |
| 1133 | .cbcr_reg = BLSP1_QUP5_SPI_APPS_CBCR, |
| 1134 | .has_sibling = 0, |
| 1135 | .base = &virt_bases[GCC_BASE], |
| 1136 | .c = { |
| 1137 | .dbg_name = "gcc_blsp1_qup5_spi_apps_clk", |
| 1138 | .parent = &blsp1_qup5_spi_apps_clk_src.c, |
| 1139 | .ops = &clk_ops_branch, |
| 1140 | CLK_INIT(gcc_blsp1_qup5_spi_apps_clk.c), |
| 1141 | }, |
| 1142 | }; |
| 1143 | |
| 1144 | static struct branch_clk gcc_blsp1_qup6_i2c_apps_clk = { |
| 1145 | .cbcr_reg = BLSP1_QUP6_I2C_APPS_CBCR, |
| 1146 | .has_sibling = 0, |
| 1147 | .base = &virt_bases[GCC_BASE], |
| 1148 | .c = { |
| 1149 | .dbg_name = "gcc_blsp1_qup6_i2c_apps_clk", |
| 1150 | .parent = &blsp1_qup6_i2c_apps_clk_src.c, |
| 1151 | .ops = &clk_ops_branch, |
| 1152 | CLK_INIT(gcc_blsp1_qup6_i2c_apps_clk.c), |
| 1153 | }, |
| 1154 | }; |
| 1155 | |
| 1156 | static struct branch_clk gcc_blsp1_qup6_spi_apps_clk = { |
| 1157 | .cbcr_reg = BLSP1_QUP6_SPI_APPS_CBCR, |
| 1158 | .has_sibling = 0, |
| 1159 | .base = &virt_bases[GCC_BASE], |
| 1160 | .c = { |
| 1161 | .dbg_name = "gcc_blsp1_qup6_spi_apps_clk", |
| 1162 | .parent = &blsp1_qup6_spi_apps_clk_src.c, |
| 1163 | .ops = &clk_ops_branch, |
| 1164 | CLK_INIT(gcc_blsp1_qup6_spi_apps_clk.c), |
| 1165 | }, |
| 1166 | }; |
| 1167 | |
| 1168 | static struct branch_clk gcc_blsp1_uart1_apps_clk = { |
| 1169 | .cbcr_reg = BLSP1_UART1_APPS_CBCR, |
| 1170 | .has_sibling = 0, |
| 1171 | .base = &virt_bases[GCC_BASE], |
| 1172 | .c = { |
| 1173 | .dbg_name = "gcc_blsp1_uart1_apps_clk", |
| 1174 | .parent = &blsp1_uart1_apps_clk_src.c, |
| 1175 | .ops = &clk_ops_branch, |
| 1176 | CLK_INIT(gcc_blsp1_uart1_apps_clk.c), |
| 1177 | }, |
| 1178 | }; |
| 1179 | |
| 1180 | static struct branch_clk gcc_blsp1_uart2_apps_clk = { |
| 1181 | .cbcr_reg = BLSP1_UART2_APPS_CBCR, |
| 1182 | .has_sibling = 0, |
| 1183 | .base = &virt_bases[GCC_BASE], |
| 1184 | .c = { |
| 1185 | .dbg_name = "gcc_blsp1_uart2_apps_clk", |
| 1186 | .parent = &blsp1_uart2_apps_clk_src.c, |
| 1187 | .ops = &clk_ops_branch, |
| 1188 | CLK_INIT(gcc_blsp1_uart2_apps_clk.c), |
| 1189 | }, |
| 1190 | }; |
| 1191 | |
| 1192 | static struct branch_clk gcc_blsp1_uart3_apps_clk = { |
| 1193 | .cbcr_reg = BLSP1_UART3_APPS_CBCR, |
| 1194 | .has_sibling = 0, |
| 1195 | .base = &virt_bases[GCC_BASE], |
| 1196 | .c = { |
| 1197 | .dbg_name = "gcc_blsp1_uart3_apps_clk", |
| 1198 | .parent = &blsp1_uart3_apps_clk_src.c, |
| 1199 | .ops = &clk_ops_branch, |
| 1200 | CLK_INIT(gcc_blsp1_uart3_apps_clk.c), |
| 1201 | }, |
| 1202 | }; |
| 1203 | |
| 1204 | static struct branch_clk gcc_blsp1_uart4_apps_clk = { |
| 1205 | .cbcr_reg = BLSP1_UART4_APPS_CBCR, |
| 1206 | .has_sibling = 0, |
| 1207 | .base = &virt_bases[GCC_BASE], |
| 1208 | .c = { |
| 1209 | .dbg_name = "gcc_blsp1_uart4_apps_clk", |
| 1210 | .parent = &blsp1_uart4_apps_clk_src.c, |
| 1211 | .ops = &clk_ops_branch, |
| 1212 | CLK_INIT(gcc_blsp1_uart4_apps_clk.c), |
| 1213 | }, |
| 1214 | }; |
| 1215 | |
| 1216 | static struct branch_clk gcc_blsp1_uart5_apps_clk = { |
| 1217 | .cbcr_reg = BLSP1_UART5_APPS_CBCR, |
| 1218 | .has_sibling = 0, |
| 1219 | .base = &virt_bases[GCC_BASE], |
| 1220 | .c = { |
| 1221 | .dbg_name = "gcc_blsp1_uart5_apps_clk", |
| 1222 | .parent = &blsp1_uart5_apps_clk_src.c, |
| 1223 | .ops = &clk_ops_branch, |
| 1224 | CLK_INIT(gcc_blsp1_uart5_apps_clk.c), |
| 1225 | }, |
| 1226 | }; |
| 1227 | |
| 1228 | static struct branch_clk gcc_blsp1_uart6_apps_clk = { |
| 1229 | .cbcr_reg = BLSP1_UART6_APPS_CBCR, |
| 1230 | .has_sibling = 0, |
| 1231 | .base = &virt_bases[GCC_BASE], |
| 1232 | .c = { |
| 1233 | .dbg_name = "gcc_blsp1_uart6_apps_clk", |
| 1234 | .parent = &blsp1_uart6_apps_clk_src.c, |
| 1235 | .ops = &clk_ops_branch, |
| 1236 | CLK_INIT(gcc_blsp1_uart6_apps_clk.c), |
| 1237 | }, |
| 1238 | }; |
| 1239 | |
| 1240 | static struct local_vote_clk gcc_boot_rom_ahb_clk = { |
| 1241 | .cbcr_reg = BOOT_ROM_AHB_CBCR, |
| 1242 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1243 | .en_mask = BIT(10), |
| 1244 | .base = &virt_bases[GCC_BASE], |
| 1245 | .c = { |
| 1246 | .dbg_name = "gcc_boot_rom_ahb_clk", |
| 1247 | .ops = &clk_ops_vote, |
| 1248 | CLK_INIT(gcc_boot_rom_ahb_clk.c), |
| 1249 | }, |
| 1250 | }; |
| 1251 | |
| 1252 | static struct local_vote_clk gcc_ce1_ahb_clk = { |
| 1253 | .cbcr_reg = CE1_AHB_CBCR, |
| 1254 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1255 | .en_mask = BIT(3), |
| 1256 | .base = &virt_bases[GCC_BASE], |
| 1257 | .c = { |
| 1258 | .dbg_name = "gcc_ce1_ahb_clk", |
| 1259 | .ops = &clk_ops_vote, |
| 1260 | CLK_INIT(gcc_ce1_ahb_clk.c), |
| 1261 | }, |
| 1262 | }; |
| 1263 | |
| 1264 | static struct local_vote_clk gcc_ce1_axi_clk = { |
| 1265 | .cbcr_reg = CE1_AXI_CBCR, |
| 1266 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1267 | .en_mask = BIT(4), |
| 1268 | .base = &virt_bases[GCC_BASE], |
| 1269 | .c = { |
| 1270 | .dbg_name = "gcc_ce1_axi_clk", |
| 1271 | .ops = &clk_ops_vote, |
| 1272 | CLK_INIT(gcc_ce1_axi_clk.c), |
| 1273 | }, |
| 1274 | }; |
| 1275 | |
| 1276 | static struct local_vote_clk gcc_ce1_clk = { |
| 1277 | .cbcr_reg = CE1_CBCR, |
| 1278 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1279 | .en_mask = BIT(5), |
| 1280 | .base = &virt_bases[GCC_BASE], |
| 1281 | .c = { |
Vikram Mulukutla | 1ed9e11 | 2013-11-01 18:36:13 -0700 | [diff] [blame] | 1282 | .parent = &ce1_clk_src.c, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1283 | .dbg_name = "gcc_ce1_clk", |
| 1284 | .ops = &clk_ops_vote, |
| 1285 | CLK_INIT(gcc_ce1_clk.c), |
| 1286 | }, |
| 1287 | }; |
| 1288 | |
| 1289 | static struct branch_clk gcc_gp1_clk = { |
| 1290 | .cbcr_reg = GP1_CBCR, |
| 1291 | .has_sibling = 0, |
| 1292 | .base = &virt_bases[GCC_BASE], |
| 1293 | .c = { |
| 1294 | .dbg_name = "gcc_gp1_clk", |
| 1295 | .parent = &gp1_clk_src.c, |
| 1296 | .ops = &clk_ops_branch, |
| 1297 | CLK_INIT(gcc_gp1_clk.c), |
| 1298 | }, |
| 1299 | }; |
| 1300 | |
| 1301 | static struct branch_clk gcc_gp2_clk = { |
| 1302 | .cbcr_reg = GP2_CBCR, |
| 1303 | .has_sibling = 0, |
| 1304 | .base = &virt_bases[GCC_BASE], |
| 1305 | .c = { |
| 1306 | .dbg_name = "gcc_gp2_clk", |
| 1307 | .parent = &gp2_clk_src.c, |
| 1308 | .ops = &clk_ops_branch, |
| 1309 | CLK_INIT(gcc_gp2_clk.c), |
| 1310 | }, |
| 1311 | }; |
| 1312 | |
| 1313 | static struct branch_clk gcc_gp3_clk = { |
| 1314 | .cbcr_reg = GP3_CBCR, |
| 1315 | .has_sibling = 0, |
| 1316 | .base = &virt_bases[GCC_BASE], |
| 1317 | .c = { |
| 1318 | .dbg_name = "gcc_gp3_clk", |
| 1319 | .parent = &gp3_clk_src.c, |
| 1320 | .ops = &clk_ops_branch, |
| 1321 | CLK_INIT(gcc_gp3_clk.c), |
| 1322 | }, |
| 1323 | }; |
| 1324 | |
| 1325 | static struct branch_clk gcc_lpass_q6_axi_clk = { |
| 1326 | .cbcr_reg = LPASS_Q6_AXI_CBCR, |
| 1327 | .has_sibling = 1, |
| 1328 | .base = &virt_bases[GCC_BASE], |
| 1329 | .c = { |
| 1330 | .dbg_name = "gcc_lpass_q6_axi_clk", |
| 1331 | .ops = &clk_ops_branch, |
| 1332 | CLK_INIT(gcc_lpass_q6_axi_clk.c), |
| 1333 | }, |
| 1334 | }; |
| 1335 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1336 | static struct branch_clk gcc_mss_cfg_ahb_clk = { |
| 1337 | .cbcr_reg = MSS_CFG_AHB_CBCR, |
| 1338 | .has_sibling = 1, |
| 1339 | .base = &virt_bases[GCC_BASE], |
| 1340 | .c = { |
| 1341 | .dbg_name = "gcc_mss_cfg_ahb_clk", |
| 1342 | .ops = &clk_ops_branch, |
| 1343 | CLK_INIT(gcc_mss_cfg_ahb_clk.c), |
| 1344 | }, |
| 1345 | }; |
| 1346 | |
| 1347 | static struct branch_clk gcc_mss_q6_bimc_axi_clk = { |
| 1348 | .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR, |
| 1349 | .has_sibling = 1, |
| 1350 | .base = &virt_bases[GCC_BASE], |
| 1351 | .c = { |
| 1352 | .dbg_name = "gcc_mss_q6_bimc_axi_clk", |
| 1353 | .ops = &clk_ops_branch, |
| 1354 | CLK_INIT(gcc_mss_q6_bimc_axi_clk.c), |
| 1355 | }, |
| 1356 | }; |
| 1357 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1358 | static struct branch_clk gcc_pdm2_clk = { |
| 1359 | .cbcr_reg = PDM2_CBCR, |
| 1360 | .has_sibling = 0, |
| 1361 | .base = &virt_bases[GCC_BASE], |
| 1362 | .c = { |
| 1363 | .dbg_name = "gcc_pdm2_clk", |
| 1364 | .parent = &pdm2_clk_src.c, |
| 1365 | .ops = &clk_ops_branch, |
| 1366 | CLK_INIT(gcc_pdm2_clk.c), |
| 1367 | }, |
| 1368 | }; |
| 1369 | |
| 1370 | static struct branch_clk gcc_pdm_ahb_clk = { |
| 1371 | .cbcr_reg = PDM_AHB_CBCR, |
| 1372 | .has_sibling = 1, |
| 1373 | .base = &virt_bases[GCC_BASE], |
| 1374 | .c = { |
| 1375 | .dbg_name = "gcc_pdm_ahb_clk", |
| 1376 | .ops = &clk_ops_branch, |
| 1377 | CLK_INIT(gcc_pdm_ahb_clk.c), |
| 1378 | }, |
| 1379 | }; |
| 1380 | |
| 1381 | static struct branch_clk gcc_pdm_xo4_clk = { |
| 1382 | .cbcr_reg = PDM_XO4_CBCR, |
| 1383 | .has_sibling = 1, |
| 1384 | .base = &virt_bases[GCC_BASE], |
| 1385 | .c = { |
| 1386 | .dbg_name = "gcc_pdm_xo4_clk", |
| 1387 | .parent = &xo.c, |
| 1388 | .ops = &clk_ops_branch, |
| 1389 | CLK_INIT(gcc_pdm_xo4_clk.c), |
| 1390 | }, |
| 1391 | }; |
| 1392 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1393 | static struct local_vote_clk gcc_prng_ahb_clk = { |
| 1394 | .cbcr_reg = PRNG_AHB_CBCR, |
| 1395 | .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE, |
| 1396 | .en_mask = BIT(13), |
| 1397 | .base = &virt_bases[GCC_BASE], |
| 1398 | .c = { |
| 1399 | .dbg_name = "gcc_prng_ahb_clk", |
| 1400 | .ops = &clk_ops_vote, |
| 1401 | CLK_INIT(gcc_prng_ahb_clk.c), |
| 1402 | }, |
| 1403 | }; |
| 1404 | |
| 1405 | static struct branch_clk gcc_sdcc1_ahb_clk = { |
| 1406 | .cbcr_reg = SDCC1_AHB_CBCR, |
| 1407 | .has_sibling = 1, |
| 1408 | .base = &virt_bases[GCC_BASE], |
| 1409 | .c = { |
| 1410 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 1411 | .ops = &clk_ops_branch, |
| 1412 | CLK_INIT(gcc_sdcc1_ahb_clk.c), |
| 1413 | }, |
| 1414 | }; |
| 1415 | |
| 1416 | static struct branch_clk gcc_sdcc1_apps_clk = { |
| 1417 | .cbcr_reg = SDCC1_APPS_CBCR, |
| 1418 | .has_sibling = 0, |
| 1419 | .base = &virt_bases[GCC_BASE], |
| 1420 | .c = { |
| 1421 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 1422 | .parent = &sdcc1_apps_clk_src.c, |
| 1423 | .ops = &clk_ops_branch, |
| 1424 | CLK_INIT(gcc_sdcc1_apps_clk.c), |
| 1425 | }, |
| 1426 | }; |
| 1427 | |
| 1428 | static struct branch_clk gcc_sdcc2_ahb_clk = { |
| 1429 | .cbcr_reg = SDCC2_AHB_CBCR, |
| 1430 | .has_sibling = 1, |
| 1431 | .base = &virt_bases[GCC_BASE], |
| 1432 | .c = { |
| 1433 | .dbg_name = "gcc_sdcc2_ahb_clk", |
| 1434 | .ops = &clk_ops_branch, |
| 1435 | CLK_INIT(gcc_sdcc2_ahb_clk.c), |
| 1436 | }, |
| 1437 | }; |
| 1438 | |
| 1439 | static struct branch_clk gcc_sdcc2_apps_clk = { |
| 1440 | .cbcr_reg = SDCC2_APPS_CBCR, |
| 1441 | .has_sibling = 0, |
| 1442 | .base = &virt_bases[GCC_BASE], |
| 1443 | .c = { |
| 1444 | .dbg_name = "gcc_sdcc2_apps_clk", |
| 1445 | .parent = &sdcc2_apps_clk_src.c, |
| 1446 | .ops = &clk_ops_branch, |
| 1447 | CLK_INIT(gcc_sdcc2_apps_clk.c), |
| 1448 | }, |
| 1449 | }; |
| 1450 | |
| 1451 | static struct branch_clk gcc_sdcc3_ahb_clk = { |
| 1452 | .cbcr_reg = SDCC3_AHB_CBCR, |
| 1453 | .has_sibling = 1, |
| 1454 | .base = &virt_bases[GCC_BASE], |
| 1455 | .c = { |
| 1456 | .dbg_name = "gcc_sdcc3_ahb_clk", |
| 1457 | .ops = &clk_ops_branch, |
| 1458 | CLK_INIT(gcc_sdcc3_ahb_clk.c), |
| 1459 | }, |
| 1460 | }; |
| 1461 | |
| 1462 | static struct branch_clk gcc_sdcc3_apps_clk = { |
| 1463 | .cbcr_reg = SDCC3_APPS_CBCR, |
| 1464 | .has_sibling = 0, |
| 1465 | .base = &virt_bases[GCC_BASE], |
| 1466 | .c = { |
| 1467 | .dbg_name = "gcc_sdcc3_apps_clk", |
| 1468 | .parent = &sdcc3_apps_clk_src.c, |
| 1469 | .ops = &clk_ops_branch, |
| 1470 | CLK_INIT(gcc_sdcc3_apps_clk.c), |
| 1471 | }, |
| 1472 | }; |
| 1473 | |
| 1474 | static struct branch_clk gcc_usb2a_phy_sleep_clk = { |
| 1475 | .cbcr_reg = USB2A_PHY_SLEEP_CBCR, |
| 1476 | .has_sibling = 1, |
| 1477 | .base = &virt_bases[GCC_BASE], |
| 1478 | .c = { |
| 1479 | .dbg_name = "gcc_usb2a_phy_sleep_clk", |
| 1480 | .ops = &clk_ops_branch, |
| 1481 | CLK_INIT(gcc_usb2a_phy_sleep_clk.c), |
| 1482 | }, |
| 1483 | }; |
| 1484 | |
| 1485 | static struct branch_clk gcc_usb_hs_ahb_clk = { |
| 1486 | .cbcr_reg = USB_HS_AHB_CBCR, |
| 1487 | .has_sibling = 1, |
| 1488 | .base = &virt_bases[GCC_BASE], |
| 1489 | .c = { |
| 1490 | .dbg_name = "gcc_usb_hs_ahb_clk", |
| 1491 | .ops = &clk_ops_branch, |
| 1492 | CLK_INIT(gcc_usb_hs_ahb_clk.c), |
| 1493 | }, |
| 1494 | }; |
| 1495 | |
| 1496 | static struct branch_clk gcc_usb_hs_system_clk = { |
| 1497 | .cbcr_reg = USB_HS_SYSTEM_CBCR, |
| 1498 | .has_sibling = 0, |
| 1499 | .bcr_reg = USB_HS_BCR, |
| 1500 | .base = &virt_bases[GCC_BASE], |
| 1501 | .c = { |
| 1502 | .dbg_name = "gcc_usb_hs_system_clk", |
| 1503 | .parent = &usb_hs_system_clk_src.c, |
| 1504 | .ops = &clk_ops_branch, |
| 1505 | CLK_INIT(gcc_usb_hs_system_clk.c), |
| 1506 | }, |
| 1507 | }; |
| 1508 | |
| 1509 | static struct branch_clk gcc_usb_hsic_ahb_clk = { |
| 1510 | .cbcr_reg = USB_HSIC_AHB_CBCR, |
| 1511 | .has_sibling = 1, |
| 1512 | .base = &virt_bases[GCC_BASE], |
| 1513 | .c = { |
| 1514 | .dbg_name = "gcc_usb_hsic_ahb_clk", |
| 1515 | .ops = &clk_ops_branch, |
| 1516 | CLK_INIT(gcc_usb_hsic_ahb_clk.c), |
| 1517 | }, |
| 1518 | }; |
| 1519 | |
| 1520 | static struct branch_clk gcc_usb_hsic_clk = { |
| 1521 | .cbcr_reg = USB_HSIC_CBCR, |
| 1522 | .has_sibling = 0, |
| 1523 | .bcr_reg = USB_HS_HSIC_BCR, |
| 1524 | .base = &virt_bases[GCC_BASE], |
| 1525 | .c = { |
| 1526 | .dbg_name = "gcc_usb_hsic_clk", |
| 1527 | .parent = &usb_hsic_clk_src.c, |
| 1528 | .ops = &clk_ops_branch, |
| 1529 | CLK_INIT(gcc_usb_hsic_clk.c), |
| 1530 | }, |
| 1531 | }; |
| 1532 | |
| 1533 | static struct branch_clk gcc_usb_hsic_io_cal_clk = { |
| 1534 | .cbcr_reg = USB_HSIC_IO_CAL_CBCR, |
| 1535 | .has_sibling = 0, |
| 1536 | .base = &virt_bases[GCC_BASE], |
| 1537 | .c = { |
| 1538 | .dbg_name = "gcc_usb_hsic_io_cal_clk", |
| 1539 | .parent = &usb_hsic_io_cal_clk_src.c, |
| 1540 | .ops = &clk_ops_branch, |
| 1541 | CLK_INIT(gcc_usb_hsic_io_cal_clk.c), |
| 1542 | }, |
| 1543 | }; |
| 1544 | |
| 1545 | static struct branch_clk gcc_usb_hsic_system_clk = { |
| 1546 | .cbcr_reg = USB_HSIC_SYSTEM_CBCR, |
| 1547 | .has_sibling = 0, |
| 1548 | .bcr_reg = USB_HS_HSIC_BCR, |
| 1549 | .base = &virt_bases[GCC_BASE], |
| 1550 | .c = { |
| 1551 | .dbg_name = "gcc_usb_hsic_system_clk", |
| 1552 | .parent = &usb_hsic_system_clk_src.c, |
| 1553 | .ops = &clk_ops_branch, |
| 1554 | CLK_INIT(gcc_usb_hsic_system_clk.c), |
| 1555 | }, |
| 1556 | }; |
| 1557 | |
Vikram Mulukutla | 8da6c84 | 2013-12-18 17:26:01 -0800 | [diff] [blame] | 1558 | static DEFINE_CLK_MEASURE(wcnss_m_clk); |
| 1559 | |
Patrick Daly | 54a5c2f | 2013-10-07 17:36:37 -0700 | [diff] [blame] | 1560 | #ifdef CONFIG_DEBUG_FS |
| 1561 | struct measure_mux_entry { |
| 1562 | struct clk *c; |
| 1563 | int base; |
| 1564 | u32 debug_mux; |
| 1565 | }; |
| 1566 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1567 | static struct measure_mux_entry measure_mux_GCC[] = { |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1568 | { &gcc_mss_cfg_ahb_clk.c, GCC_BASE, 0x0030 }, |
| 1569 | { &gcc_mss_q6_bimc_axi_clk.c, GCC_BASE, 0x0031 }, |
| 1570 | { &gcc_usb_hsic_ahb_clk.c, GCC_BASE, 0x0058 }, |
| 1571 | { &gcc_usb_hsic_system_clk.c, GCC_BASE, 0x0059 }, |
| 1572 | { &gcc_usb_hsic_clk.c, GCC_BASE, 0x005a }, |
| 1573 | { &gcc_usb_hsic_io_cal_clk.c, GCC_BASE, 0x005b }, |
| 1574 | { &gcc_usb_hs_system_clk.c, GCC_BASE, 0x0060 }, |
| 1575 | { &gcc_usb_hs_ahb_clk.c, GCC_BASE, 0x0061 }, |
| 1576 | { &gcc_usb2a_phy_sleep_clk.c, GCC_BASE, 0x0063 }, |
| 1577 | { &gcc_sdcc1_apps_clk.c, GCC_BASE, 0x0068 }, |
| 1578 | { &gcc_sdcc1_ahb_clk.c, GCC_BASE, 0x0069 }, |
| 1579 | { &gcc_sdcc2_apps_clk.c, GCC_BASE, 0x0070 }, |
| 1580 | { &gcc_sdcc2_ahb_clk.c, GCC_BASE, 0x0071 }, |
| 1581 | { &gcc_sdcc3_apps_clk.c, GCC_BASE, 0x0078 }, |
| 1582 | { &gcc_sdcc3_ahb_clk.c, GCC_BASE, 0x0079 }, |
| 1583 | { &gcc_blsp1_ahb_clk.c, GCC_BASE, 0x0088 }, |
| 1584 | { &gcc_blsp1_qup1_spi_apps_clk.c, GCC_BASE, 0x008a }, |
| 1585 | { &gcc_blsp1_qup1_i2c_apps_clk.c, GCC_BASE, 0x008b }, |
| 1586 | { &gcc_blsp1_uart1_apps_clk.c, GCC_BASE, 0x008c }, |
| 1587 | { &gcc_blsp1_qup2_spi_apps_clk.c, GCC_BASE, 0x008e }, |
| 1588 | { &gcc_blsp1_qup2_i2c_apps_clk.c, GCC_BASE, 0x0090 }, |
| 1589 | { &gcc_blsp1_uart2_apps_clk.c, GCC_BASE, 0x0091 }, |
| 1590 | { &gcc_blsp1_qup3_spi_apps_clk.c, GCC_BASE, 0x0093 }, |
| 1591 | { &gcc_blsp1_qup3_i2c_apps_clk.c, GCC_BASE, 0x0094 }, |
| 1592 | { &gcc_blsp1_uart3_apps_clk.c, GCC_BASE, 0x0095 }, |
| 1593 | { &gcc_blsp1_qup4_spi_apps_clk.c, GCC_BASE, 0x0098 }, |
| 1594 | { &gcc_blsp1_qup4_i2c_apps_clk.c, GCC_BASE, 0x0099 }, |
| 1595 | { &gcc_blsp1_uart4_apps_clk.c, GCC_BASE, 0x009a }, |
| 1596 | { &gcc_blsp1_qup5_spi_apps_clk.c, GCC_BASE, 0x009c }, |
| 1597 | { &gcc_blsp1_qup5_i2c_apps_clk.c, GCC_BASE, 0x009d }, |
| 1598 | { &gcc_blsp1_uart5_apps_clk.c, GCC_BASE, 0x009e }, |
| 1599 | { &gcc_blsp1_qup6_spi_apps_clk.c, GCC_BASE, 0x00a1 }, |
| 1600 | { &gcc_blsp1_qup6_i2c_apps_clk.c, GCC_BASE, 0x00a2 }, |
| 1601 | { &gcc_blsp1_uart6_apps_clk.c, GCC_BASE, 0x00a3 }, |
| 1602 | { &gcc_pdm_ahb_clk.c, GCC_BASE, 0x00d0 }, |
| 1603 | { &gcc_pdm_xo4_clk.c, GCC_BASE, 0x00d1 }, |
| 1604 | { &gcc_pdm2_clk.c, GCC_BASE, 0x00d2 }, |
| 1605 | { &gcc_prng_ahb_clk.c, GCC_BASE, 0x00d8 }, |
| 1606 | { &gcc_bam_dma_ahb_clk.c, GCC_BASE, 0x00e0 }, |
| 1607 | { &gcc_boot_rom_ahb_clk.c, GCC_BASE, 0x00f8 }, |
| 1608 | { &gcc_ce1_clk.c, GCC_BASE, 0x0138 }, |
| 1609 | { &gcc_ce1_axi_clk.c, GCC_BASE, 0x0139 }, |
| 1610 | { &gcc_ce1_ahb_clk.c, GCC_BASE, 0x013a }, |
| 1611 | { &gcc_lpass_q6_axi_clk.c, GCC_BASE, 0x0160 }, |
Patrick Daly | 2a4ba83 | 2013-07-17 12:52:40 -0700 | [diff] [blame] | 1612 | { &pnoc_clk.c, GCC_BASE, 0x010}, |
| 1613 | { &snoc_clk.c, GCC_BASE, 0x000}, |
| 1614 | { &cnoc_clk.c, GCC_BASE, 0x008}, |
Vikram Mulukutla | 8da6c84 | 2013-12-18 17:26:01 -0800 | [diff] [blame] | 1615 | { &wcnss_m_clk, GCC_BASE, 0x0198}, |
Patrick Daly | 2a4ba83 | 2013-07-17 12:52:40 -0700 | [diff] [blame] | 1616 | /* |
| 1617 | * measure the gcc_bimc_kpss_axi_clk instead to account for the DDR |
| 1618 | * rate being gcc_bimc_clk/2. |
| 1619 | */ |
| 1620 | { &bimc_clk.c, GCC_BASE, 0x155}, |
| 1621 | { &dummy_clk, N_BASES, 0x0000}, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1622 | }; |
Patrick Daly | 54a5c2f | 2013-10-07 17:36:37 -0700 | [diff] [blame] | 1623 | #endif /* CONFIG_DEBUG_FS */ |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1624 | |
| 1625 | static struct pll_vote_clk mmpll0_pll = { |
| 1626 | .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS, |
| 1627 | .en_mask = BIT(0), |
| 1628 | .status_reg = (void __iomem *)MMPLL0_PLL_STATUS, |
| 1629 | .status_mask = BIT(17), |
| 1630 | .base = &virt_bases[MMSS_BASE], |
| 1631 | .c = { |
| 1632 | .rate = 800000000, |
| 1633 | .parent = &xo.c, |
| 1634 | .dbg_name = "mmpll0_pll", |
| 1635 | .ops = &clk_ops_pll_vote, |
| 1636 | CLK_INIT(mmpll0_pll.c), |
| 1637 | }, |
| 1638 | }; |
| 1639 | |
| 1640 | static struct pll_vote_clk mmpll1_pll = { |
| 1641 | .en_reg = (void __iomem *)MMSS_PLL_VOTE_APCS, |
| 1642 | .en_mask = BIT(1), |
| 1643 | .status_reg = (void __iomem *)MMPLL1_PLL_STATUS, |
| 1644 | .status_mask = BIT(17), |
| 1645 | .base = &virt_bases[MMSS_BASE], |
| 1646 | .c = { |
| 1647 | .rate = 1000000000, |
| 1648 | .parent = &xo.c, |
| 1649 | .dbg_name = "mmpll1_pll", |
| 1650 | .ops = &clk_ops_pll_vote, |
| 1651 | CLK_INIT(mmpll1_pll.c), |
| 1652 | }, |
| 1653 | }; |
| 1654 | |
| 1655 | static struct clk_freq_tbl ftbl_mmss_mmssnoc_axi_clk[] = { |
| 1656 | F_MMSS( 19200000, xo, 1, 0, 0), |
| 1657 | F_MMSS( 37500000, gpll0, 16, 0, 0), |
| 1658 | F_MMSS( 50000000, gpll0, 12, 0, 0), |
| 1659 | F_MMSS( 75000000, gpll0, 8, 0, 0), |
| 1660 | F_MMSS( 100000000, gpll0, 6, 0, 0), |
| 1661 | F_MMSS( 150000000, gpll0, 4, 0, 0), |
| 1662 | F_MMSS( 200000000, mmpll0_pll, 4, 0, 0), |
pfang | 948c93e | 2013-03-20 17:04:18 -0700 | [diff] [blame] | 1663 | F_MMSS( 266666666, mmpll0_pll, 3, 0, 0), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1664 | F_END |
| 1665 | }; |
| 1666 | |
| 1667 | static struct rcg_clk axi_clk_src = { |
| 1668 | .cmd_rcgr_reg = AXI_CMD_RCGR, |
| 1669 | .set_rate = set_rate_hid, |
| 1670 | .freq_tbl = ftbl_mmss_mmssnoc_axi_clk, |
| 1671 | .current_freq = &rcg_dummy_freq, |
| 1672 | .base = &virt_bases[MMSS_BASE], |
| 1673 | .c = { |
| 1674 | .dbg_name = "axi_clk_src", |
| 1675 | .ops = &clk_ops_rcg, |
| 1676 | VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000, HIGH, |
Patrick Daly | e02a563 | 2013-02-12 20:23:35 -0800 | [diff] [blame] | 1677 | 266670000), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1678 | CLK_INIT(axi_clk_src.c), |
| 1679 | }, |
| 1680 | }; |
| 1681 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1682 | static struct clk_freq_tbl ftbl_camss_csi0_1_clk[] = { |
| 1683 | F_MMSS( 100000000, gpll0, 6, 0, 0), |
| 1684 | F_MMSS( 200000000, mmpll0_pll, 4, 0, 0), |
| 1685 | F_END |
| 1686 | }; |
| 1687 | |
| 1688 | static struct rcg_clk csi0_clk_src = { |
| 1689 | .cmd_rcgr_reg = CSI0_CMD_RCGR, |
| 1690 | .set_rate = set_rate_hid, |
| 1691 | .freq_tbl = ftbl_camss_csi0_1_clk, |
| 1692 | .current_freq = &rcg_dummy_freq, |
| 1693 | .base = &virt_bases[MMSS_BASE], |
| 1694 | .c = { |
| 1695 | .dbg_name = "csi0_clk_src", |
| 1696 | .ops = &clk_ops_rcg, |
| 1697 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1698 | CLK_INIT(csi0_clk_src.c), |
| 1699 | }, |
| 1700 | }; |
| 1701 | |
| 1702 | static struct rcg_clk csi1_clk_src = { |
| 1703 | .cmd_rcgr_reg = CSI1_CMD_RCGR, |
| 1704 | .set_rate = set_rate_hid, |
| 1705 | .freq_tbl = ftbl_camss_csi0_1_clk, |
| 1706 | .current_freq = &rcg_dummy_freq, |
| 1707 | .base = &virt_bases[MMSS_BASE], |
| 1708 | .c = { |
| 1709 | .dbg_name = "csi1_clk_src", |
| 1710 | .ops = &clk_ops_rcg, |
| 1711 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1712 | CLK_INIT(csi1_clk_src.c), |
| 1713 | }, |
| 1714 | }; |
| 1715 | |
| 1716 | static struct clk_freq_tbl ftbl_camss_vfe_vfe0_clk[] = { |
| 1717 | F_MMSS( 37500000, gpll0, 16, 0, 0), |
| 1718 | F_MMSS( 50000000, gpll0, 12, 0, 0), |
| 1719 | F_MMSS( 60000000, gpll0, 10, 0, 0), |
| 1720 | F_MMSS( 80000000, gpll0, 7.5, 0, 0), |
| 1721 | F_MMSS( 100000000, gpll0, 6, 0, 0), |
| 1722 | F_MMSS( 109090000, gpll0, 5.5, 0, 0), |
| 1723 | F_MMSS( 133330000, gpll0, 4.5, 0, 0), |
Patrick Daly | d3fd03f | 2013-03-08 19:01:18 -0800 | [diff] [blame] | 1724 | F_MMSS( 150000000, gpll0, 4, 0, 0), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1725 | F_MMSS( 200000000, gpll0, 3, 0, 0), |
| 1726 | F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0), |
| 1727 | F_MMSS( 266670000, mmpll0_pll, 3, 0, 0), |
| 1728 | F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0), |
Patrick Daly | d3fd03f | 2013-03-08 19:01:18 -0800 | [diff] [blame] | 1729 | F_MMSS( 400000000, mmpll0_pll, 2, 0, 0), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1730 | F_END |
| 1731 | }; |
| 1732 | |
Patrick Daly | d3fd03f | 2013-03-08 19:01:18 -0800 | [diff] [blame] | 1733 | static unsigned long camss_vfe_vfe0_fmax_v2[VDD_DIG_NUM] = { |
| 1734 | 150000000, 320000000, 400000000, |
| 1735 | }; |
| 1736 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1737 | static struct rcg_clk vfe0_clk_src = { |
| 1738 | .cmd_rcgr_reg = VFE0_CMD_RCGR, |
| 1739 | .set_rate = set_rate_hid, |
| 1740 | .freq_tbl = ftbl_camss_vfe_vfe0_clk, |
| 1741 | .current_freq = &rcg_dummy_freq, |
| 1742 | .base = &virt_bases[MMSS_BASE], |
| 1743 | .c = { |
| 1744 | .dbg_name = "vfe0_clk_src", |
| 1745 | .ops = &clk_ops_rcg, |
| 1746 | VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH, |
Patrick Daly | e02a563 | 2013-02-12 20:23:35 -0800 | [diff] [blame] | 1747 | 320000000), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1748 | CLK_INIT(vfe0_clk_src.c), |
| 1749 | }, |
| 1750 | }; |
| 1751 | |
| 1752 | static struct clk_freq_tbl ftbl_mdss_mdp_clk[] = { |
| 1753 | F_MMSS( 37500000, gpll0, 16, 0, 0), |
| 1754 | F_MMSS( 60000000, gpll0, 10, 0, 0), |
| 1755 | F_MMSS( 75000000, gpll0, 8, 0, 0), |
| 1756 | F_MMSS( 92310000, gpll0, 6.5, 0, 0), |
| 1757 | F_MMSS( 100000000, gpll0, 6, 0, 0), |
| 1758 | F_MMSS( 133330000, mmpll0_pll, 6, 0, 0), |
| 1759 | F_MMSS( 177780000, mmpll0_pll, 4.5, 0, 0), |
| 1760 | F_MMSS( 200000000, mmpll0_pll, 4, 0, 0), |
| 1761 | F_END |
| 1762 | }; |
| 1763 | |
| 1764 | static struct rcg_clk mdp_clk_src = { |
| 1765 | .cmd_rcgr_reg = MDP_CMD_RCGR, |
| 1766 | .set_rate = set_rate_hid, |
| 1767 | .freq_tbl = ftbl_mdss_mdp_clk, |
| 1768 | .current_freq = &rcg_dummy_freq, |
| 1769 | .base = &virt_bases[MMSS_BASE], |
| 1770 | .c = { |
| 1771 | .dbg_name = "mdp_clk_src", |
| 1772 | .ops = &clk_ops_rcg, |
| 1773 | VDD_DIG_FMAX_MAP3(LOW, 92310000, NOMINAL, 177780000, HIGH, |
Patrick Daly | e02a563 | 2013-02-12 20:23:35 -0800 | [diff] [blame] | 1774 | 200000000), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1775 | CLK_INIT(mdp_clk_src.c), |
| 1776 | }, |
| 1777 | }; |
| 1778 | |
| 1779 | static struct clk_freq_tbl ftbl_camss_jpeg_jpeg0_clk[] = { |
| 1780 | F_MMSS( 75000000, gpll0, 8, 0, 0), |
| 1781 | F_MMSS( 133330000, gpll0, 4.5, 0, 0), |
| 1782 | F_MMSS( 200000000, gpll0, 3, 0, 0), |
| 1783 | F_MMSS( 228570000, mmpll0_pll, 3.5, 0, 0), |
| 1784 | F_MMSS( 266670000, mmpll0_pll, 3, 0, 0), |
| 1785 | F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0), |
| 1786 | F_END |
| 1787 | }; |
| 1788 | |
| 1789 | static struct rcg_clk jpeg0_clk_src = { |
| 1790 | .cmd_rcgr_reg = JPEG0_CMD_RCGR, |
| 1791 | .set_rate = set_rate_hid, |
| 1792 | .freq_tbl = ftbl_camss_jpeg_jpeg0_clk, |
| 1793 | .current_freq = &rcg_dummy_freq, |
| 1794 | .base = &virt_bases[MMSS_BASE], |
| 1795 | .c = { |
| 1796 | .dbg_name = "jpeg0_clk_src", |
| 1797 | .ops = &clk_ops_rcg, |
| 1798 | VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH, |
Patrick Daly | e02a563 | 2013-02-12 20:23:35 -0800 | [diff] [blame] | 1799 | 320000000), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1800 | CLK_INIT(jpeg0_clk_src.c), |
| 1801 | }, |
| 1802 | }; |
| 1803 | |
Aravind Venkateswaran | 78b7325 | 2013-05-08 18:25:21 -0700 | [diff] [blame] | 1804 | struct clk_ops clk_ops_pixel_clock; |
Patrick Daly | 5555c2c | 2013-03-06 21:25:26 -0800 | [diff] [blame] | 1805 | |
Aravind Venkateswaran | 78b7325 | 2013-05-08 18:25:21 -0700 | [diff] [blame] | 1806 | static long round_rate_pixel(struct clk *clk, unsigned long rate) |
| 1807 | { |
| 1808 | int frac_num[] = {3, 2, 4, 1}; |
| 1809 | int frac_den[] = {8, 9, 9, 1}; |
| 1810 | int delta = 100000; |
| 1811 | int i; |
| 1812 | |
| 1813 | for (i = 0; i < ARRAY_SIZE(frac_num); i++) { |
| 1814 | unsigned long request = (rate * frac_den[i]) / frac_num[i]; |
| 1815 | unsigned long src_rate; |
| 1816 | |
| 1817 | src_rate = clk_round_rate(clk->parent, request); |
| 1818 | if ((src_rate < (request - delta)) || |
| 1819 | (src_rate > (request + delta))) |
| 1820 | continue; |
| 1821 | |
| 1822 | return (src_rate * frac_num[i]) / frac_den[i]; |
| 1823 | } |
| 1824 | |
| 1825 | return -EINVAL; |
| 1826 | } |
| 1827 | |
| 1828 | |
| 1829 | static int set_rate_pixel(struct clk *clk, unsigned long rate) |
| 1830 | { |
| 1831 | struct rcg_clk *rcg = to_rcg_clk(clk); |
| 1832 | struct clk_freq_tbl *pixel_freq = rcg->current_freq; |
| 1833 | int frac_num[] = {3, 2, 4, 1}; |
| 1834 | int frac_den[] = {8, 9, 9, 1}; |
| 1835 | int delta = 100000; |
| 1836 | int i, rc; |
| 1837 | |
| 1838 | for (i = 0; i < ARRAY_SIZE(frac_num); i++) { |
| 1839 | unsigned long request = (rate * frac_den[i]) / frac_num[i]; |
| 1840 | unsigned long src_rate; |
| 1841 | |
| 1842 | src_rate = clk_round_rate(clk->parent, request); |
| 1843 | if ((src_rate < (request - delta)) || |
| 1844 | (src_rate > (request + delta))) |
| 1845 | continue; |
| 1846 | |
| 1847 | rc = clk_set_rate(clk->parent, src_rate); |
| 1848 | if (rc) |
| 1849 | return rc; |
| 1850 | |
| 1851 | pixel_freq->div_src_val &= ~BM(4, 0); |
| 1852 | if (frac_den[i] == frac_num[i]) { |
| 1853 | pixel_freq->m_val = 0; |
| 1854 | pixel_freq->n_val = 0; |
| 1855 | } else { |
| 1856 | pixel_freq->m_val = frac_num[i]; |
| 1857 | pixel_freq->n_val = ~(frac_den[i] - frac_num[i]); |
| 1858 | pixel_freq->d_val = ~frac_den[i]; |
| 1859 | } |
| 1860 | set_rate_mnd(rcg, pixel_freq); |
| 1861 | return 0; |
| 1862 | } |
| 1863 | return -EINVAL; |
| 1864 | } |
Patrick Daly | 5555c2c | 2013-03-06 21:25:26 -0800 | [diff] [blame] | 1865 | |
Vikram Mulukutla | ae13f3c | 2013-03-20 18:03:29 -0700 | [diff] [blame] | 1866 | static struct clk_freq_tbl pixel_freq_tbl[] = { |
| 1867 | { |
Aravind Venkateswaran | 78b7325 | 2013-05-08 18:25:21 -0700 | [diff] [blame] | 1868 | .src_clk = &pixel_clk_src_8226.c, |
| 1869 | .div_src_val = BVAL(10, 8, dsipll0_pixel_mm_source_val) |
| 1870 | | BVAL(4, 0, 0), |
Vikram Mulukutla | ae13f3c | 2013-03-20 18:03:29 -0700 | [diff] [blame] | 1871 | }, |
| 1872 | F_END |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1873 | }; |
| 1874 | |
| 1875 | static struct rcg_clk pclk0_clk_src = { |
| 1876 | .cmd_rcgr_reg = PCLK0_CMD_RCGR, |
Vikram Mulukutla | ae13f3c | 2013-03-20 18:03:29 -0700 | [diff] [blame] | 1877 | .current_freq = pixel_freq_tbl, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1878 | .base = &virt_bases[MMSS_BASE], |
| 1879 | .c = { |
Aravind Venkateswaran | 78b7325 | 2013-05-08 18:25:21 -0700 | [diff] [blame] | 1880 | .parent = &pixel_clk_src_8226.c, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1881 | .dbg_name = "pclk0_clk_src", |
Patrick Daly | 5555c2c | 2013-03-06 21:25:26 -0800 | [diff] [blame] | 1882 | .ops = &clk_ops_pixel, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1883 | VDD_DIG_FMAX_MAP2(LOW, 83330000, NOMINAL, 166670000), |
| 1884 | CLK_INIT(pclk0_clk_src.c), |
| 1885 | }, |
| 1886 | }; |
| 1887 | |
| 1888 | static struct clk_freq_tbl ftbl_venus0_vcodec0_clk[] = { |
| 1889 | F_MMSS( 66700000, gpll0, 9, 0, 0), |
| 1890 | F_MMSS( 100000000, gpll0, 6, 0, 0), |
| 1891 | F_MMSS( 133330000, mmpll0_pll, 6, 0, 0), |
Patrick Daly | 4f83243 | 2013-02-26 12:40:49 -0800 | [diff] [blame] | 1892 | F_MMSS( 160000000, mmpll0_pll, 5, 0, 0), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1893 | F_END |
| 1894 | }; |
| 1895 | |
| 1896 | static struct rcg_clk vcodec0_clk_src = { |
| 1897 | .cmd_rcgr_reg = VCODEC0_CMD_RCGR, |
| 1898 | .set_rate = set_rate_mnd, |
| 1899 | .freq_tbl = ftbl_venus0_vcodec0_clk, |
| 1900 | .current_freq = &rcg_dummy_freq, |
| 1901 | .base = &virt_bases[MMSS_BASE], |
| 1902 | .c = { |
| 1903 | .dbg_name = "vcodec0_clk_src", |
| 1904 | .ops = &clk_ops_rcg_mnd, |
Patrick Daly | 59c7432 | 2013-06-07 12:00:42 -0700 | [diff] [blame] | 1905 | VDD_DIG_FMAX_MAP3(LOW, 66700000, NOMINAL, 133330000, HIGH, |
Patrick Daly | e02a563 | 2013-02-12 20:23:35 -0800 | [diff] [blame] | 1906 | 160000000), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1907 | CLK_INIT(vcodec0_clk_src.c), |
| 1908 | }, |
| 1909 | }; |
| 1910 | |
| 1911 | static struct clk_freq_tbl ftbl_camss_cci_cci_clk[] = { |
| 1912 | F_MMSS( 19200000, xo, 1, 0, 0), |
| 1913 | F_END |
| 1914 | }; |
| 1915 | |
| 1916 | static struct rcg_clk cci_clk_src = { |
| 1917 | .cmd_rcgr_reg = CCI_CMD_RCGR, |
| 1918 | .set_rate = set_rate_mnd, |
| 1919 | .freq_tbl = ftbl_camss_cci_cci_clk, |
| 1920 | .current_freq = &rcg_dummy_freq, |
| 1921 | .base = &virt_bases[MMSS_BASE], |
| 1922 | .c = { |
| 1923 | .dbg_name = "cci_clk_src", |
| 1924 | .ops = &clk_ops_rcg_mnd, |
| 1925 | VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000), |
| 1926 | CLK_INIT(cci_clk_src.c), |
| 1927 | }, |
| 1928 | }; |
| 1929 | |
| 1930 | static struct clk_freq_tbl ftbl_camss_gp0_1_clk[] = { |
| 1931 | F_MMSS( 10000, xo, 16, 1, 120), |
| 1932 | F_MMSS( 24000, xo, 16, 1, 50), |
| 1933 | F_MMSS( 6000000, gpll0, 10, 1, 10), |
| 1934 | F_MMSS( 12000000, gpll0, 10, 1, 5), |
| 1935 | F_MMSS( 13000000, gpll0, 4, 13, 150), |
| 1936 | F_MMSS( 24000000, gpll0, 5, 1, 5), |
| 1937 | F_END |
| 1938 | }; |
| 1939 | |
| 1940 | static struct rcg_clk mmss_gp0_clk_src = { |
| 1941 | .cmd_rcgr_reg = MMSS_GP0_CMD_RCGR, |
| 1942 | .set_rate = set_rate_mnd, |
| 1943 | .freq_tbl = ftbl_camss_gp0_1_clk, |
| 1944 | .current_freq = &rcg_dummy_freq, |
| 1945 | .base = &virt_bases[MMSS_BASE], |
| 1946 | .c = { |
| 1947 | .dbg_name = "mmss_gp0_clk_src", |
| 1948 | .ops = &clk_ops_rcg_mnd, |
| 1949 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1950 | CLK_INIT(mmss_gp0_clk_src.c), |
| 1951 | }, |
| 1952 | }; |
| 1953 | |
| 1954 | static struct rcg_clk mmss_gp1_clk_src = { |
| 1955 | .cmd_rcgr_reg = MMSS_GP1_CMD_RCGR, |
| 1956 | .set_rate = set_rate_mnd, |
| 1957 | .freq_tbl = ftbl_camss_gp0_1_clk, |
| 1958 | .current_freq = &rcg_dummy_freq, |
| 1959 | .base = &virt_bases[MMSS_BASE], |
| 1960 | .c = { |
| 1961 | .dbg_name = "mmss_gp1_clk_src", |
| 1962 | .ops = &clk_ops_rcg_mnd, |
| 1963 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 1964 | CLK_INIT(mmss_gp1_clk_src.c), |
| 1965 | }, |
| 1966 | }; |
| 1967 | |
| 1968 | static struct clk_freq_tbl ftbl_camss_mclk0_1_clk[] = { |
Patrick Daly | 42d2b7a | 2013-03-07 17:12:33 -0800 | [diff] [blame] | 1969 | F_MMSS( 19200000, xo, 1, 0, 0), |
| 1970 | F_MMSS( 24000000, gpll0, 5, 1, 5), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 1971 | F_MMSS( 66670000, gpll0, 9, 0, 0), |
| 1972 | F_END |
| 1973 | }; |
| 1974 | |
| 1975 | static struct rcg_clk mclk0_clk_src = { |
| 1976 | .cmd_rcgr_reg = MCLK0_CMD_RCGR, |
| 1977 | .set_rate = set_rate_mnd, |
| 1978 | .freq_tbl = ftbl_camss_mclk0_1_clk, |
| 1979 | .current_freq = &rcg_dummy_freq, |
| 1980 | .base = &virt_bases[MMSS_BASE], |
| 1981 | .c = { |
| 1982 | .dbg_name = "mclk0_clk_src", |
| 1983 | .ops = &clk_ops_rcg_mnd, |
| 1984 | VDD_DIG_FMAX_MAP1(LOW, 66670000), |
| 1985 | CLK_INIT(mclk0_clk_src.c), |
| 1986 | }, |
| 1987 | }; |
| 1988 | |
| 1989 | static struct rcg_clk mclk1_clk_src = { |
| 1990 | .cmd_rcgr_reg = MCLK1_CMD_RCGR, |
| 1991 | .set_rate = set_rate_mnd, |
| 1992 | .freq_tbl = ftbl_camss_mclk0_1_clk, |
| 1993 | .current_freq = &rcg_dummy_freq, |
| 1994 | .base = &virt_bases[MMSS_BASE], |
| 1995 | .c = { |
| 1996 | .dbg_name = "mclk1_clk_src", |
| 1997 | .ops = &clk_ops_rcg_mnd, |
| 1998 | VDD_DIG_FMAX_MAP1(LOW, 66670000), |
| 1999 | CLK_INIT(mclk1_clk_src.c), |
| 2000 | }, |
| 2001 | }; |
| 2002 | |
| 2003 | static struct clk_freq_tbl ftbl_camss_phy0_1_csi0_1phytimer_clk[] = { |
| 2004 | F_MMSS( 100000000, gpll0, 6, 0, 0), |
| 2005 | F_MMSS( 200000000, mmpll0_pll, 4, 0, 0), |
| 2006 | F_END |
| 2007 | }; |
| 2008 | |
| 2009 | static struct rcg_clk csi0phytimer_clk_src = { |
| 2010 | .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR, |
| 2011 | .set_rate = set_rate_hid, |
| 2012 | .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk, |
| 2013 | .current_freq = &rcg_dummy_freq, |
| 2014 | .base = &virt_bases[MMSS_BASE], |
| 2015 | .c = { |
| 2016 | .dbg_name = "csi0phytimer_clk_src", |
| 2017 | .ops = &clk_ops_rcg, |
| 2018 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 2019 | CLK_INIT(csi0phytimer_clk_src.c), |
| 2020 | }, |
| 2021 | }; |
| 2022 | |
| 2023 | static struct rcg_clk csi1phytimer_clk_src = { |
| 2024 | .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR, |
| 2025 | .set_rate = set_rate_hid, |
| 2026 | .freq_tbl = ftbl_camss_phy0_1_csi0_1phytimer_clk, |
| 2027 | .current_freq = &rcg_dummy_freq, |
| 2028 | .base = &virt_bases[MMSS_BASE], |
| 2029 | .c = { |
| 2030 | .dbg_name = "csi1phytimer_clk_src", |
| 2031 | .ops = &clk_ops_rcg, |
| 2032 | VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), |
| 2033 | CLK_INIT(csi1phytimer_clk_src.c), |
| 2034 | }, |
| 2035 | }; |
| 2036 | |
| 2037 | static struct clk_freq_tbl ftbl_camss_vfe_cpp_clk[] = { |
| 2038 | F_MMSS( 133330000, gpll0, 4.5, 0, 0), |
Patrick Daly | d3fd03f | 2013-03-08 19:01:18 -0800 | [diff] [blame] | 2039 | F_MMSS( 150000000, gpll0, 4, 0, 0), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2040 | F_MMSS( 266670000, mmpll0_pll, 3, 0, 0), |
| 2041 | F_MMSS( 320000000, mmpll0_pll, 2.5, 0, 0), |
Patrick Daly | d3fd03f | 2013-03-08 19:01:18 -0800 | [diff] [blame] | 2042 | F_MMSS( 400000000, mmpll0_pll, 2, 0, 0), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2043 | F_END |
| 2044 | }; |
| 2045 | |
Patrick Daly | d3fd03f | 2013-03-08 19:01:18 -0800 | [diff] [blame] | 2046 | static unsigned long camss_vfe_cpp_fmax_v2[VDD_DIG_NUM] = { |
| 2047 | 150000000, 320000000, 400000000, |
| 2048 | }; |
| 2049 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2050 | static struct rcg_clk cpp_clk_src = { |
| 2051 | .cmd_rcgr_reg = CPP_CMD_RCGR, |
| 2052 | .set_rate = set_rate_hid, |
| 2053 | .freq_tbl = ftbl_camss_vfe_cpp_clk, |
| 2054 | .current_freq = &rcg_dummy_freq, |
| 2055 | .base = &virt_bases[MMSS_BASE], |
| 2056 | .c = { |
| 2057 | .dbg_name = "cpp_clk_src", |
| 2058 | .ops = &clk_ops_rcg, |
| 2059 | VDD_DIG_FMAX_MAP3(LOW, 133330000, NOMINAL, 266670000, HIGH, |
Patrick Daly | e02a563 | 2013-02-12 20:23:35 -0800 | [diff] [blame] | 2060 | 320000000), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2061 | CLK_INIT(cpp_clk_src.c), |
| 2062 | }, |
| 2063 | }; |
| 2064 | |
Vikram Mulukutla | ae13f3c | 2013-03-20 18:03:29 -0700 | [diff] [blame] | 2065 | static struct clk_freq_tbl byte_freq_tbl[] = { |
| 2066 | { |
Aravind Venkateswaran | 78b7325 | 2013-05-08 18:25:21 -0700 | [diff] [blame] | 2067 | .src_clk = &byte_clk_src_8226.c, |
Vikram Mulukutla | ae13f3c | 2013-03-20 18:03:29 -0700 | [diff] [blame] | 2068 | .div_src_val = BVAL(10, 8, dsipll0_byte_mm_source_val), |
| 2069 | }, |
| 2070 | F_END |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2071 | }; |
| 2072 | |
| 2073 | static struct rcg_clk byte0_clk_src = { |
| 2074 | .cmd_rcgr_reg = BYTE0_CMD_RCGR, |
Vikram Mulukutla | ae13f3c | 2013-03-20 18:03:29 -0700 | [diff] [blame] | 2075 | .current_freq = byte_freq_tbl, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2076 | .base = &virt_bases[MMSS_BASE], |
| 2077 | .c = { |
Aravind Venkateswaran | 78b7325 | 2013-05-08 18:25:21 -0700 | [diff] [blame] | 2078 | .parent = &byte_clk_src_8226.c, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2079 | .dbg_name = "byte0_clk_src", |
Patrick Daly | 5555c2c | 2013-03-06 21:25:26 -0800 | [diff] [blame] | 2080 | .ops = &clk_ops_byte, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2081 | VDD_DIG_FMAX_MAP2(LOW, 62500000, NOMINAL, 125000000), |
| 2082 | CLK_INIT(byte0_clk_src.c), |
| 2083 | }, |
| 2084 | }; |
| 2085 | |
| 2086 | static struct clk_freq_tbl ftbl_mdss_esc0_clk[] = { |
| 2087 | F_MDSS( 19200000, xo, 1, 0, 0), |
| 2088 | F_END |
| 2089 | }; |
| 2090 | |
| 2091 | static struct rcg_clk esc0_clk_src = { |
| 2092 | .cmd_rcgr_reg = ESC0_CMD_RCGR, |
| 2093 | .set_rate = set_rate_hid, |
| 2094 | .freq_tbl = ftbl_mdss_esc0_clk, |
| 2095 | .current_freq = &rcg_dummy_freq, |
| 2096 | .base = &virt_bases[MMSS_BASE], |
| 2097 | .c = { |
| 2098 | .dbg_name = "esc0_clk_src", |
| 2099 | .ops = &clk_ops_rcg, |
| 2100 | VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000), |
| 2101 | CLK_INIT(esc0_clk_src.c), |
| 2102 | }, |
| 2103 | }; |
| 2104 | |
| 2105 | static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = { |
| 2106 | F_MDSS( 19200000, xo, 1, 0, 0), |
| 2107 | F_END |
| 2108 | }; |
| 2109 | |
| 2110 | static struct rcg_clk vsync_clk_src = { |
| 2111 | .cmd_rcgr_reg = VSYNC_CMD_RCGR, |
| 2112 | .set_rate = set_rate_hid, |
| 2113 | .freq_tbl = ftbl_mdss_vsync_clk, |
| 2114 | .current_freq = &rcg_dummy_freq, |
| 2115 | .base = &virt_bases[MMSS_BASE], |
| 2116 | .c = { |
| 2117 | .dbg_name = "vsync_clk_src", |
| 2118 | .ops = &clk_ops_rcg, |
| 2119 | VDD_DIG_FMAX_MAP2(LOW, 20000000, NOMINAL, 40000000), |
| 2120 | CLK_INIT(vsync_clk_src.c), |
| 2121 | }, |
| 2122 | }; |
| 2123 | |
| 2124 | static struct branch_clk camss_cci_cci_ahb_clk = { |
| 2125 | .cbcr_reg = CAMSS_CCI_CCI_AHB_CBCR, |
| 2126 | .has_sibling = 1, |
| 2127 | .base = &virt_bases[MMSS_BASE], |
| 2128 | .c = { |
| 2129 | .dbg_name = "camss_cci_cci_ahb_clk", |
| 2130 | .ops = &clk_ops_branch, |
| 2131 | CLK_INIT(camss_cci_cci_ahb_clk.c), |
| 2132 | }, |
| 2133 | }; |
| 2134 | |
| 2135 | static struct branch_clk camss_cci_cci_clk = { |
| 2136 | .cbcr_reg = CAMSS_CCI_CCI_CBCR, |
| 2137 | .has_sibling = 0, |
| 2138 | .base = &virt_bases[MMSS_BASE], |
| 2139 | .c = { |
| 2140 | .dbg_name = "camss_cci_cci_clk", |
| 2141 | .parent = &cci_clk_src.c, |
| 2142 | .ops = &clk_ops_branch, |
| 2143 | CLK_INIT(camss_cci_cci_clk.c), |
| 2144 | }, |
| 2145 | }; |
| 2146 | |
| 2147 | static struct branch_clk camss_csi0_ahb_clk = { |
| 2148 | .cbcr_reg = CAMSS_CSI0_AHB_CBCR, |
| 2149 | .has_sibling = 1, |
| 2150 | .base = &virt_bases[MMSS_BASE], |
| 2151 | .c = { |
| 2152 | .dbg_name = "camss_csi0_ahb_clk", |
| 2153 | .ops = &clk_ops_branch, |
| 2154 | CLK_INIT(camss_csi0_ahb_clk.c), |
| 2155 | }, |
| 2156 | }; |
| 2157 | |
| 2158 | static struct branch_clk camss_csi0_clk = { |
| 2159 | .cbcr_reg = CAMSS_CSI0_CBCR, |
| 2160 | .has_sibling = 1, |
| 2161 | .base = &virt_bases[MMSS_BASE], |
| 2162 | .c = { |
| 2163 | .dbg_name = "camss_csi0_clk", |
| 2164 | .parent = &csi0_clk_src.c, |
| 2165 | .ops = &clk_ops_branch, |
| 2166 | CLK_INIT(camss_csi0_clk.c), |
| 2167 | }, |
| 2168 | }; |
| 2169 | |
| 2170 | static struct branch_clk camss_csi0phy_clk = { |
| 2171 | .cbcr_reg = CAMSS_CSI0PHY_CBCR, |
| 2172 | .has_sibling = 1, |
| 2173 | .base = &virt_bases[MMSS_BASE], |
| 2174 | .c = { |
| 2175 | .dbg_name = "camss_csi0phy_clk", |
| 2176 | .parent = &csi0_clk_src.c, |
| 2177 | .ops = &clk_ops_branch, |
| 2178 | CLK_INIT(camss_csi0phy_clk.c), |
| 2179 | }, |
| 2180 | }; |
| 2181 | |
| 2182 | static struct branch_clk camss_csi0pix_clk = { |
| 2183 | .cbcr_reg = CAMSS_CSI0PIX_CBCR, |
| 2184 | .has_sibling = 1, |
| 2185 | .base = &virt_bases[MMSS_BASE], |
| 2186 | .c = { |
| 2187 | .dbg_name = "camss_csi0pix_clk", |
| 2188 | .parent = &csi0_clk_src.c, |
| 2189 | .ops = &clk_ops_branch, |
| 2190 | CLK_INIT(camss_csi0pix_clk.c), |
| 2191 | }, |
| 2192 | }; |
| 2193 | |
| 2194 | static struct branch_clk camss_csi0rdi_clk = { |
| 2195 | .cbcr_reg = CAMSS_CSI0RDI_CBCR, |
| 2196 | .has_sibling = 1, |
| 2197 | .base = &virt_bases[MMSS_BASE], |
| 2198 | .c = { |
| 2199 | .dbg_name = "camss_csi0rdi_clk", |
| 2200 | .parent = &csi0_clk_src.c, |
| 2201 | .ops = &clk_ops_branch, |
| 2202 | CLK_INIT(camss_csi0rdi_clk.c), |
| 2203 | }, |
| 2204 | }; |
| 2205 | |
| 2206 | static struct branch_clk camss_csi1_ahb_clk = { |
| 2207 | .cbcr_reg = CAMSS_CSI1_AHB_CBCR, |
| 2208 | .has_sibling = 1, |
| 2209 | .base = &virt_bases[MMSS_BASE], |
| 2210 | .c = { |
| 2211 | .dbg_name = "camss_csi1_ahb_clk", |
| 2212 | .ops = &clk_ops_branch, |
| 2213 | CLK_INIT(camss_csi1_ahb_clk.c), |
| 2214 | }, |
| 2215 | }; |
| 2216 | |
| 2217 | static struct branch_clk camss_csi1_clk = { |
| 2218 | .cbcr_reg = CAMSS_CSI1_CBCR, |
| 2219 | .has_sibling = 1, |
| 2220 | .base = &virt_bases[MMSS_BASE], |
| 2221 | .c = { |
| 2222 | .dbg_name = "camss_csi1_clk", |
| 2223 | .parent = &csi1_clk_src.c, |
| 2224 | .ops = &clk_ops_branch, |
| 2225 | CLK_INIT(camss_csi1_clk.c), |
| 2226 | }, |
| 2227 | }; |
| 2228 | |
| 2229 | static struct branch_clk camss_csi1phy_clk = { |
| 2230 | .cbcr_reg = CAMSS_CSI1PHY_CBCR, |
| 2231 | .has_sibling = 1, |
| 2232 | .base = &virt_bases[MMSS_BASE], |
| 2233 | .c = { |
| 2234 | .dbg_name = "camss_csi1phy_clk", |
| 2235 | .parent = &csi1_clk_src.c, |
| 2236 | .ops = &clk_ops_branch, |
| 2237 | CLK_INIT(camss_csi1phy_clk.c), |
| 2238 | }, |
| 2239 | }; |
| 2240 | |
| 2241 | static struct branch_clk camss_csi1pix_clk = { |
| 2242 | .cbcr_reg = CAMSS_CSI1PIX_CBCR, |
| 2243 | .has_sibling = 1, |
| 2244 | .base = &virt_bases[MMSS_BASE], |
| 2245 | .c = { |
| 2246 | .dbg_name = "camss_csi1pix_clk", |
| 2247 | .parent = &csi1_clk_src.c, |
| 2248 | .ops = &clk_ops_branch, |
| 2249 | CLK_INIT(camss_csi1pix_clk.c), |
| 2250 | }, |
| 2251 | }; |
| 2252 | |
| 2253 | static struct branch_clk camss_csi1rdi_clk = { |
| 2254 | .cbcr_reg = CAMSS_CSI1RDI_CBCR, |
| 2255 | .has_sibling = 1, |
| 2256 | .base = &virt_bases[MMSS_BASE], |
| 2257 | .c = { |
| 2258 | .dbg_name = "camss_csi1rdi_clk", |
| 2259 | .parent = &csi1_clk_src.c, |
| 2260 | .ops = &clk_ops_branch, |
| 2261 | CLK_INIT(camss_csi1rdi_clk.c), |
| 2262 | }, |
| 2263 | }; |
| 2264 | |
| 2265 | static struct branch_clk camss_csi_vfe0_clk = { |
| 2266 | .cbcr_reg = CAMSS_CSI_VFE0_CBCR, |
Matt Wagantall | 57b7456 | 2013-07-03 19:24:53 -0700 | [diff] [blame] | 2267 | .bcr_reg = CAMSS_CSI_VFE0_BCR, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2268 | .has_sibling = 1, |
| 2269 | .base = &virt_bases[MMSS_BASE], |
| 2270 | .c = { |
| 2271 | .dbg_name = "camss_csi_vfe0_clk", |
| 2272 | .parent = &vfe0_clk_src.c, |
| 2273 | .ops = &clk_ops_branch, |
| 2274 | CLK_INIT(camss_csi_vfe0_clk.c), |
| 2275 | }, |
| 2276 | }; |
| 2277 | |
| 2278 | static struct branch_clk camss_gp0_clk = { |
| 2279 | .cbcr_reg = CAMSS_GP0_CBCR, |
| 2280 | .has_sibling = 0, |
| 2281 | .base = &virt_bases[MMSS_BASE], |
| 2282 | .c = { |
| 2283 | .dbg_name = "camss_gp0_clk", |
| 2284 | .parent = &mmss_gp0_clk_src.c, |
| 2285 | .ops = &clk_ops_branch, |
| 2286 | CLK_INIT(camss_gp0_clk.c), |
| 2287 | }, |
| 2288 | }; |
| 2289 | |
| 2290 | static struct branch_clk camss_gp1_clk = { |
| 2291 | .cbcr_reg = CAMSS_GP1_CBCR, |
| 2292 | .has_sibling = 0, |
| 2293 | .base = &virt_bases[MMSS_BASE], |
| 2294 | .c = { |
| 2295 | .dbg_name = "camss_gp1_clk", |
| 2296 | .parent = &mmss_gp1_clk_src.c, |
| 2297 | .ops = &clk_ops_branch, |
| 2298 | CLK_INIT(camss_gp1_clk.c), |
| 2299 | }, |
| 2300 | }; |
| 2301 | |
| 2302 | static struct branch_clk camss_ispif_ahb_clk = { |
| 2303 | .cbcr_reg = CAMSS_ISPIF_AHB_CBCR, |
| 2304 | .has_sibling = 1, |
| 2305 | .base = &virt_bases[MMSS_BASE], |
| 2306 | .c = { |
| 2307 | .dbg_name = "camss_ispif_ahb_clk", |
| 2308 | .ops = &clk_ops_branch, |
| 2309 | CLK_INIT(camss_ispif_ahb_clk.c), |
| 2310 | }, |
| 2311 | }; |
| 2312 | |
| 2313 | static struct branch_clk camss_jpeg_jpeg0_clk = { |
| 2314 | .cbcr_reg = CAMSS_JPEG_JPEG0_CBCR, |
Matt Wagantall | 57b7456 | 2013-07-03 19:24:53 -0700 | [diff] [blame] | 2315 | .bcr_reg = CAMSS_JPEG_BCR, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2316 | .has_sibling = 0, |
| 2317 | .base = &virt_bases[MMSS_BASE], |
| 2318 | .c = { |
| 2319 | .dbg_name = "camss_jpeg_jpeg0_clk", |
| 2320 | .parent = &jpeg0_clk_src.c, |
| 2321 | .ops = &clk_ops_branch, |
| 2322 | CLK_INIT(camss_jpeg_jpeg0_clk.c), |
| 2323 | }, |
| 2324 | }; |
| 2325 | |
| 2326 | static struct branch_clk camss_jpeg_jpeg_ahb_clk = { |
| 2327 | .cbcr_reg = CAMSS_JPEG_JPEG_AHB_CBCR, |
| 2328 | .has_sibling = 1, |
| 2329 | .base = &virt_bases[MMSS_BASE], |
| 2330 | .c = { |
| 2331 | .dbg_name = "camss_jpeg_jpeg_ahb_clk", |
| 2332 | .ops = &clk_ops_branch, |
| 2333 | CLK_INIT(camss_jpeg_jpeg_ahb_clk.c), |
| 2334 | }, |
| 2335 | }; |
| 2336 | |
| 2337 | static struct branch_clk camss_jpeg_jpeg_axi_clk = { |
| 2338 | .cbcr_reg = CAMSS_JPEG_JPEG_AXI_CBCR, |
| 2339 | .has_sibling = 1, |
| 2340 | .base = &virt_bases[MMSS_BASE], |
| 2341 | .c = { |
| 2342 | .dbg_name = "camss_jpeg_jpeg_axi_clk", |
| 2343 | .parent = &axi_clk_src.c, |
| 2344 | .ops = &clk_ops_branch, |
| 2345 | CLK_INIT(camss_jpeg_jpeg_axi_clk.c), |
| 2346 | }, |
| 2347 | }; |
| 2348 | |
| 2349 | static struct branch_clk camss_mclk0_clk = { |
| 2350 | .cbcr_reg = CAMSS_MCLK0_CBCR, |
| 2351 | .has_sibling = 0, |
| 2352 | .base = &virt_bases[MMSS_BASE], |
| 2353 | .c = { |
| 2354 | .dbg_name = "camss_mclk0_clk", |
| 2355 | .parent = &mclk0_clk_src.c, |
| 2356 | .ops = &clk_ops_branch, |
| 2357 | CLK_INIT(camss_mclk0_clk.c), |
| 2358 | }, |
| 2359 | }; |
| 2360 | |
| 2361 | static struct branch_clk camss_mclk1_clk = { |
| 2362 | .cbcr_reg = CAMSS_MCLK1_CBCR, |
| 2363 | .has_sibling = 0, |
| 2364 | .base = &virt_bases[MMSS_BASE], |
| 2365 | .c = { |
| 2366 | .dbg_name = "camss_mclk1_clk", |
| 2367 | .parent = &mclk1_clk_src.c, |
| 2368 | .ops = &clk_ops_branch, |
| 2369 | CLK_INIT(camss_mclk1_clk.c), |
| 2370 | }, |
| 2371 | }; |
| 2372 | |
| 2373 | static struct branch_clk camss_micro_ahb_clk = { |
| 2374 | .cbcr_reg = CAMSS_MICRO_AHB_CBCR, |
| 2375 | .has_sibling = 1, |
Rajakumar Govindaram | 4c2482b | 2013-09-05 19:45:01 -0700 | [diff] [blame] | 2376 | .bcr_reg = CAMSS_MICRO_BCR, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2377 | .base = &virt_bases[MMSS_BASE], |
| 2378 | .c = { |
| 2379 | .dbg_name = "camss_micro_ahb_clk", |
| 2380 | .ops = &clk_ops_branch, |
| 2381 | CLK_INIT(camss_micro_ahb_clk.c), |
| 2382 | }, |
| 2383 | }; |
| 2384 | |
| 2385 | static struct branch_clk camss_phy0_csi0phytimer_clk = { |
| 2386 | .cbcr_reg = CAMSS_PHY0_CSI0PHYTIMER_CBCR, |
| 2387 | .has_sibling = 0, |
| 2388 | .base = &virt_bases[MMSS_BASE], |
| 2389 | .c = { |
| 2390 | .dbg_name = "camss_phy0_csi0phytimer_clk", |
| 2391 | .parent = &csi0phytimer_clk_src.c, |
| 2392 | .ops = &clk_ops_branch, |
| 2393 | CLK_INIT(camss_phy0_csi0phytimer_clk.c), |
| 2394 | }, |
| 2395 | }; |
| 2396 | |
| 2397 | static struct branch_clk camss_phy1_csi1phytimer_clk = { |
| 2398 | .cbcr_reg = CAMSS_PHY1_CSI1PHYTIMER_CBCR, |
| 2399 | .has_sibling = 0, |
| 2400 | .base = &virt_bases[MMSS_BASE], |
| 2401 | .c = { |
| 2402 | .dbg_name = "camss_phy1_csi1phytimer_clk", |
| 2403 | .parent = &csi1phytimer_clk_src.c, |
| 2404 | .ops = &clk_ops_branch, |
| 2405 | CLK_INIT(camss_phy1_csi1phytimer_clk.c), |
| 2406 | }, |
| 2407 | }; |
| 2408 | |
| 2409 | static struct branch_clk camss_top_ahb_clk = { |
| 2410 | .cbcr_reg = CAMSS_TOP_AHB_CBCR, |
| 2411 | .has_sibling = 1, |
| 2412 | .base = &virt_bases[MMSS_BASE], |
| 2413 | .c = { |
| 2414 | .dbg_name = "camss_top_ahb_clk", |
| 2415 | .ops = &clk_ops_branch, |
| 2416 | CLK_INIT(camss_top_ahb_clk.c), |
| 2417 | }, |
| 2418 | }; |
| 2419 | |
| 2420 | static struct branch_clk camss_vfe_cpp_ahb_clk = { |
| 2421 | .cbcr_reg = CAMSS_VFE_CPP_AHB_CBCR, |
| 2422 | .has_sibling = 1, |
| 2423 | .base = &virt_bases[MMSS_BASE], |
| 2424 | .c = { |
| 2425 | .dbg_name = "camss_vfe_cpp_ahb_clk", |
| 2426 | .ops = &clk_ops_branch, |
| 2427 | CLK_INIT(camss_vfe_cpp_ahb_clk.c), |
| 2428 | }, |
| 2429 | }; |
| 2430 | |
| 2431 | static struct branch_clk camss_vfe_cpp_clk = { |
| 2432 | .cbcr_reg = CAMSS_VFE_CPP_CBCR, |
| 2433 | .has_sibling = 0, |
| 2434 | .base = &virt_bases[MMSS_BASE], |
| 2435 | .c = { |
| 2436 | .dbg_name = "camss_vfe_cpp_clk", |
| 2437 | .parent = &cpp_clk_src.c, |
| 2438 | .ops = &clk_ops_branch, |
| 2439 | CLK_INIT(camss_vfe_cpp_clk.c), |
| 2440 | }, |
| 2441 | }; |
| 2442 | |
| 2443 | static struct branch_clk camss_vfe_vfe0_clk = { |
| 2444 | .cbcr_reg = CAMSS_VFE_VFE0_CBCR, |
Matt Wagantall | 57b7456 | 2013-07-03 19:24:53 -0700 | [diff] [blame] | 2445 | .bcr_reg = CAMSS_VFE_BCR, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2446 | .has_sibling = 1, |
| 2447 | .base = &virt_bases[MMSS_BASE], |
| 2448 | .c = { |
| 2449 | .dbg_name = "camss_vfe_vfe0_clk", |
| 2450 | .parent = &vfe0_clk_src.c, |
| 2451 | .ops = &clk_ops_branch, |
| 2452 | CLK_INIT(camss_vfe_vfe0_clk.c), |
| 2453 | }, |
| 2454 | }; |
| 2455 | |
| 2456 | static struct branch_clk camss_vfe_vfe_ahb_clk = { |
| 2457 | .cbcr_reg = CAMSS_VFE_VFE_AHB_CBCR, |
| 2458 | .has_sibling = 1, |
| 2459 | .base = &virt_bases[MMSS_BASE], |
| 2460 | .c = { |
| 2461 | .dbg_name = "camss_vfe_vfe_ahb_clk", |
| 2462 | .ops = &clk_ops_branch, |
| 2463 | CLK_INIT(camss_vfe_vfe_ahb_clk.c), |
| 2464 | }, |
| 2465 | }; |
| 2466 | |
| 2467 | static struct branch_clk camss_vfe_vfe_axi_clk = { |
| 2468 | .cbcr_reg = CAMSS_VFE_VFE_AXI_CBCR, |
| 2469 | .has_sibling = 1, |
| 2470 | .base = &virt_bases[MMSS_BASE], |
| 2471 | .c = { |
| 2472 | .dbg_name = "camss_vfe_vfe_axi_clk", |
| 2473 | .parent = &axi_clk_src.c, |
| 2474 | .ops = &clk_ops_branch, |
| 2475 | CLK_INIT(camss_vfe_vfe_axi_clk.c), |
| 2476 | }, |
| 2477 | }; |
| 2478 | |
| 2479 | static struct branch_clk mdss_ahb_clk = { |
| 2480 | .cbcr_reg = MDSS_AHB_CBCR, |
| 2481 | .has_sibling = 1, |
| 2482 | .base = &virt_bases[MMSS_BASE], |
| 2483 | .c = { |
| 2484 | .dbg_name = "mdss_ahb_clk", |
| 2485 | .ops = &clk_ops_branch, |
| 2486 | CLK_INIT(mdss_ahb_clk.c), |
| 2487 | }, |
| 2488 | }; |
| 2489 | |
| 2490 | static struct branch_clk mdss_axi_clk = { |
| 2491 | .cbcr_reg = MDSS_AXI_CBCR, |
| 2492 | .has_sibling = 1, |
| 2493 | .base = &virt_bases[MMSS_BASE], |
| 2494 | .c = { |
| 2495 | .dbg_name = "mdss_axi_clk", |
| 2496 | .parent = &axi_clk_src.c, |
| 2497 | .ops = &clk_ops_branch, |
| 2498 | CLK_INIT(mdss_axi_clk.c), |
| 2499 | }, |
| 2500 | }; |
| 2501 | |
| 2502 | static struct branch_clk mdss_byte0_clk = { |
| 2503 | .cbcr_reg = MDSS_BYTE0_CBCR, |
| 2504 | .has_sibling = 0, |
| 2505 | .base = &virt_bases[MMSS_BASE], |
| 2506 | .c = { |
| 2507 | .dbg_name = "mdss_byte0_clk", |
| 2508 | .parent = &byte0_clk_src.c, |
| 2509 | .ops = &clk_ops_branch, |
| 2510 | CLK_INIT(mdss_byte0_clk.c), |
| 2511 | }, |
| 2512 | }; |
| 2513 | |
| 2514 | static struct branch_clk mdss_esc0_clk = { |
| 2515 | .cbcr_reg = MDSS_ESC0_CBCR, |
| 2516 | .has_sibling = 0, |
| 2517 | .base = &virt_bases[MMSS_BASE], |
| 2518 | .c = { |
| 2519 | .dbg_name = "mdss_esc0_clk", |
| 2520 | .parent = &esc0_clk_src.c, |
| 2521 | .ops = &clk_ops_branch, |
| 2522 | CLK_INIT(mdss_esc0_clk.c), |
| 2523 | }, |
| 2524 | }; |
| 2525 | |
| 2526 | static struct branch_clk mdss_mdp_clk = { |
| 2527 | .cbcr_reg = MDSS_MDP_CBCR, |
Matt Wagantall | 57b7456 | 2013-07-03 19:24:53 -0700 | [diff] [blame] | 2528 | .bcr_reg = MDSS_BCR, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2529 | .has_sibling = 1, |
| 2530 | .base = &virt_bases[MMSS_BASE], |
| 2531 | .c = { |
| 2532 | .dbg_name = "mdss_mdp_clk", |
| 2533 | .parent = &mdp_clk_src.c, |
| 2534 | .ops = &clk_ops_branch, |
| 2535 | CLK_INIT(mdss_mdp_clk.c), |
| 2536 | }, |
| 2537 | }; |
| 2538 | |
| 2539 | static struct branch_clk mdss_mdp_lut_clk = { |
| 2540 | .cbcr_reg = MDSS_MDP_LUT_CBCR, |
| 2541 | .has_sibling = 1, |
| 2542 | .base = &virt_bases[MMSS_BASE], |
| 2543 | .c = { |
| 2544 | .dbg_name = "mdss_mdp_lut_clk", |
| 2545 | .parent = &mdp_clk_src.c, |
| 2546 | .ops = &clk_ops_branch, |
| 2547 | CLK_INIT(mdss_mdp_lut_clk.c), |
| 2548 | }, |
| 2549 | }; |
| 2550 | |
| 2551 | static struct branch_clk mdss_pclk0_clk = { |
| 2552 | .cbcr_reg = MDSS_PCLK0_CBCR, |
| 2553 | .has_sibling = 0, |
| 2554 | .base = &virt_bases[MMSS_BASE], |
| 2555 | .c = { |
| 2556 | .dbg_name = "mdss_pclk0_clk", |
| 2557 | .parent = &pclk0_clk_src.c, |
| 2558 | .ops = &clk_ops_branch, |
| 2559 | CLK_INIT(mdss_pclk0_clk.c), |
| 2560 | }, |
| 2561 | }; |
| 2562 | |
| 2563 | static struct branch_clk mdss_vsync_clk = { |
| 2564 | .cbcr_reg = MDSS_VSYNC_CBCR, |
| 2565 | .has_sibling = 0, |
| 2566 | .base = &virt_bases[MMSS_BASE], |
| 2567 | .c = { |
| 2568 | .dbg_name = "mdss_vsync_clk", |
| 2569 | .parent = &vsync_clk_src.c, |
| 2570 | .ops = &clk_ops_branch, |
| 2571 | CLK_INIT(mdss_vsync_clk.c), |
| 2572 | }, |
| 2573 | }; |
| 2574 | |
| 2575 | static struct branch_clk mmss_misc_ahb_clk = { |
| 2576 | .cbcr_reg = MMSS_MISC_AHB_CBCR, |
| 2577 | .has_sibling = 1, |
| 2578 | .base = &virt_bases[MMSS_BASE], |
| 2579 | .c = { |
| 2580 | .dbg_name = "mmss_misc_ahb_clk", |
| 2581 | .ops = &clk_ops_branch, |
| 2582 | CLK_INIT(mmss_misc_ahb_clk.c), |
| 2583 | }, |
| 2584 | }; |
| 2585 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2586 | static struct branch_clk mmss_mmssnoc_axi_clk = { |
| 2587 | .cbcr_reg = MMSS_MMSSNOC_AXI_CBCR, |
| 2588 | .has_sibling = 1, |
| 2589 | .base = &virt_bases[MMSS_BASE], |
| 2590 | .c = { |
| 2591 | .dbg_name = "mmss_mmssnoc_axi_clk", |
| 2592 | .parent = &axi_clk_src.c, |
| 2593 | .ops = &clk_ops_branch, |
| 2594 | CLK_INIT(mmss_mmssnoc_axi_clk.c), |
| 2595 | }, |
| 2596 | }; |
| 2597 | |
| 2598 | static struct branch_clk mmss_s0_axi_clk = { |
| 2599 | .cbcr_reg = MMSS_S0_AXI_CBCR, |
| 2600 | .has_sibling = 0, |
| 2601 | .max_div = 0, |
| 2602 | .base = &virt_bases[MMSS_BASE], |
| 2603 | .c = { |
| 2604 | .dbg_name = "mmss_s0_axi_clk", |
| 2605 | .parent = &axi_clk_src.c, |
| 2606 | .ops = &clk_ops_branch, |
| 2607 | CLK_INIT(mmss_s0_axi_clk.c), |
| 2608 | .depends = &mmss_mmssnoc_axi_clk.c, |
| 2609 | }, |
| 2610 | }; |
| 2611 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2612 | static struct branch_clk oxili_gfx3d_clk = { |
| 2613 | .cbcr_reg = OXILI_GFX3D_CBCR, |
Matt Wagantall | 57b7456 | 2013-07-03 19:24:53 -0700 | [diff] [blame] | 2614 | .bcr_reg = OXILICX_BCR, |
Patrick Daly | 295173b | 2013-03-11 13:35:40 -0700 | [diff] [blame] | 2615 | .has_sibling = 0, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2616 | .max_div = 0, |
| 2617 | .base = &virt_bases[MMSS_BASE], |
| 2618 | .c = { |
| 2619 | .dbg_name = "oxili_gfx3d_clk", |
| 2620 | .parent = &gfx3d_clk_src.c, |
| 2621 | .ops = &clk_ops_branch, |
| 2622 | CLK_INIT(oxili_gfx3d_clk.c), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2623 | }, |
| 2624 | }; |
| 2625 | |
| 2626 | static struct branch_clk oxilicx_ahb_clk = { |
| 2627 | .cbcr_reg = OXILICX_AHB_CBCR, |
| 2628 | .has_sibling = 1, |
| 2629 | .base = &virt_bases[MMSS_BASE], |
| 2630 | .c = { |
| 2631 | .dbg_name = "oxilicx_ahb_clk", |
| 2632 | .ops = &clk_ops_branch, |
| 2633 | CLK_INIT(oxilicx_ahb_clk.c), |
| 2634 | }, |
| 2635 | }; |
| 2636 | |
| 2637 | static struct branch_clk oxilicx_axi_clk = { |
| 2638 | .cbcr_reg = OXILICX_AXI_CBCR, |
| 2639 | .has_sibling = 1, |
| 2640 | .base = &virt_bases[MMSS_BASE], |
| 2641 | .c = { |
| 2642 | .dbg_name = "oxilicx_axi_clk", |
| 2643 | .parent = &axi_clk_src.c, |
| 2644 | .ops = &clk_ops_branch, |
| 2645 | CLK_INIT(oxilicx_axi_clk.c), |
| 2646 | }, |
| 2647 | }; |
| 2648 | |
| 2649 | static struct branch_clk venus0_ahb_clk = { |
| 2650 | .cbcr_reg = VENUS0_AHB_CBCR, |
| 2651 | .has_sibling = 1, |
| 2652 | .base = &virt_bases[MMSS_BASE], |
| 2653 | .c = { |
| 2654 | .dbg_name = "venus0_ahb_clk", |
| 2655 | .ops = &clk_ops_branch, |
| 2656 | CLK_INIT(venus0_ahb_clk.c), |
| 2657 | }, |
| 2658 | }; |
| 2659 | |
| 2660 | static struct branch_clk venus0_axi_clk = { |
| 2661 | .cbcr_reg = VENUS0_AXI_CBCR, |
| 2662 | .has_sibling = 1, |
| 2663 | .base = &virt_bases[MMSS_BASE], |
| 2664 | .c = { |
| 2665 | .dbg_name = "venus0_axi_clk", |
| 2666 | .parent = &axi_clk_src.c, |
| 2667 | .ops = &clk_ops_branch, |
| 2668 | CLK_INIT(venus0_axi_clk.c), |
| 2669 | }, |
| 2670 | }; |
| 2671 | |
| 2672 | static struct branch_clk venus0_vcodec0_clk = { |
| 2673 | .cbcr_reg = VENUS0_VCODEC0_CBCR, |
Matt Wagantall | 57b7456 | 2013-07-03 19:24:53 -0700 | [diff] [blame] | 2674 | .bcr_reg = VENUS0_BCR, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2675 | .has_sibling = 0, |
| 2676 | .base = &virt_bases[MMSS_BASE], |
| 2677 | .c = { |
| 2678 | .dbg_name = "venus0_vcodec0_clk", |
| 2679 | .parent = &vcodec0_clk_src.c, |
| 2680 | .ops = &clk_ops_branch, |
| 2681 | CLK_INIT(venus0_vcodec0_clk.c), |
| 2682 | }, |
| 2683 | }; |
| 2684 | |
Patrick Daly | 54a5c2f | 2013-10-07 17:36:37 -0700 | [diff] [blame] | 2685 | #ifdef CONFIG_DEBUG_FS |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2686 | static struct measure_mux_entry measure_mux_MMSS[] = { |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2687 | { &mmss_misc_ahb_clk.c, MMSS_BASE, 0x0003 }, |
| 2688 | { &mmss_mmssnoc_axi_clk.c, MMSS_BASE, 0x0004 }, |
| 2689 | { &mmss_s0_axi_clk.c, MMSS_BASE, 0x0005 }, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2690 | { &oxilicx_axi_clk.c, MMSS_BASE, 0x000b }, |
| 2691 | { &oxilicx_ahb_clk.c, MMSS_BASE, 0x000c }, |
| 2692 | { &oxili_gfx3d_clk.c, MMSS_BASE, 0x000d }, |
| 2693 | { &venus0_vcodec0_clk.c, MMSS_BASE, 0x000e }, |
| 2694 | { &venus0_axi_clk.c, MMSS_BASE, 0x000f }, |
| 2695 | { &venus0_ahb_clk.c, MMSS_BASE, 0x0011 }, |
| 2696 | { &mdss_mdp_clk.c, MMSS_BASE, 0x0014 }, |
| 2697 | { &mdss_mdp_lut_clk.c, MMSS_BASE, 0x0015 }, |
| 2698 | { &mdss_pclk0_clk.c, MMSS_BASE, 0x0016 }, |
| 2699 | { &mdss_vsync_clk.c, MMSS_BASE, 0x001c }, |
| 2700 | { &mdss_byte0_clk.c, MMSS_BASE, 0x001e }, |
| 2701 | { &mdss_esc0_clk.c, MMSS_BASE, 0x0020 }, |
| 2702 | { &mdss_ahb_clk.c, MMSS_BASE, 0x0022 }, |
| 2703 | { &mdss_axi_clk.c, MMSS_BASE, 0x0024 }, |
| 2704 | { &camss_top_ahb_clk.c, MMSS_BASE, 0x0025 }, |
| 2705 | { &camss_micro_ahb_clk.c, MMSS_BASE, 0x0026 }, |
| 2706 | { &camss_gp0_clk.c, MMSS_BASE, 0x0027 }, |
| 2707 | { &camss_gp1_clk.c, MMSS_BASE, 0x0028 }, |
| 2708 | { &camss_mclk0_clk.c, MMSS_BASE, 0x0029 }, |
| 2709 | { &camss_mclk1_clk.c, MMSS_BASE, 0x002a }, |
| 2710 | { &camss_cci_cci_clk.c, MMSS_BASE, 0x002d }, |
| 2711 | { &camss_cci_cci_ahb_clk.c, MMSS_BASE, 0x002e }, |
| 2712 | { &camss_phy0_csi0phytimer_clk.c, MMSS_BASE, 0x002f }, |
| 2713 | { &camss_phy1_csi1phytimer_clk.c, MMSS_BASE, 0x0030 }, |
| 2714 | { &camss_jpeg_jpeg0_clk.c, MMSS_BASE, 0x0032 }, |
| 2715 | { &camss_jpeg_jpeg_ahb_clk.c, MMSS_BASE, 0x0035 }, |
| 2716 | { &camss_jpeg_jpeg_axi_clk.c, MMSS_BASE, 0x0036 }, |
| 2717 | { &camss_vfe_vfe0_clk.c, MMSS_BASE, 0x0038 }, |
| 2718 | { &camss_vfe_cpp_clk.c, MMSS_BASE, 0x003a }, |
| 2719 | { &camss_vfe_cpp_ahb_clk.c, MMSS_BASE, 0x003b }, |
| 2720 | { &camss_vfe_vfe_ahb_clk.c, MMSS_BASE, 0x003c }, |
| 2721 | { &camss_vfe_vfe_axi_clk.c, MMSS_BASE, 0x003d }, |
| 2722 | { &camss_csi_vfe0_clk.c, MMSS_BASE, 0x003f }, |
| 2723 | { &camss_csi0_clk.c, MMSS_BASE, 0x0041 }, |
| 2724 | { &camss_csi0_ahb_clk.c, MMSS_BASE, 0x0042 }, |
| 2725 | { &camss_csi0phy_clk.c, MMSS_BASE, 0x0043 }, |
| 2726 | { &camss_csi0rdi_clk.c, MMSS_BASE, 0x0044 }, |
| 2727 | { &camss_csi0pix_clk.c, MMSS_BASE, 0x0045 }, |
| 2728 | { &camss_csi1_clk.c, MMSS_BASE, 0x0046 }, |
| 2729 | { &camss_csi1_ahb_clk.c, MMSS_BASE, 0x0047 }, |
| 2730 | { &camss_csi1phy_clk.c, MMSS_BASE, 0x0048 }, |
| 2731 | { &camss_csi1rdi_clk.c, MMSS_BASE, 0x0049 }, |
| 2732 | { &camss_csi1pix_clk.c, MMSS_BASE, 0x004a }, |
| 2733 | { &camss_ispif_ahb_clk.c, MMSS_BASE, 0x0055 }, |
Patrick Daly | 2a4ba83 | 2013-07-17 12:52:40 -0700 | [diff] [blame] | 2734 | { &mmssnoc_ahb_clk.c, MMSS_BASE, 0x0001 }, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2735 | {&dummy_clk, N_BASES, 0x0000}, |
| 2736 | }; |
Patrick Daly | 54a5c2f | 2013-10-07 17:36:37 -0700 | [diff] [blame] | 2737 | #endif /* CONFIG_DEBUG_FS */ |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2738 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2739 | static struct branch_clk q6ss_ahb_lfabif_clk = { |
| 2740 | .cbcr_reg = Q6SS_AHB_LFABIF_CBCR, |
| 2741 | .has_sibling = 1, |
| 2742 | .base = &virt_bases[LPASS_BASE], |
| 2743 | .c = { |
| 2744 | .dbg_name = "q6ss_ahb_lfabif_clk", |
| 2745 | .ops = &clk_ops_branch, |
| 2746 | CLK_INIT(q6ss_ahb_lfabif_clk.c), |
| 2747 | }, |
| 2748 | }; |
| 2749 | |
| 2750 | static struct branch_clk q6ss_ahbm_clk = { |
| 2751 | .cbcr_reg = Q6SS_AHBM_CBCR, |
| 2752 | .has_sibling = 1, |
| 2753 | .base = &virt_bases[LPASS_BASE], |
| 2754 | .c = { |
| 2755 | .dbg_name = "q6ss_ahbm_clk", |
| 2756 | .ops = &clk_ops_branch, |
| 2757 | CLK_INIT(q6ss_ahbm_clk.c), |
| 2758 | }, |
| 2759 | }; |
| 2760 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2761 | static struct branch_clk q6ss_xo_clk = { |
| 2762 | .cbcr_reg = Q6SS_XO_CBCR, |
| 2763 | .has_sibling = 1, |
| 2764 | .bcr_reg = Q6SS_BCR, |
| 2765 | .base = &virt_bases[LPASS_BASE], |
| 2766 | .c = { |
| 2767 | .dbg_name = "q6ss_xo_clk", |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2768 | .ops = &clk_ops_branch, |
| 2769 | CLK_INIT(q6ss_xo_clk.c), |
| 2770 | }, |
| 2771 | }; |
| 2772 | |
Patrick Daly | 54a5c2f | 2013-10-07 17:36:37 -0700 | [diff] [blame] | 2773 | #ifdef CONFIG_DEBUG_FS |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2774 | static struct measure_mux_entry measure_mux_LPASS[] = { |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2775 | { &q6ss_ahbm_clk.c, LPASS_BASE, 0x001d }, |
| 2776 | { &q6ss_ahb_lfabif_clk.c, LPASS_BASE, 0x001e }, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2777 | { &q6ss_xo_clk.c, LPASS_BASE, 0x002b }, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2778 | {&dummy_clk, N_BASES, 0x0000}, |
| 2779 | }; |
Patrick Daly | 54a5c2f | 2013-10-07 17:36:37 -0700 | [diff] [blame] | 2780 | #endif /* CONFIG_DEBUG_FS */ |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2781 | |
| 2782 | |
| 2783 | static DEFINE_CLK_MEASURE(apc0_m_clk); |
| 2784 | static DEFINE_CLK_MEASURE(apc1_m_clk); |
| 2785 | static DEFINE_CLK_MEASURE(apc2_m_clk); |
| 2786 | static DEFINE_CLK_MEASURE(apc3_m_clk); |
| 2787 | static DEFINE_CLK_MEASURE(l2_m_clk); |
| 2788 | |
Patrick Daly | 54a5c2f | 2013-10-07 17:36:37 -0700 | [diff] [blame] | 2789 | #ifdef CONFIG_DEBUG_FS |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2790 | static struct measure_mux_entry measure_mux_APSS[] = { |
| 2791 | {&apc0_m_clk, APCS_BASE, 0x00010}, |
| 2792 | {&apc1_m_clk, APCS_BASE, 0x00114}, |
| 2793 | {&apc2_m_clk, APCS_BASE, 0x00220}, |
| 2794 | {&apc3_m_clk, APCS_BASE, 0x00324}, |
| 2795 | {&l2_m_clk, APCS_BASE, 0x01000}, |
| 2796 | {&dummy_clk, N_BASES, 0x0000} |
| 2797 | }; |
Patrick Daly | 54a5c2f | 2013-10-07 17:36:37 -0700 | [diff] [blame] | 2798 | #endif /* CONFIG_DEBUG_FS */ |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2799 | |
| 2800 | #define APCS_SH_PLL_MODE (0x000) |
| 2801 | #define APCS_SH_PLL_L_VAL (0x004) |
| 2802 | #define APCS_SH_PLL_M_VAL (0x008) |
| 2803 | #define APCS_SH_PLL_N_VAL (0x00C) |
| 2804 | #define APCS_SH_PLL_USER_CTL (0x010) |
| 2805 | #define APCS_SH_PLL_CONFIG_CTL (0x014) |
| 2806 | #define APCS_SH_PLL_STATUS (0x01C) |
| 2807 | |
| 2808 | enum vdd_sr2_pll_levels { |
| 2809 | VDD_SR2_PLL_OFF, |
Patrick Daly | 6fb589a | 2013-03-29 17:55:55 -0700 | [diff] [blame] | 2810 | VDD_SR2_PLL_SVS, |
| 2811 | VDD_SR2_PLL_NOM, |
| 2812 | VDD_SR2_PLL_TUR, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2813 | VDD_SR2_PLL_NUM |
| 2814 | }; |
| 2815 | |
Junjie Wu | bb5a79e | 2013-05-15 13:12:39 -0700 | [diff] [blame] | 2816 | static int vdd_sr2_levels[] = { |
| 2817 | 0, RPM_REGULATOR_CORNER_NONE, /* VDD_SR2_PLL_OFF */ |
| 2818 | 1800000, RPM_REGULATOR_CORNER_SVS_SOC, /* VDD_SR2_PLL_SVS */ |
| 2819 | 1800000, RPM_REGULATOR_CORNER_NORMAL, /* VDD_SR2_PLL_NOM */ |
| 2820 | 1800000, RPM_REGULATOR_CORNER_SUPER_TURBO, /* VDD_SR2_PLL_TUR */ |
Patrick Daly | ebc26bc | 2013-02-05 11:49:07 -0800 | [diff] [blame] | 2821 | }; |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2822 | |
Patrick Daly | 653c0b5 | 2013-04-16 17:18:28 -0700 | [diff] [blame] | 2823 | static DEFINE_VDD_REGULATORS(vdd_sr2_pll, VDD_SR2_PLL_NUM, 2, |
| 2824 | vdd_sr2_levels, NULL); |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2825 | |
| 2826 | static struct pll_freq_tbl apcs_pll_freq[] = { |
Patrick Daly | 8380603 | 2013-03-25 15:18:24 -0700 | [diff] [blame] | 2827 | F_APCS_PLL( 768000000, 40, 0x0, 0x1, 0x0, 0x0, 0x0), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2828 | F_APCS_PLL( 787200000, 41, 0x0, 0x1, 0x0, 0x0, 0x0), |
| 2829 | F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0), |
Patrick Daly | f363c25 | 2013-03-21 12:08:37 -0700 | [diff] [blame] | 2830 | F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2831 | F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0), |
Patrick Daly | 66e32aa | 2013-05-30 15:11:52 -0700 | [diff] [blame] | 2832 | F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0), |
| 2833 | F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0), |
| 2834 | F_APCS_PLL(1401600000, 73, 0x0, 0x1, 0x0, 0x0, 0x0), |
Patrick Daly | 5a66c08 | 2013-08-02 10:58:56 -0700 | [diff] [blame] | 2835 | F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0), |
| 2836 | F_APCS_PLL(1593600000, 83, 0x0, 0x1, 0x0, 0x0, 0x0), |
Patrick Daly | 20eb696 | 2014-01-17 15:22:16 -0800 | [diff] [blame] | 2837 | F_APCS_PLL(1689600000, 88, 0x0, 0x1, 0x0, 0x0, 0x0), |
| 2838 | F_APCS_PLL(1785600000, 93, 0x0, 0x1, 0x0, 0x0, 0x0), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2839 | PLL_F_END |
| 2840 | }; |
| 2841 | |
| 2842 | static struct pll_clk a7sspll = { |
| 2843 | .mode_reg = (void __iomem *)APCS_SH_PLL_MODE, |
| 2844 | .l_reg = (void __iomem *)APCS_SH_PLL_L_VAL, |
| 2845 | .m_reg = (void __iomem *)APCS_SH_PLL_M_VAL, |
| 2846 | .n_reg = (void __iomem *)APCS_SH_PLL_N_VAL, |
| 2847 | .config_reg = (void __iomem *)APCS_SH_PLL_USER_CTL, |
| 2848 | .status_reg = (void __iomem *)APCS_SH_PLL_STATUS, |
| 2849 | .freq_tbl = apcs_pll_freq, |
| 2850 | .masks = { |
| 2851 | .vco_mask = BM(29, 28), |
| 2852 | .pre_div_mask = BIT(12), |
| 2853 | .post_div_mask = BM(9, 8), |
| 2854 | .mn_en_mask = BIT(24), |
| 2855 | .main_output_mask = BIT(0), |
| 2856 | }, |
| 2857 | .base = &virt_bases[APCS_PLL_BASE], |
| 2858 | .c = { |
Patrick Daly | 9bdc8a5 | 2013-03-21 19:12:40 -0700 | [diff] [blame] | 2859 | .parent = &xo_a_clk.c, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2860 | .dbg_name = "a7sspll", |
| 2861 | .ops = &clk_ops_sr2_pll, |
| 2862 | .vdd_class = &vdd_sr2_pll, |
| 2863 | .fmax = (unsigned long [VDD_SR2_PLL_NUM]) { |
Patrick Daly | 6fb589a | 2013-03-29 17:55:55 -0700 | [diff] [blame] | 2864 | [VDD_SR2_PLL_SVS] = 1000000000, |
| 2865 | [VDD_SR2_PLL_NOM] = 1900000000, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2866 | }, |
| 2867 | .num_fmax = VDD_SR2_PLL_NUM, |
| 2868 | CLK_INIT(a7sspll.c), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2869 | }, |
| 2870 | }; |
| 2871 | |
Patrick Daly | 01d4c1d | 2013-05-22 19:10:55 -0700 | [diff] [blame] | 2872 | static struct clk_freq_tbl ftbl_kpss_ahb_clk[] = { |
| 2873 | F_GCC(19200000, xo_a_clk, 0, 0, 0), |
| 2874 | F_GCC(37500000, gpll0, 16, 0, 0), |
Patrick Daly | 01d4c1d | 2013-05-22 19:10:55 -0700 | [diff] [blame] | 2875 | F_END |
| 2876 | }; |
| 2877 | |
| 2878 | static struct rcg_clk kpss_ahb_clk_src = { |
| 2879 | .cmd_rcgr_reg = KPSS_AHB_CMD_RCGR, |
| 2880 | .set_rate = set_rate_hid, |
| 2881 | .freq_tbl = ftbl_kpss_ahb_clk, |
| 2882 | .current_freq = &rcg_dummy_freq, |
| 2883 | .base = &virt_bases[GCC_BASE], |
| 2884 | .c = { |
| 2885 | .dbg_name = "kpss_ahb_clk_src", |
| 2886 | .ops = &clk_ops_rcg, |
Patrick Daly | 01d4c1d | 2013-05-22 19:10:55 -0700 | [diff] [blame] | 2887 | CLK_INIT(kpss_ahb_clk_src.c), |
| 2888 | }, |
| 2889 | }; |
| 2890 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2891 | static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX); |
| 2892 | static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX); |
| 2893 | static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX); |
| 2894 | static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX); |
| 2895 | static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX); |
| 2896 | static DEFINE_CLK_VOTER(cnoc_msmbus_a_clk, &cnoc_a_clk.c, LONG_MAX); |
| 2897 | |
| 2898 | static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX); |
| 2899 | static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX); |
| 2900 | static DEFINE_CLK_VOTER(bimc_acpu_a_clk, &bimc_a_clk.c, LONG_MAX); |
| 2901 | static DEFINE_CLK_VOTER(oxili_gfx3d_clk_src, &gfx3d_clk_src.c, LONG_MAX); |
| 2902 | static DEFINE_CLK_VOTER(ocmemgx_msmbus_clk, &ocmemgx_clk.c, LONG_MAX); |
| 2903 | static DEFINE_CLK_VOTER(ocmemgx_msmbus_a_clk, &ocmemgx_a_clk.c, LONG_MAX); |
| 2904 | static DEFINE_CLK_VOTER(ocmemgx_core_clk, &ocmemgx_clk.c, LONG_MAX); |
| 2905 | |
| 2906 | static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, LONG_MAX); |
| 2907 | |
Patrick Daly | 4aef16c | 2013-04-17 15:44:12 -0700 | [diff] [blame] | 2908 | static DEFINE_CLK_VOTER(qseecom_ce1_clk_src, &ce1_clk_src.c, 100000000); |
| 2909 | static DEFINE_CLK_VOTER(scm_ce1_clk_src, &ce1_clk_src.c, 100000000); |
Hariprasad Dhalinarasimha | e898bb1 | 2013-06-07 14:12:14 -0700 | [diff] [blame] | 2910 | static DEFINE_CLK_VOTER(gud_ce1_clk_src, &ce1_clk_src.c, 100000000); |
Patrick Daly | e07324c | 2013-03-27 18:02:49 -0700 | [diff] [blame] | 2911 | |
Patrick Daly | a529607 | 2013-03-19 12:18:04 -0700 | [diff] [blame] | 2912 | static DEFINE_CLK_BRANCH_VOTER(cxo_otg_clk, &xo.c); |
| 2913 | static DEFINE_CLK_BRANCH_VOTER(cxo_pil_lpass_clk, &xo.c); |
| 2914 | static DEFINE_CLK_BRANCH_VOTER(cxo_pil_mss_clk, &xo.c); |
| 2915 | static DEFINE_CLK_BRANCH_VOTER(cxo_wlan_clk, &xo.c); |
| 2916 | static DEFINE_CLK_BRANCH_VOTER(cxo_pil_pronto_clk, &xo.c); |
Vikram Mulukutla | ae4ae30 | 2013-04-24 12:00:28 -0700 | [diff] [blame] | 2917 | static DEFINE_CLK_BRANCH_VOTER(cxo_lpm_clk, &xo.c); |
Patrick Daly | a529607 | 2013-03-19 12:18:04 -0700 | [diff] [blame] | 2918 | |
| 2919 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2920 | #ifdef CONFIG_DEBUG_FS |
| 2921 | static int measure_clk_set_parent(struct clk *c, struct clk *parent) |
| 2922 | { |
| 2923 | struct measure_clk *clk = to_measure_clk(c); |
| 2924 | unsigned long flags; |
Patrick Daly | b499798 | 2013-01-31 11:45:28 -0800 | [diff] [blame] | 2925 | u32 regval, clk_sel, found = 0; |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2926 | int i; |
Patrick Daly | b499798 | 2013-01-31 11:45:28 -0800 | [diff] [blame] | 2927 | static const struct measure_mux_entry *array[] = { |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2928 | measure_mux_GCC, |
| 2929 | measure_mux_MMSS, |
| 2930 | measure_mux_LPASS, |
| 2931 | measure_mux_APSS, |
| 2932 | NULL |
| 2933 | }; |
Patrick Daly | b499798 | 2013-01-31 11:45:28 -0800 | [diff] [blame] | 2934 | const struct measure_mux_entry *mux = array[0]; |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2935 | |
| 2936 | if (!parent) |
| 2937 | return -EINVAL; |
| 2938 | |
Patrick Daly | b499798 | 2013-01-31 11:45:28 -0800 | [diff] [blame] | 2939 | for (i = 0; array[i] && !found; i++) { |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2940 | for (mux = array[i]; mux->c != &dummy_clk; mux++) |
Patrick Daly | b499798 | 2013-01-31 11:45:28 -0800 | [diff] [blame] | 2941 | if (mux->c == parent) { |
| 2942 | found = 1; |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2943 | break; |
Patrick Daly | b499798 | 2013-01-31 11:45:28 -0800 | [diff] [blame] | 2944 | } |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 2945 | } |
| 2946 | |
| 2947 | if (mux->c == &dummy_clk) |
| 2948 | return -EINVAL; |
| 2949 | |
| 2950 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 2951 | /* |
| 2952 | * Program the test vector, measurement period (sample_ticks) |
| 2953 | * and scaling multiplier. |
| 2954 | */ |
| 2955 | clk->sample_ticks = 0x10000; |
| 2956 | clk->multiplier = 1; |
| 2957 | |
| 2958 | switch (mux->base) { |
| 2959 | |
| 2960 | case GCC_BASE: |
| 2961 | writel_relaxed(0, GCC_REG_BASE(GCC_DEBUG_CLK_CTL)); |
| 2962 | clk_sel = mux->debug_mux; |
| 2963 | break; |
| 2964 | |
| 2965 | case MMSS_BASE: |
| 2966 | writel_relaxed(0, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL)); |
| 2967 | clk_sel = 0x02C; |
| 2968 | regval = BVAL(11, 0, mux->debug_mux); |
| 2969 | writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL)); |
| 2970 | |
| 2971 | /* Activate debug clock output */ |
| 2972 | regval |= BIT(16); |
| 2973 | writel_relaxed(regval, MMSS_REG_BASE(MMSS_DEBUG_CLK_CTL)); |
| 2974 | break; |
| 2975 | |
| 2976 | case LPASS_BASE: |
| 2977 | writel_relaxed(0, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL)); |
| 2978 | clk_sel = 0x161; |
| 2979 | regval = BVAL(11, 0, mux->debug_mux); |
| 2980 | writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL)); |
| 2981 | |
| 2982 | /* Activate debug clock output */ |
| 2983 | regval |= BIT(20); |
| 2984 | writel_relaxed(regval, LPASS_REG_BASE(LPASS_DEBUG_CLK_CTL)); |
| 2985 | break; |
| 2986 | |
| 2987 | case APCS_BASE: |
| 2988 | clk->multiplier = 4; |
| 2989 | clk_sel = 362; |
| 2990 | regval = readl_relaxed(APCS_REG_BASE(GLB_CLK_DIAG)); |
| 2991 | regval &= ~0xC0037335; |
| 2992 | /* configure a divider of 4 */ |
| 2993 | regval = BVAL(31, 30, 0x3) | mux->debug_mux; |
| 2994 | writel_relaxed(regval, APCS_REG_BASE(GLB_CLK_DIAG)); |
| 2995 | break; |
| 2996 | |
| 2997 | default: |
| 2998 | return -EINVAL; |
| 2999 | } |
| 3000 | |
| 3001 | /* Set debug mux clock index */ |
| 3002 | regval = BVAL(8, 0, clk_sel); |
| 3003 | writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL)); |
| 3004 | |
| 3005 | /* Activate debug clock output */ |
| 3006 | regval |= BIT(16); |
| 3007 | writel_relaxed(regval, GCC_REG_BASE(GCC_DEBUG_CLK_CTL)); |
| 3008 | |
| 3009 | /* Make sure test vector is set before starting measurements. */ |
| 3010 | mb(); |
| 3011 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 3012 | |
| 3013 | return 0; |
| 3014 | } |
| 3015 | |
| 3016 | /* Sample clock for 'ticks' reference clock ticks. */ |
| 3017 | static u32 run_measurement(unsigned ticks) |
| 3018 | { |
| 3019 | /* Stop counters and set the XO4 counter start value. */ |
| 3020 | writel_relaxed(ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL)); |
| 3021 | |
| 3022 | /* Wait for timer to become ready. */ |
| 3023 | while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) & |
| 3024 | BIT(25)) != 0) |
| 3025 | cpu_relax(); |
| 3026 | |
| 3027 | /* Run measurement and wait for completion. */ |
| 3028 | writel_relaxed(BIT(20)|ticks, GCC_REG_BASE(CLOCK_FRQ_MEASURE_CTL)); |
| 3029 | while ((readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) & |
| 3030 | BIT(25)) == 0) |
| 3031 | cpu_relax(); |
| 3032 | |
| 3033 | /* Return measured ticks. */ |
| 3034 | return readl_relaxed(GCC_REG_BASE(CLOCK_FRQ_MEASURE_STATUS)) & |
| 3035 | BM(24, 0); |
| 3036 | } |
| 3037 | |
| 3038 | /* |
| 3039 | * Perform a hardware rate measurement for a given clock. |
| 3040 | * FOR DEBUG USE ONLY: Measurements take ~15 ms! |
| 3041 | */ |
| 3042 | static unsigned long measure_clk_get_rate(struct clk *c) |
| 3043 | { |
| 3044 | unsigned long flags; |
| 3045 | u32 gcc_xo4_reg_backup; |
| 3046 | u64 raw_count_short, raw_count_full; |
| 3047 | struct measure_clk *clk = to_measure_clk(c); |
| 3048 | unsigned ret; |
| 3049 | |
| 3050 | ret = clk_prepare_enable(&xo.c); |
| 3051 | if (ret) { |
| 3052 | pr_warn("CXO clock failed to enable. Can't measure\n"); |
| 3053 | return 0; |
| 3054 | } |
| 3055 | |
| 3056 | spin_lock_irqsave(&local_clock_reg_lock, flags); |
| 3057 | |
| 3058 | /* Enable CXO/4 and RINGOSC branch. */ |
| 3059 | gcc_xo4_reg_backup = readl_relaxed(GCC_REG_BASE(GCC_XO_DIV4_CBCR)); |
| 3060 | writel_relaxed(0x1, GCC_REG_BASE(GCC_XO_DIV4_CBCR)); |
| 3061 | |
| 3062 | /* |
| 3063 | * The ring oscillator counter will not reset if the measured clock |
| 3064 | * is not running. To detect this, run a short measurement before |
| 3065 | * the full measurement. If the raw results of the two are the same |
| 3066 | * then the clock must be off. |
| 3067 | */ |
| 3068 | |
| 3069 | /* Run a short measurement. (~1 ms) */ |
| 3070 | raw_count_short = run_measurement(0x1000); |
| 3071 | /* Run a full measurement. (~14 ms) */ |
| 3072 | raw_count_full = run_measurement(clk->sample_ticks); |
| 3073 | |
| 3074 | writel_relaxed(gcc_xo4_reg_backup, GCC_REG_BASE(GCC_XO_DIV4_CBCR)); |
| 3075 | |
| 3076 | /* Return 0 if the clock is off. */ |
| 3077 | if (raw_count_full == raw_count_short) { |
| 3078 | ret = 0; |
| 3079 | } else { |
| 3080 | /* Compute rate in Hz. */ |
| 3081 | raw_count_full = ((raw_count_full * 10) + 15) * 4800000; |
| 3082 | do_div(raw_count_full, ((clk->sample_ticks * 10) + 35)); |
| 3083 | ret = (raw_count_full * clk->multiplier); |
| 3084 | } |
| 3085 | |
Patrick Daly | e095edb | 2013-05-23 14:13:09 -0700 | [diff] [blame] | 3086 | /* Set pin to gcc_debug_clock, enable output mode, disable input mode */ |
| 3087 | writel_relaxed(0x51200, GCC_REG_BASE(PLLTEST_PAD_CFG)); |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3088 | spin_unlock_irqrestore(&local_clock_reg_lock, flags); |
| 3089 | |
| 3090 | clk_disable_unprepare(&xo.c); |
| 3091 | |
| 3092 | return ret; |
| 3093 | } |
| 3094 | |
| 3095 | #else /* !CONFIG_DEBUG_FS */ |
| 3096 | static int measure_clk_set_parent(struct clk *clk, struct clk *parent) |
| 3097 | { |
| 3098 | return -EINVAL; |
| 3099 | } |
| 3100 | |
| 3101 | static unsigned long measure_clk_get_rate(struct clk *clk) |
| 3102 | { |
| 3103 | return 0; |
| 3104 | } |
| 3105 | #endif /* CONFIG_DEBUG_FS */ |
| 3106 | |
| 3107 | static struct clk_ops clk_ops_measure = { |
| 3108 | .set_parent = measure_clk_set_parent, |
| 3109 | .get_rate = measure_clk_get_rate, |
| 3110 | }; |
| 3111 | |
| 3112 | static struct measure_clk measure_clk = { |
| 3113 | .c = { |
| 3114 | .dbg_name = "measure_clk", |
| 3115 | .ops = &clk_ops_measure, |
| 3116 | CLK_INIT(measure_clk.c), |
| 3117 | }, |
| 3118 | .multiplier = 1, |
| 3119 | }; |
| 3120 | |
| 3121 | static struct clk_lookup msm_clocks_8226[] = { |
| 3122 | /* Debug Clocks */ |
| 3123 | CLK_LOOKUP("measure", measure_clk.c, "debug"), |
| 3124 | CLK_LOOKUP("apc0_m_clk", apc0_m_clk, ""), |
| 3125 | CLK_LOOKUP("apc1_m_clk", apc1_m_clk, ""), |
| 3126 | CLK_LOOKUP("apc2_m_clk", apc2_m_clk, ""), |
| 3127 | CLK_LOOKUP("apc3_m_clk", apc3_m_clk, ""), |
| 3128 | CLK_LOOKUP("l2_m_clk", l2_m_clk, ""), |
| 3129 | |
Vikram Mulukutla | 8da6c84 | 2013-12-18 17:26:01 -0800 | [diff] [blame] | 3130 | /* Measure clocks for WCNSS */ |
| 3131 | CLK_LOOKUP("measure", measure_clk.c, "fb000000.qcom,wcnss-wlan"), |
| 3132 | CLK_LOOKUP("wcnss_debug", wcnss_m_clk, "fb000000.qcom,wcnss-wlan"), |
| 3133 | |
Vikram Mulukutla | ae4ae30 | 2013-04-24 12:00:28 -0700 | [diff] [blame] | 3134 | /* LPM Resources */ |
| 3135 | CLK_LOOKUP("xo", cxo_lpm_clk.c, "fc4281d0.qcom,mpm"), |
| 3136 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3137 | /* PIL-LPASS */ |
Patrick Daly | a529607 | 2013-03-19 12:18:04 -0700 | [diff] [blame] | 3138 | CLK_LOOKUP("xo", cxo_pil_lpass_clk.c, "fe200000.qcom,lpass"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3139 | CLK_LOOKUP("core_clk", q6ss_xo_clk.c, "fe200000.qcom,lpass"), |
| 3140 | CLK_LOOKUP("bus_clk", gcc_lpass_q6_axi_clk.c, "fe200000.qcom,lpass"), |
| 3141 | CLK_LOOKUP("iface_clk", q6ss_ahb_lfabif_clk.c, "fe200000.qcom,lpass"), |
| 3142 | CLK_LOOKUP("reg_clk", q6ss_ahbm_clk.c, "fe200000.qcom,lpass"), |
| 3143 | |
| 3144 | /* PIL-MODEM */ |
Patrick Daly | a529607 | 2013-03-19 12:18:04 -0700 | [diff] [blame] | 3145 | CLK_LOOKUP("xo", cxo_pil_mss_clk.c, "fc880000.qcom,mss"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3146 | CLK_LOOKUP("bus_clk", gcc_mss_q6_bimc_axi_clk.c, "fc880000.qcom,mss"), |
| 3147 | CLK_LOOKUP("iface_clk", gcc_mss_cfg_ahb_clk.c, "fc880000.qcom,mss"), |
| 3148 | CLK_LOOKUP("mem_clk", gcc_boot_rom_ahb_clk.c, "fc880000.qcom,mss"), |
Madan Mohan Koyyalamudi | 497b700 | 2013-06-19 17:32:39 -0700 | [diff] [blame] | 3149 | /* NFC */ |
Manish Kumar | 402e57e | 2014-01-02 22:15:29 -0800 | [diff] [blame] | 3150 | CLK_LOOKUP("ref_clk", cxo_d1_a_pin.c, "2-000e"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3151 | /* PIL-PRONTO */ |
Patrick Daly | a529607 | 2013-03-19 12:18:04 -0700 | [diff] [blame] | 3152 | CLK_LOOKUP("xo", cxo_pil_pronto_clk.c, "fb21b000.qcom,pronto"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3153 | |
| 3154 | /* PIL-VENUS */ |
| 3155 | CLK_LOOKUP("src_clk", vcodec0_clk_src.c, "fdce0000.qcom,venus"), |
| 3156 | CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdce0000.qcom,venus"), |
| 3157 | CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"), |
| 3158 | CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdce0000.qcom,venus"), |
| 3159 | CLK_LOOKUP("mem_clk", venus0_ahb_clk.c, "fdce0000.qcom,venus"), |
| 3160 | |
| 3161 | /* ACPUCLOCK */ |
| 3162 | CLK_LOOKUP("xo", xo_a_clk.c, "f9011050.qcom,acpuclk"), |
| 3163 | CLK_LOOKUP("gpll0", gpll0_ao.c, "f9011050.qcom,acpuclk"), |
| 3164 | CLK_LOOKUP("a7sspll", a7sspll.c, "f9011050.qcom,acpuclk"), |
Patrick Daly | 2d2dfb5 | 2013-09-16 17:00:30 -0700 | [diff] [blame] | 3165 | CLK_LOOKUP("clk-4", gpll0_ao.c, "f9011050.qcom,clock-a7"), |
| 3166 | CLK_LOOKUP("clk-5", a7sspll.c, "f9011050.qcom,clock-a7"), |
Patrick Daly | 01d4c1d | 2013-05-22 19:10:55 -0700 | [diff] [blame] | 3167 | CLK_LOOKUP("kpss_ahb", kpss_ahb_clk_src.c, ""), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3168 | |
| 3169 | /* WCNSS CLOCKS */ |
Patrick Daly | a529607 | 2013-03-19 12:18:04 -0700 | [diff] [blame] | 3170 | CLK_LOOKUP("xo", cxo_wlan_clk.c, "fb000000.qcom,wcnss-wlan"), |
Vikram Mulukutla | 7e5b311 | 2013-04-15 16:32:40 -0700 | [diff] [blame] | 3171 | CLK_LOOKUP("rf_clk", cxo_a1.c, "fb000000.qcom,wcnss-wlan"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3172 | |
| 3173 | /* BUS DRIVER */ |
| 3174 | CLK_LOOKUP("bus_clk", cnoc_msmbus_clk.c, "msm_config_noc"), |
| 3175 | CLK_LOOKUP("bus_a_clk", cnoc_msmbus_a_clk.c, "msm_config_noc"), |
| 3176 | CLK_LOOKUP("bus_clk", snoc_msmbus_clk.c, "msm_sys_noc"), |
| 3177 | CLK_LOOKUP("bus_a_clk", snoc_msmbus_a_clk.c, "msm_sys_noc"), |
| 3178 | CLK_LOOKUP("bus_clk", pnoc_msmbus_clk.c, "msm_periph_noc"), |
| 3179 | CLK_LOOKUP("bus_a_clk", pnoc_msmbus_a_clk.c, "msm_periph_noc"), |
| 3180 | CLK_LOOKUP("mem_clk", bimc_msmbus_clk.c, "msm_bimc"), |
| 3181 | CLK_LOOKUP("mem_a_clk", bimc_msmbus_a_clk.c, "msm_bimc"), |
| 3182 | CLK_LOOKUP("mem_clk", bimc_acpu_a_clk.c, ""), |
| 3183 | CLK_LOOKUP("ocmem_clk", ocmemgx_msmbus_clk.c, "msm_bus"), |
| 3184 | CLK_LOOKUP("ocmem_a_clk", ocmemgx_msmbus_a_clk.c, "msm_bus"), |
| 3185 | CLK_LOOKUP("bus_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"), |
| 3186 | CLK_LOOKUP("bus_a_clk", mmss_s0_axi_clk.c, "msm_mmss_noc"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3187 | |
Aparna Das | 8c8e975 | 2013-02-28 21:23:24 -0800 | [diff] [blame] | 3188 | /* CoreSight clocks */ |
| 3189 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc322000.tmc"), |
| 3190 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc318000.tpiu"), |
| 3191 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc31c000.replicator"), |
| 3192 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc307000.tmc"), |
| 3193 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc31b000.funnel"), |
| 3194 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc319000.funnel"), |
| 3195 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc31a000.funnel"), |
| 3196 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc345000.funnel"), |
| 3197 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc364000.funnel"), |
| 3198 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc321000.stm"), |
| 3199 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.etm"), |
| 3200 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.etm"), |
| 3201 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.etm"), |
| 3202 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.etm"), |
Pushkar Joshi | 14676cc | 2013-03-11 14:53:53 -0700 | [diff] [blame] | 3203 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc33c000.jtagmm"), |
| 3204 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc33d000.jtagmm"), |
| 3205 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc33e000.jtagmm"), |
| 3206 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc33f000.jtagmm"), |
Aparna Das | bb65be4 | 2013-03-07 12:39:45 -0800 | [diff] [blame] | 3207 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc308000.cti"), |
| 3208 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc309000.cti"), |
| 3209 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc30a000.cti"), |
| 3210 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc30b000.cti"), |
| 3211 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc30c000.cti"), |
| 3212 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc30d000.cti"), |
| 3213 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc30e000.cti"), |
| 3214 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc30f000.cti"), |
| 3215 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc310000.cti"), |
| 3216 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc340000.cti"), |
| 3217 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc341000.cti"), |
| 3218 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc342000.cti"), |
| 3219 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc343000.cti"), |
| 3220 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc344000.cti"), |
Pratik Patel | 40c4b87 | 2013-10-04 16:09:59 -0700 | [diff] [blame] | 3221 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc348000.cti"), |
| 3222 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc34d000.cti"), |
| 3223 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc350000.cti"), |
| 3224 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc354000.cti"), |
| 3225 | CLK_LOOKUP("core_clk", qdss_clk.c, "fc358000.cti"), |
Aparna Das | ca6aa3a | 2013-04-02 16:25:27 -0700 | [diff] [blame] | 3226 | CLK_LOOKUP("core_clk", qdss_clk.c, "fd828018.hwevent"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3227 | |
Aparna Das | 8c8e975 | 2013-02-28 21:23:24 -0800 | [diff] [blame] | 3228 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc322000.tmc"), |
| 3229 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc318000.tpiu"), |
| 3230 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31c000.replicator"), |
| 3231 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc307000.tmc"), |
| 3232 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31b000.funnel"), |
| 3233 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc319000.funnel"), |
| 3234 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc31a000.funnel"), |
| 3235 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc345000.funnel"), |
| 3236 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc364000.funnel"), |
| 3237 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc321000.stm"), |
| 3238 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33c000.etm"), |
| 3239 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33d000.etm"), |
| 3240 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33e000.etm"), |
| 3241 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33f000.etm"), |
Aparna Das | 664239c | 2013-05-03 20:13:50 -0700 | [diff] [blame] | 3242 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33c000.jtagmm"), |
| 3243 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33d000.jtagmm"), |
| 3244 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33e000.jtagmm"), |
| 3245 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc33f000.jtagmm"), |
Aparna Das | bb65be4 | 2013-03-07 12:39:45 -0800 | [diff] [blame] | 3246 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc308000.cti"), |
| 3247 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc309000.cti"), |
| 3248 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30a000.cti"), |
| 3249 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30b000.cti"), |
| 3250 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30c000.cti"), |
| 3251 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30d000.cti"), |
| 3252 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30e000.cti"), |
| 3253 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc30f000.cti"), |
| 3254 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc310000.cti"), |
| 3255 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc340000.cti"), |
| 3256 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc341000.cti"), |
| 3257 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc342000.cti"), |
| 3258 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc343000.cti"), |
| 3259 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc344000.cti"), |
Pratik Patel | 40c4b87 | 2013-10-04 16:09:59 -0700 | [diff] [blame] | 3260 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc348000.cti"), |
| 3261 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc34d000.cti"), |
| 3262 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc350000.cti"), |
| 3263 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc354000.cti"), |
| 3264 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fc358000.cti"), |
Aparna Das | ca6aa3a | 2013-04-02 16:25:27 -0700 | [diff] [blame] | 3265 | CLK_LOOKUP("core_a_clk", qdss_a_clk.c, "fd828018.hwevent"), |
| 3266 | |
| 3267 | CLK_LOOKUP("core_mmss_clk", mmss_misc_ahb_clk.c, "fd828018.hwevent"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3268 | |
| 3269 | /* HSUSB-OTG Clocks */ |
Patrick Daly | a529607 | 2013-03-19 12:18:04 -0700 | [diff] [blame] | 3270 | CLK_LOOKUP("xo", cxo_otg_clk.c, "f9a55000.usb"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3271 | CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "f9a55000.usb"), |
| 3272 | CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "f9a55000.usb"), |
Mayank Rana | f14cb8d | 2013-07-24 17:09:17 +0530 | [diff] [blame] | 3273 | CLK_LOOKUP("sleep_clk", gcc_usb2a_phy_sleep_clk.c, "f9a55000.usb"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3274 | |
| 3275 | /* SPS CLOCKS */ |
| 3276 | CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "f9984000.qcom,sps"), |
| 3277 | CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "f9884000.qcom,sps"), |
| 3278 | CLK_LOOKUP("dfab_clk", pnoc_sps_clk.c, "msm_sps"), |
| 3279 | CLK_LOOKUP("dma_bam_pclk", gcc_bam_dma_ahb_clk.c, "msm_sps"), |
| 3280 | |
| 3281 | /* I2C Clocks */ |
| 3282 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9926000.i2c"), |
| 3283 | CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, "f9926000.i2c"), |
| 3284 | |
Amy Maloche | 41708ba | 2013-03-03 15:19:27 -0800 | [diff] [blame] | 3285 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9927000.i2c"), |
| 3286 | CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, "f9927000.i2c"), |
| 3287 | |
Madan Mohan Koyyalamudi | 497b700 | 2013-06-19 17:32:39 -0700 | [diff] [blame] | 3288 | /* I2C Clocks nfc */ |
| 3289 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9925000.i2c"), |
| 3290 | CLK_LOOKUP("core_clk", gcc_blsp1_qup3_i2c_apps_clk.c, "f9925000.i2c"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3291 | /* lsuart-v14 Clocks */ |
| 3292 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f991f000.serial"), |
| 3293 | CLK_LOOKUP("core_clk", gcc_blsp1_uart3_apps_clk.c, "f991f000.serial"), |
| 3294 | |
| 3295 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f995e000.serial"), |
| 3296 | CLK_LOOKUP("core_clk", gcc_blsp1_uart2_apps_clk.c, "f995e000.serial"), |
| 3297 | |
Gilad Avidov | d59217c | 2013-02-01 13:45:59 -0700 | [diff] [blame] | 3298 | CLK_LOOKUP("iface_clk", gcc_blsp1_ahb_clk.c, "f9923000.spi"), |
| 3299 | CLK_LOOKUP("core_clk", gcc_blsp1_qup1_spi_apps_clk.c, "f9923000.spi"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3300 | |
| 3301 | CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "qseecom"), |
| 3302 | CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "qseecom"), |
| 3303 | CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "qseecom"), |
Patrick Daly | e07324c | 2013-03-27 18:02:49 -0700 | [diff] [blame] | 3304 | CLK_LOOKUP("core_clk_src", qseecom_ce1_clk_src.c, "qseecom"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3305 | |
Hariprasad Dhalinarasimha | e898bb1 | 2013-06-07 14:12:14 -0700 | [diff] [blame] | 3306 | CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "mcd"), |
| 3307 | CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "mcd"), |
| 3308 | CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "mcd"), |
| 3309 | CLK_LOOKUP("core_clk_src", gud_ce1_clk_src.c, "mcd"), |
| 3310 | |
Patrick Daly | d523425 | 2013-03-07 16:35:08 -0800 | [diff] [blame] | 3311 | CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "scm"), |
| 3312 | CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "scm"), |
| 3313 | CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "scm"), |
Patrick Daly | e07324c | 2013-03-27 18:02:49 -0700 | [diff] [blame] | 3314 | CLK_LOOKUP("core_clk_src", scm_ce1_clk_src.c, "scm"), |
| 3315 | |
| 3316 | CLK_LOOKUP("core_clk_src", ce1_clk_src.c, ""), |
Patrick Daly | d523425 | 2013-03-07 16:35:08 -0800 | [diff] [blame] | 3317 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3318 | /* SDCC */ |
| 3319 | CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "f9824000.qcom,sdcc"), |
| 3320 | CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "f9824000.qcom,sdcc"), |
| 3321 | CLK_LOOKUP("iface_clk", gcc_sdcc1_ahb_clk.c, "msm_sdcc.1"), |
| 3322 | CLK_LOOKUP("core_clk", gcc_sdcc1_apps_clk.c, "msm_sdcc.1"), |
| 3323 | |
| 3324 | CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "f98a4000.qcom,sdcc"), |
| 3325 | CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "f98a4000.qcom,sdcc"), |
| 3326 | CLK_LOOKUP("iface_clk", gcc_sdcc2_ahb_clk.c, "msm_sdcc.2"), |
| 3327 | CLK_LOOKUP("core_clk", gcc_sdcc2_apps_clk.c, "msm_sdcc.2"), |
| 3328 | |
| 3329 | CLK_LOOKUP("iface_clk", gcc_sdcc3_ahb_clk.c, "msm_sdcc.3"), |
| 3330 | CLK_LOOKUP("core_clk", gcc_sdcc3_apps_clk.c, "msm_sdcc.3"), |
| 3331 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3332 | CLK_LOOKUP("bus_clk", pnoc_clk.c, ""), |
| 3333 | CLK_LOOKUP("bus_clk", pnoc_a_clk.c, ""), |
| 3334 | CLK_LOOKUP("bus_clk", snoc_clk.c, ""), |
| 3335 | CLK_LOOKUP("bus_clk", snoc_a_clk.c, ""), |
| 3336 | CLK_LOOKUP("bus_clk", cnoc_clk.c, ""), |
| 3337 | CLK_LOOKUP("bus_clk", cnoc_a_clk.c, ""), |
| 3338 | CLK_LOOKUP("bus_clk", mmssnoc_ahb_clk.c, ""), |
| 3339 | CLK_LOOKUP("bus_clk", mmssnoc_ahb_a_clk.c, ""), |
| 3340 | CLK_LOOKUP("bus_clk", bimc_clk.c, ""), |
| 3341 | CLK_LOOKUP("bus_clk", bimc_a_clk.c, ""), |
| 3342 | CLK_LOOKUP("bus_clk_src", axi_clk_src.c, ""), |
| 3343 | |
| 3344 | CLK_LOOKUP("gpll0", gpll0.c, ""), |
| 3345 | CLK_LOOKUP("gpll1", gpll1.c, ""), |
| 3346 | CLK_LOOKUP("mmpll0", mmpll0_pll.c, ""), |
| 3347 | CLK_LOOKUP("mmpll1", mmpll1_pll.c, ""), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3348 | |
| 3349 | CLK_LOOKUP("core_clk", gcc_blsp1_qup1_i2c_apps_clk.c, ""), |
| 3350 | CLK_LOOKUP("core_clk", gcc_blsp1_qup2_i2c_apps_clk.c, ""), |
| 3351 | CLK_LOOKUP("core_clk", gcc_blsp1_qup2_spi_apps_clk.c, ""), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3352 | CLK_LOOKUP("core_clk", gcc_blsp1_qup3_spi_apps_clk.c, ""), |
| 3353 | CLK_LOOKUP("core_clk", gcc_blsp1_qup4_i2c_apps_clk.c, ""), |
| 3354 | CLK_LOOKUP("core_clk", gcc_blsp1_qup4_spi_apps_clk.c, ""), |
| 3355 | CLK_LOOKUP("core_clk", gcc_blsp1_qup5_i2c_apps_clk.c, ""), |
| 3356 | CLK_LOOKUP("core_clk", gcc_blsp1_qup5_spi_apps_clk.c, ""), |
| 3357 | CLK_LOOKUP("core_clk", gcc_blsp1_qup6_i2c_apps_clk.c, ""), |
| 3358 | CLK_LOOKUP("core_clk", gcc_blsp1_qup6_spi_apps_clk.c, ""), |
| 3359 | CLK_LOOKUP("core_clk", gcc_blsp1_uart1_apps_clk.c, ""), |
| 3360 | CLK_LOOKUP("core_clk", gcc_blsp1_uart4_apps_clk.c, ""), |
| 3361 | CLK_LOOKUP("core_clk", gcc_blsp1_uart5_apps_clk.c, ""), |
| 3362 | CLK_LOOKUP("core_clk", gcc_blsp1_uart6_apps_clk.c, ""), |
| 3363 | CLK_LOOKUP("core_clk", gcc_pdm2_clk.c, ""), |
| 3364 | CLK_LOOKUP("iface_clk", gcc_pdm_ahb_clk.c, ""), |
| 3365 | CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, ""), |
| 3366 | CLK_LOOKUP("core_clk", gcc_gp1_clk.c, ""), |
| 3367 | CLK_LOOKUP("core_clk", gcc_gp2_clk.c, ""), |
| 3368 | CLK_LOOKUP("core_clk", gcc_gp3_clk.c, ""), |
| 3369 | |
| 3370 | CLK_LOOKUP("iface_clk", gcc_usb_hsic_ahb_clk.c, "msm_hsic_host"), |
| 3371 | CLK_LOOKUP("phy_clk", gcc_usb_hsic_clk.c, "msm_hsic_host"), |
| 3372 | CLK_LOOKUP("cal_clk", gcc_usb_hsic_io_cal_clk.c, "msm_hsic_host"), |
| 3373 | CLK_LOOKUP("core_clk", gcc_usb_hsic_system_clk.c, "msm_hsic_host"), |
| 3374 | CLK_LOOKUP("ref_clk", div_clk2.c, "msm_smsc_hub"), |
| 3375 | CLK_LOOKUP("iface_clk", gcc_usb_hs_ahb_clk.c, "msm_ehci_host"), |
| 3376 | CLK_LOOKUP("core_clk", gcc_usb_hs_system_clk.c, "msm_ehci_host"), |
| 3377 | CLK_LOOKUP("pwm_clk", div_clk2.c, "0-0048"), |
| 3378 | |
| 3379 | /* Multimedia clocks */ |
| 3380 | CLK_LOOKUP("byte_clk", mdss_byte0_clk.c, "fd922800.qcom,mdss_dsi"), |
| 3381 | CLK_LOOKUP("core_clk", mdss_esc0_clk.c, "fd922800.qcom,mdss_dsi"), |
| 3382 | CLK_LOOKUP("pixel_clk", mdss_pclk0_clk.c, "fd922800.qcom,mdss_dsi"), |
Aravind Venkateswaran | 6b6d9c4 | 2013-05-06 16:10:03 -0700 | [diff] [blame] | 3383 | CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd922800.qcom,mdss_dsi"), |
| 3384 | CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "fd922800.qcom,mdss_dsi"), |
Kuogee Hsieh | 29ccc04 | 2013-07-26 13:23:23 -0700 | [diff] [blame] | 3385 | CLK_LOOKUP("mdp_core_clk", mdss_mdp_clk.c, "fd922800.qcom,mdss_dsi"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3386 | |
Adrian Salido-Moreno | f840a03 | 2013-03-01 23:10:03 -0800 | [diff] [blame] | 3387 | CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "fd900000.qcom,mdss_mdp"), |
| 3388 | CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "fd900000.qcom,mdss_mdp"), |
| 3389 | CLK_LOOKUP("core_clk_src", mdp_clk_src.c, "fd900000.qcom,mdss_mdp"), |
| 3390 | CLK_LOOKUP("vsync_clk", mdss_vsync_clk.c, "fd900000.qcom,mdss_mdp"), |
| 3391 | CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd900000.qcom,mdss_mdp"), |
| 3392 | CLK_LOOKUP("bus_clk", mdss_axi_clk.c, "fd900000.qcom,mdss_mdp"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3393 | |
| 3394 | CLK_LOOKUP("iface_clk", mdss_ahb_clk.c, "fd928000.qcom,iommu"), |
| 3395 | CLK_LOOKUP("core_clk", mdss_axi_clk.c, "fd928000.qcom,iommu"), |
| 3396 | |
Matt Wagantall | b8cba29 | 2013-04-11 15:45:17 -0700 | [diff] [blame] | 3397 | CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fd8c1024.qcom,gdsc"), |
| 3398 | CLK_LOOKUP("core_clk", mdss_mdp_clk.c, "fd8c2304.qcom,gdsc"), |
| 3399 | CLK_LOOKUP("lut_clk", mdss_mdp_lut_clk.c, "fd8c2304.qcom,gdsc"), |
| 3400 | CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, "fd8c35a4.qcom,gdsc"), |
| 3401 | CLK_LOOKUP("core_clk", camss_vfe_vfe0_clk.c, "fd8c36a4.qcom,gdsc"), |
| 3402 | CLK_LOOKUP("csi_clk", camss_csi_vfe0_clk.c, "fd8c36a4.qcom,gdsc"), |
| 3403 | CLK_LOOKUP("cpp_clk", camss_vfe_cpp_clk.c, "fd8c36a4.qcom,gdsc"), |
| 3404 | CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fd8c4034.qcom,gdsc"), |
| 3405 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3406 | /* MM sensor clocks */ |
Su Liu | d1c66ee | 2013-03-22 15:29:48 -0700 | [diff] [blame] | 3407 | CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6f.qcom,camera"), |
Ju He | 0dd84ad | 2013-06-18 09:59:13 +0800 | [diff] [blame] | 3408 | CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "90.qcom,camera"), |
Su Liu | d1c66ee | 2013-03-22 15:29:48 -0700 | [diff] [blame] | 3409 | CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6d.qcom,camera"), |
Liu Su | 1e4c0ba | 2013-06-08 23:30:01 +0800 | [diff] [blame] | 3410 | CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6a.qcom,camera"), |
feim | 0aaee48 | 2013-06-08 15:26:20 +0800 | [diff] [blame] | 3411 | CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6c.qcom,camera"), |
Ju He | bbe039e | 2013-07-29 04:45:26 -0700 | [diff] [blame] | 3412 | CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "20.qcom,camera"), |
Su Liu | d1c66ee | 2013-03-22 15:29:48 -0700 | [diff] [blame] | 3413 | CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6f.qcom,camera"), |
Ju He | 0dd84ad | 2013-06-18 09:59:13 +0800 | [diff] [blame] | 3414 | CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "90.qcom,camera"), |
Su Liu | d1c66ee | 2013-03-22 15:29:48 -0700 | [diff] [blame] | 3415 | CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6d.qcom,camera"), |
Liu Su | 1e4c0ba | 2013-06-08 23:30:01 +0800 | [diff] [blame] | 3416 | CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6a.qcom,camera"), |
feim | 0aaee48 | 2013-06-08 15:26:20 +0800 | [diff] [blame] | 3417 | CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6c.qcom,camera"), |
Ju He | bbe039e | 2013-07-29 04:45:26 -0700 | [diff] [blame] | 3418 | CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "20.qcom,camera"), |
Evgeniy Borisov | 11d85b0 | 2013-09-16 16:52:36 +0300 | [diff] [blame] | 3419 | CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "0.qcom,camera"), |
| 3420 | CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "1.qcom,camera"), |
| 3421 | CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "0.qcom,camera"), |
| 3422 | CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "1.qcom,camera"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3423 | |
Ju He | f80f40b | 2013-07-18 17:06:32 +0800 | [diff] [blame] | 3424 | /* eeprom clocks */ |
| 3425 | CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6c.qcom,eeprom"), |
| 3426 | CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6c.qcom,eeprom"), |
Wang Wenbin | adb9448 | 2013-08-07 14:26:09 +0800 | [diff] [blame] | 3427 | CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "18.qcom,eeprom"), |
| 3428 | CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "18.qcom,eeprom"), |
Su Liu | 5666493 | 2013-08-14 10:20:06 +0800 | [diff] [blame] | 3429 | CLK_LOOKUP("cam_src_clk", mclk0_clk_src.c, "6b.qcom,eeprom"), |
| 3430 | CLK_LOOKUP("cam_clk", camss_mclk0_clk.c, "6b.qcom,eeprom"), |
Ju He | f80f40b | 2013-07-18 17:06:32 +0800 | [diff] [blame] | 3431 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3432 | /* CCI clocks */ |
| 3433 | CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c, |
| 3434 | "fda0c000.qcom,cci"), |
| 3435 | CLK_LOOKUP("cci_ahb_clk", camss_cci_cci_ahb_clk.c, |
| 3436 | "fda0c000.qcom,cci"), |
| 3437 | CLK_LOOKUP("cci_src_clk", cci_clk_src.c, "fda0c000.qcom,cci"), |
| 3438 | CLK_LOOKUP("cci_clk", camss_cci_cci_clk.c, "fda0c000.qcom,cci"), |
| 3439 | |
| 3440 | /* CSIPHY clocks */ |
| 3441 | CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c, |
| 3442 | "fda0ac00.qcom,csiphy"), |
| 3443 | CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c, |
| 3444 | "fda0ac00.qcom,csiphy"), |
| 3445 | CLK_LOOKUP("csiphy_timer_src_clk", csi0phytimer_clk_src.c, |
| 3446 | "fda0ac00.qcom,csiphy"), |
| 3447 | CLK_LOOKUP("csiphy_timer_clk", camss_phy0_csi0phytimer_clk.c, |
| 3448 | "fda0ac00.qcom,csiphy"), |
| 3449 | CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c, |
| 3450 | "fda0b000.qcom,csiphy"), |
| 3451 | CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c, |
| 3452 | "fda0b000.qcom,csiphy"), |
| 3453 | CLK_LOOKUP("csiphy_timer_src_clk", csi1phytimer_clk_src.c, |
| 3454 | "fda0b000.qcom,csiphy"), |
| 3455 | CLK_LOOKUP("csiphy_timer_clk", camss_phy1_csi1phytimer_clk.c, |
| 3456 | "fda0b000.qcom,csiphy"), |
| 3457 | |
| 3458 | /* CSID clocks */ |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3459 | CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c, |
Su Liu | 2d73d77 | 2013-04-24 23:55:32 -0700 | [diff] [blame] | 3460 | "fda08000.qcom,csid"), |
| 3461 | CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c, |
| 3462 | "fda08000.qcom,csid"), |
| 3463 | CLK_LOOKUP("csi_ahb_clk", camss_csi0_ahb_clk.c, |
| 3464 | "fda08000.qcom,csid"), |
| 3465 | CLK_LOOKUP("csi_src_clk", csi0_clk_src.c, |
| 3466 | "fda08000.qcom,csid"), |
| 3467 | CLK_LOOKUP("csi_phy_clk", camss_csi0phy_clk.c, |
| 3468 | "fda08000.qcom,csid"), |
| 3469 | CLK_LOOKUP("csi_clk", camss_csi0_clk.c, |
| 3470 | "fda08000.qcom,csid"), |
| 3471 | CLK_LOOKUP("csi_pix_clk", camss_csi0pix_clk.c, |
| 3472 | "fda08000.qcom,csid"), |
| 3473 | CLK_LOOKUP("csi_rdi_clk", camss_csi0rdi_clk.c, |
| 3474 | "fda08000.qcom,csid"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3475 | |
Su Liu | 2d73d77 | 2013-04-24 23:55:32 -0700 | [diff] [blame] | 3476 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3477 | CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c, |
Su Liu | 2d73d77 | 2013-04-24 23:55:32 -0700 | [diff] [blame] | 3478 | "fda08400.qcom,csid"), |
| 3479 | CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c, |
| 3480 | "fda08400.qcom,csid"), |
| 3481 | CLK_LOOKUP("csi_ahb_clk", camss_csi1_ahb_clk.c, |
| 3482 | "fda08400.qcom,csid"), |
| 3483 | CLK_LOOKUP("csi_src_clk", csi1_clk_src.c, |
| 3484 | "fda08400.qcom,csid"), |
| 3485 | CLK_LOOKUP("csi_phy_clk", camss_csi1phy_clk.c, |
| 3486 | "fda08400.qcom,csid"), |
| 3487 | CLK_LOOKUP("csi_clk", camss_csi1_clk.c, |
| 3488 | "fda08400.qcom,csid"), |
| 3489 | CLK_LOOKUP("csi_pix_clk", camss_csi1pix_clk.c, |
| 3490 | "fda08400.qcom,csid"), |
| 3491 | CLK_LOOKUP("csi_rdi_clk", camss_csi1rdi_clk.c, |
| 3492 | "fda08400.qcom,csid"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3493 | |
| 3494 | /* ISPIF clocks */ |
Sreesudhan Ramakrish Ramkumar | ecdcfce | 2013-04-17 12:58:26 -0700 | [diff] [blame] | 3495 | CLK_LOOKUP("ispif_ahb_clk", camss_ispif_ahb_clk.c, |
| 3496 | "fda0a000.qcom,ispif"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3497 | CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c, |
| 3498 | "fda0a000.qcom,ispif"), |
| 3499 | CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c, |
| 3500 | "fda0a000.qcom,ispif"), |
| 3501 | |
| 3502 | /* VFE clocks */ |
| 3503 | CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c, |
| 3504 | "fda10000.qcom,vfe"), |
| 3505 | CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda10000.qcom,vfe"), |
| 3506 | CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c, |
| 3507 | "fda10000.qcom,vfe"), |
| 3508 | CLK_LOOKUP("camss_csi_vfe_clk", camss_csi_vfe0_clk.c, |
| 3509 | "fda10000.qcom,vfe"), |
| 3510 | CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda10000.qcom,vfe"), |
| 3511 | CLK_LOOKUP("bus_clk", camss_vfe_vfe_axi_clk.c, "fda10000.qcom,vfe"), |
| 3512 | |
| 3513 | CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, |
| 3514 | "fda44000.qcom,iommu"), |
| 3515 | CLK_LOOKUP("core_clk", camss_vfe_vfe_axi_clk.c, "fda44000.qcom,iommu"), |
| 3516 | CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda44000.qcom,iommu"), |
| 3517 | |
| 3518 | /* Jpeg Clocks */ |
| 3519 | CLK_LOOKUP("core_clk", camss_jpeg_jpeg0_clk.c, "fda1c000.qcom,jpeg"), |
| 3520 | CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c, |
| 3521 | "fda1c000.qcom,jpeg"), |
| 3522 | CLK_LOOKUP("bus_clk0", camss_jpeg_jpeg_axi_clk.c, |
| 3523 | "fda1c000.qcom,jpeg"), |
| 3524 | CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c, |
| 3525 | "fda1c000.qcom,jpeg"), |
| 3526 | |
| 3527 | CLK_LOOKUP("alt_core_clk", camss_top_ahb_clk.c, "fda64000.qcom,iommu"), |
| 3528 | CLK_LOOKUP("iface_clk", camss_jpeg_jpeg_ahb_clk.c, |
| 3529 | "fda64000.qcom,iommu"), |
| 3530 | CLK_LOOKUP("core_clk", camss_jpeg_jpeg_axi_clk.c, |
| 3531 | "fda64000.qcom,iommu"), |
| 3532 | |
Su Liu | db7b206 | 2013-03-14 20:57:15 -0700 | [diff] [blame] | 3533 | CLK_LOOKUP("micro_iface_clk", camss_micro_ahb_clk.c, |
| 3534 | "fda04000.qcom,cpp"), |
| 3535 | CLK_LOOKUP("camss_top_ahb_clk", camss_top_ahb_clk.c, |
| 3536 | "fda04000.qcom,cpp"), |
| 3537 | CLK_LOOKUP("cpp_iface_clk", camss_vfe_cpp_ahb_clk.c, |
| 3538 | "fda04000.qcom,cpp"), |
| 3539 | CLK_LOOKUP("cpp_core_clk", camss_vfe_cpp_clk.c, "fda04000.qcom,cpp"), |
| 3540 | CLK_LOOKUP("cpp_bus_clk", camss_vfe_vfe_axi_clk.c, "fda04000.qcom,cpp"), |
| 3541 | CLK_LOOKUP("vfe_clk_src", vfe0_clk_src.c, "fda04000.qcom,cpp"), |
| 3542 | CLK_LOOKUP("camss_vfe_vfe_clk", camss_vfe_vfe0_clk.c, |
| 3543 | "fda04000.qcom,cpp"), |
| 3544 | CLK_LOOKUP("iface_clk", camss_vfe_vfe_ahb_clk.c, "fda04000.qcom,cpp"), |
| 3545 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3546 | /* KGSL Clocks */ |
| 3547 | CLK_LOOKUP("core_clk", oxili_gfx3d_clk.c, "fdb00000.qcom,kgsl-3d0"), |
| 3548 | CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb00000.qcom,kgsl-3d0"), |
liu zhong | c45eb8b | 2013-02-21 11:50:24 -0800 | [diff] [blame] | 3549 | CLK_LOOKUP("mem_iface_clk", oxilicx_axi_clk.c, |
| 3550 | "fdb00000.qcom,kgsl-3d0"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3551 | |
| 3552 | CLK_LOOKUP("alt_core_clk", oxili_gfx3d_clk.c, "fdb10000.qcom,iommu"), |
| 3553 | CLK_LOOKUP("iface_clk", oxilicx_ahb_clk.c, "fdb10000.qcom,iommu"), |
| 3554 | CLK_LOOKUP("core_clk", oxilicx_axi_clk.c, "fdb10000.qcom,iommu"), |
| 3555 | |
| 3556 | CLK_LOOKUP("core_clk", ocmemgx_core_clk.c, "fdd00000.qcom,ocmem"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3557 | |
| 3558 | /* Venus Clocks */ |
| 3559 | CLK_LOOKUP("core_clk", venus0_vcodec0_clk.c, "fdc00000.qcom,vidc"), |
| 3560 | CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc00000.qcom,vidc"), |
| 3561 | CLK_LOOKUP("bus_clk", venus0_axi_clk.c, "fdc00000.qcom,vidc"), |
| 3562 | |
| 3563 | CLK_LOOKUP("alt_core_clk", venus0_vcodec0_clk.c, |
| 3564 | "fdc84000.qcom,iommu"), |
| 3565 | CLK_LOOKUP("iface_clk", venus0_ahb_clk.c, "fdc84000.qcom,iommu"), |
| 3566 | CLK_LOOKUP("core_clk", venus0_axi_clk.c, "fdc84000.qcom,iommu"), |
Hariprasad Dhalinarasimha | 92a1322 | 2013-03-12 11:59:28 -0700 | [diff] [blame] | 3567 | CLK_LOOKUP("iface_clk", gcc_prng_ahb_clk.c, "f9bff000.qcom,msm-rng"), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3568 | CLK_LOOKUP("cam_gp0_clk", camss_gp0_clk.c, ""), |
| 3569 | CLK_LOOKUP("cam_gp1_clk", camss_gp1_clk.c, ""), |
| 3570 | CLK_LOOKUP("iface_clk", camss_micro_ahb_clk.c, ""), |
| 3571 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3572 | CLK_LOOKUP("", mmss_mmssnoc_axi_clk.c, ""), |
| 3573 | CLK_LOOKUP("", mmss_s0_axi_clk.c, ""), |
Bhalchandra Gajare | d5a4ba7 | 2013-03-11 16:15:13 -0700 | [diff] [blame] | 3574 | |
| 3575 | /* Audio clocks */ |
| 3576 | CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.224"), |
| 3577 | CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.4106"), |
| 3578 | CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16384"), |
| 3579 | CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16386"), |
| 3580 | CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16390"), |
| 3581 | CLK_LOOKUP("osr_clk", div_clk1.c, "msm-dai-q6-dev.16391"), |
| 3582 | |
Hariprasad Dhalinarasimha | 1fa5439 | 2013-03-21 15:57:51 -0700 | [diff] [blame] | 3583 | /* Add QCEDEV clocks */ |
| 3584 | CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "fd400000.qcom,qcedev"), |
| 3585 | CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "fd400000.qcom,qcedev"), |
| 3586 | CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "fd400000.qcom,qcedev"), |
| 3587 | CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "fd400000.qcom,qcedev"), |
| 3588 | |
| 3589 | /* Add QCRYPTO clocks */ |
| 3590 | CLK_LOOKUP("core_clk", gcc_ce1_clk.c, "fd404000.qcom,qcrypto"), |
| 3591 | CLK_LOOKUP("iface_clk", gcc_ce1_ahb_clk.c, "fd404000.qcom,qcrypto"), |
| 3592 | CLK_LOOKUP("bus_clk", gcc_ce1_axi_clk.c, "fd404000.qcom,qcrypto"), |
| 3593 | CLK_LOOKUP("core_clk_src", ce1_clk_src.c, "fd404000.qcom,qcrypto"), |
| 3594 | |
Aravind Venkateswaran | 78b7325 | 2013-05-08 18:25:21 -0700 | [diff] [blame] | 3595 | /* DSI PLL clocks */ |
| 3596 | CLK_LOOKUP("", dsi_vco_clk_8226.c, ""), |
| 3597 | CLK_LOOKUP("", analog_postdiv_clk_8226.c, ""), |
| 3598 | CLK_LOOKUP("", indirect_path_div2_clk_8226.c, ""), |
| 3599 | CLK_LOOKUP("", pixel_clk_src_8226.c, ""), |
| 3600 | CLK_LOOKUP("", byte_mux_8226.c, ""), |
| 3601 | CLK_LOOKUP("", byte_clk_src_8226.c, ""), |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3602 | }; |
| 3603 | |
| 3604 | static struct clk_lookup msm_clocks_8226_rumi[] = { |
| 3605 | CLK_DUMMY("core_clk", BLSP1_UART_CLK, "f991f000.serial", OFF), |
| 3606 | CLK_DUMMY("iface_clk", BLSP1_UART_CLK, "f991f000.serial", OFF), |
| 3607 | CLK_DUMMY("iface_clk", HSUSB_IFACE_CLK, "f9a55000.usb", OFF), |
| 3608 | CLK_DUMMY("core_clk", HSUSB_CORE_CLK, "f9a55000.usb", OFF), |
| 3609 | CLK_DUMMY("iface_clk", NULL, "msm_sdcc.1", OFF), |
| 3610 | CLK_DUMMY("core_clk", NULL, "msm_sdcc.1", OFF), |
| 3611 | CLK_DUMMY("bus_clk", NULL, "msm_sdcc.1", OFF), |
| 3612 | CLK_DUMMY("iface_clk", NULL, "msm_sdcc.2", OFF), |
| 3613 | CLK_DUMMY("core_clk", NULL, "msm_sdcc.2", OFF), |
| 3614 | CLK_DUMMY("bus_clk", NULL, "msm_sdcc.2", OFF), |
| 3615 | }; |
| 3616 | |
| 3617 | struct clock_init_data msm8226_rumi_clock_init_data __initdata = { |
| 3618 | .table = msm_clocks_8226_rumi, |
| 3619 | .size = ARRAY_SIZE(msm_clocks_8226_rumi), |
| 3620 | }; |
| 3621 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3622 | static void __init reg_init(void) |
| 3623 | { |
Patrick Daly | e02a563 | 2013-02-12 20:23:35 -0800 | [diff] [blame] | 3624 | u32 regval; |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3625 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3626 | /* Vote for GPLL0 to turn on. Needed by acpuclock. */ |
| 3627 | regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE)); |
| 3628 | regval |= BIT(0); |
| 3629 | writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE)); |
| 3630 | |
| 3631 | /* |
Patrick Daly | 3668dd6 | 2013-03-04 20:27:55 -0800 | [diff] [blame] | 3632 | * No clocks need to be enabled during sleep. |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3633 | */ |
| 3634 | writel_relaxed(0x0, GCC_REG_BASE(APCS_CLOCK_SLEEP_ENA_VOTE)); |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3635 | } |
Patrick Daly | e02a563 | 2013-02-12 20:23:35 -0800 | [diff] [blame] | 3636 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3637 | static void __init msm8226_clock_post_init(void) |
| 3638 | { |
Vikram Mulukutla | 441db7a | 2013-03-15 13:56:33 -0700 | [diff] [blame] | 3639 | /* |
| 3640 | * Hold an active set vote for CXO; this is because CXO is expected |
| 3641 | * to remain on whenever CPUs aren't power collapsed. |
| 3642 | */ |
| 3643 | clk_prepare_enable(&xo_a_clk.c); |
| 3644 | |
Patrick Daly | 856c2fe | 2013-07-18 12:59:40 -0700 | [diff] [blame] | 3645 | /* |
| 3646 | * Handoff will override the prepare enable count as well as the rate |
| 3647 | * Set them again. |
| 3648 | */ |
| 3649 | clk_set_rate(&mmssnoc_ahb_a_clk.c, 40000000); |
| 3650 | clk_prepare_enable(&mmssnoc_ahb_a_clk.c); |
| 3651 | |
Patrick Daly | fd3df10 | 2013-05-28 18:08:22 -0700 | [diff] [blame] | 3652 | /* Set an initial rate (fmax at nominal) on the MMSSNOC AXI clock */ |
| 3653 | clk_set_rate(&axi_clk_src.c, 200000000); |
| 3654 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3655 | /* Set rates for single-rate clocks. */ |
| 3656 | clk_set_rate(&usb_hs_system_clk_src.c, |
| 3657 | usb_hs_system_clk_src.freq_tbl[0].freq_hz); |
| 3658 | clk_set_rate(&usb_hsic_clk_src.c, |
| 3659 | usb_hsic_clk_src.freq_tbl[0].freq_hz); |
| 3660 | clk_set_rate(&usb_hsic_io_cal_clk_src.c, |
| 3661 | usb_hsic_io_cal_clk_src.freq_tbl[0].freq_hz); |
| 3662 | clk_set_rate(&usb_hsic_system_clk_src.c, |
| 3663 | usb_hsic_system_clk_src.freq_tbl[0].freq_hz); |
| 3664 | clk_set_rate(&pdm2_clk_src.c, pdm2_clk_src.freq_tbl[0].freq_hz); |
| 3665 | clk_set_rate(&cci_clk_src.c, cci_clk_src.freq_tbl[0].freq_hz); |
| 3666 | clk_set_rate(&mclk0_clk_src.c, mclk0_clk_src.freq_tbl[0].freq_hz); |
| 3667 | clk_set_rate(&mclk1_clk_src.c, mclk1_clk_src.freq_tbl[0].freq_hz); |
| 3668 | clk_set_rate(&esc0_clk_src.c, esc0_clk_src.freq_tbl[0].freq_hz); |
| 3669 | clk_set_rate(&vsync_clk_src.c, vsync_clk_src.freq_tbl[0].freq_hz); |
Patrick Daly | 01d4c1d | 2013-05-22 19:10:55 -0700 | [diff] [blame] | 3670 | |
| 3671 | clk_set_rate(&kpss_ahb_clk_src.c, 19200000); |
| 3672 | clk_prepare_enable(&kpss_ahb_clk_src.c); |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3673 | } |
| 3674 | |
| 3675 | #define GCC_CC_PHYS 0xFC400000 |
| 3676 | #define GCC_CC_SIZE SZ_16K |
| 3677 | |
| 3678 | #define MMSS_CC_PHYS 0xFD8C0000 |
| 3679 | #define MMSS_CC_SIZE SZ_256K |
| 3680 | |
| 3681 | #define LPASS_CC_PHYS 0xFE000000 |
| 3682 | #define LPASS_CC_SIZE SZ_256K |
| 3683 | |
| 3684 | #define APCS_KPSS_SH_PLL_PHYS 0xF9016000 |
| 3685 | #define APCS_KPSS_SH_PLL_SIZE SZ_64 |
| 3686 | |
| 3687 | #define APCS_KPSS_GLB_PHYS 0xF9011000 |
| 3688 | #define APCS_KPSS_GLB_SIZE SZ_4K |
| 3689 | |
| 3690 | |
| 3691 | static void __init msm8226_clock_pre_init(void) |
| 3692 | { |
| 3693 | virt_bases[GCC_BASE] = ioremap(GCC_CC_PHYS, GCC_CC_SIZE); |
| 3694 | if (!virt_bases[GCC_BASE]) |
| 3695 | panic("clock-8226: Unable to ioremap GCC memory!"); |
| 3696 | |
| 3697 | virt_bases[MMSS_BASE] = ioremap(MMSS_CC_PHYS, MMSS_CC_SIZE); |
| 3698 | if (!virt_bases[MMSS_BASE]) |
| 3699 | panic("clock-8226: Unable to ioremap MMSS_CC memory!"); |
| 3700 | |
| 3701 | virt_bases[LPASS_BASE] = ioremap(LPASS_CC_PHYS, LPASS_CC_SIZE); |
| 3702 | if (!virt_bases[LPASS_BASE]) |
| 3703 | panic("clock-8226: Unable to ioremap LPASS_CC memory!"); |
| 3704 | |
| 3705 | virt_bases[APCS_BASE] = ioremap(APCS_KPSS_GLB_PHYS, |
| 3706 | APCS_KPSS_GLB_SIZE); |
| 3707 | if (!virt_bases[APCS_BASE]) |
| 3708 | panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!"); |
| 3709 | |
| 3710 | virt_bases[APCS_PLL_BASE] = ioremap(APCS_KPSS_SH_PLL_PHYS, |
| 3711 | APCS_KPSS_SH_PLL_SIZE); |
| 3712 | if (!virt_bases[APCS_PLL_BASE]) |
| 3713 | panic("clock-8226: Unable to ioremap APCS_GCC_CC memory!"); |
| 3714 | |
| 3715 | clk_ops_local_pll.enable = sr_hpm_lp_pll_clk_enable; |
| 3716 | |
Patrick Daly | ebc26bc | 2013-02-05 11:49:07 -0800 | [diff] [blame] | 3717 | vdd_dig.regulator[0] = regulator_get(NULL, "vdd_dig"); |
| 3718 | if (IS_ERR(vdd_dig.regulator[0])) |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3719 | panic("clock-8226: Unable to get the vdd_dig regulator!"); |
| 3720 | |
Patrick Daly | ebc26bc | 2013-02-05 11:49:07 -0800 | [diff] [blame] | 3721 | vdd_sr2_pll.regulator[0] = regulator_get(NULL, "vdd_sr2_pll"); |
| 3722 | if (IS_ERR(vdd_sr2_pll.regulator[0])) |
Patrick Daly | 48e00f3 | 2013-01-28 19:13:47 -0800 | [diff] [blame] | 3723 | panic("clock-8226: Unable to get the sr2_pll regulator!"); |
| 3724 | |
Patrick Daly | 6fb589a | 2013-03-29 17:55:55 -0700 | [diff] [blame] | 3725 | vdd_sr2_pll.regulator[1] = regulator_get(NULL, "vdd_sr2_dig"); |
| 3726 | if (IS_ERR(vdd_sr2_pll.regulator[1])) |
| 3727 | panic("clock-8226: Unable to get the vdd_sr2_dig regulator!"); |
| 3728 | |
Patrick Daly | 856c2fe | 2013-07-18 12:59:40 -0700 | [diff] [blame] | 3729 | |
| 3730 | enable_rpm_scaling(); |
| 3731 | |
Patrick Daly | 48e00f3 | 2013-01-28 19:13:47 -0800 | [diff] [blame] | 3732 | /* |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3733 | * Hold an active set vote at a rate of 40MHz for the MMSS NOC AHB |
| 3734 | * source. Sleep set vote is 0. |
| 3735 | * RPM will also turn on gcc_mmss_noc_cfg_ahb_clk, which is needed to |
| 3736 | * access mmss clock controller registers. |
| 3737 | */ |
| 3738 | clk_set_rate(&mmssnoc_ahb_a_clk.c, 40000000); |
Patrick Daly | 856c2fe | 2013-07-18 12:59:40 -0700 | [diff] [blame] | 3739 | clk_prepare_enable(&mmssnoc_ahb_a_clk.c); |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3740 | |
| 3741 | reg_init(); |
Patrick Daly | 5555c2c | 2013-03-06 21:25:26 -0800 | [diff] [blame] | 3742 | |
Patrick Daly | d3fd03f | 2013-03-08 19:01:18 -0800 | [diff] [blame] | 3743 | /* v2 specific changes */ |
| 3744 | if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) { |
| 3745 | cpp_clk_src.c.fmax = camss_vfe_cpp_fmax_v2; |
| 3746 | vfe0_clk_src.c.fmax = camss_vfe_vfe0_fmax_v2; |
| 3747 | } |
| 3748 | |
Aravind Venkateswaran | 78b7325 | 2013-05-08 18:25:21 -0700 | [diff] [blame] | 3749 | clk_ops_pixel_clock = clk_ops_pixel; |
| 3750 | clk_ops_pixel_clock.set_rate = set_rate_pixel; |
| 3751 | clk_ops_pixel_clock.round_rate = round_rate_pixel; |
| 3752 | |
Patrick Daly | 5555c2c | 2013-03-06 21:25:26 -0800 | [diff] [blame] | 3753 | /* |
| 3754 | * MDSS needs the ahb clock and needs to init before we register the |
| 3755 | * lookup table. |
| 3756 | */ |
| 3757 | mdss_clk_ctrl_pre_init(&mdss_ahb_clk.c); |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3758 | } |
| 3759 | |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3760 | struct clock_init_data msm8226_clock_init_data __initdata = { |
| 3761 | .table = msm_clocks_8226, |
| 3762 | .size = ARRAY_SIZE(msm_clocks_8226), |
| 3763 | .pre_init = msm8226_clock_pre_init, |
| 3764 | .post_init = msm8226_clock_post_init, |
Patrick Daly | eb370ea | 2012-10-23 11:57:50 -0700 | [diff] [blame] | 3765 | }; |