Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / kernel / msm / 6502fbfaf81b09b3f474bb7b3796257e9450273e / . / drivers / gpu / drm / radeon / radeon_drv.h
blob: 3933f8216a34d8aa43cb536b7157c0e7cc6d4c21 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__
33
34/* General customization:
35 */
36
37#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon"
Dave Airliec0beb2a2008-05-28 13:52:28 +1000[diff] [blame]41#define DRIVER_DATE "20080528"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]42
43/* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]71 * clients use to tell the DRM where they think the framebuffer is
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
Dave Airlied985c102006-01-02 21:32:48 +1100[diff] [blame]76 * (No 3D support yet - just microcode loading).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]85 * 1.17- Add initial support for R300 (3D).
Dave Airlie9d176012005-09-11 19:55:53 +1000[diff] [blame]86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]90 * 1.19- Add support for gart table in FB memory and PCIE r300
Dave Airlied985c102006-01-02 21:32:48 +1100[diff] [blame]91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
Dave Airlie4e5e2e22006-02-18 15:51:35 +1100[diff] [blame]93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
Dave Airlied5ea7022006-03-19 19:37:55 +1100[diff] [blame]94 * 1.23- Add new radeon memory map work from benh
Dave Airlieee4621f2006-03-19 19:45:26 +1100[diff] [blame]95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
Dave Airlied6fece02006-06-24 17:04:07 +1000[diff] [blame]96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
Dave Airlief2b04cd2007-05-08 15:19:23 +1000[diff] [blame]98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
Dave Airlieddbee332007-07-11 12:16:01 +1000[diff] [blame]100 * 1.28- Add support for VBL on CRTC2
Dave Airliec0beb2a2008-05-28 13:52:28 +1000[diff] [blame]101 * 1.29- R500 3D cmd buffer support
Maciej Cencorae8a13442009-04-17 15:55:09 +0200[diff] [blame]102 * 1.30- Add support for occlusion queries
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]103 */
104#define DRIVER_MAJOR 1
Maciej Cencorae8a13442009-04-17 15:55:09 +0200[diff] [blame]105#define DRIVER_MINOR 30
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]106#define DRIVER_PATCHLEVEL 0
107
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]108/*
109 * Radeon chip families
110 */
111enum radeon_family {
112 CHIP_R100,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]113 CHIP_RV100,
Dave Airliedfab1152006-03-19 20:01:37 +1100[diff] [blame]114 CHIP_RS100,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]115 CHIP_RV200,
116 CHIP_RS200,
Dave Airliedfab1152006-03-19 20:01:37 +1100[diff] [blame]117 CHIP_R200,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]118 CHIP_RV250,
Dave Airliedfab1152006-03-19 20:01:37 +1100[diff] [blame]119 CHIP_RS300,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]120 CHIP_RV280,
121 CHIP_R300,
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]122 CHIP_R350,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]123 CHIP_RV350,
Dave Airliedfab1152006-03-19 20:01:37 +1100[diff] [blame]124 CHIP_RV380,
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]125 CHIP_R420,
Alex Deucheredc6f382008-10-17 09:21:45 +1000[diff] [blame]126 CHIP_R423,
Dave Airliedfab1152006-03-19 20:01:37 +1100[diff] [blame]127 CHIP_RV410,
Alex Deucherb2ceddf2008-10-17 09:19:33 +1000[diff] [blame]128 CHIP_RS400,
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]129 CHIP_RS480,
Alex Deucherc1556f72009-02-25 16:57:49 -0500[diff] [blame]130 CHIP_RS600,
Maciej Cencora60f92682008-02-19 21:32:45 +1000[diff] [blame]131 CHIP_RS690,
Alex Deucherf0738e92008-10-16 17:12:02 +1000[diff] [blame]132 CHIP_RS740,
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]133 CHIP_RV515,
134 CHIP_R520,
135 CHIP_RV530,
136 CHIP_RV560,
137 CHIP_RV570,
138 CHIP_R580,
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]139 CHIP_R600,
140 CHIP_RV610,
141 CHIP_RV630,
142 CHIP_RV620,
143 CHIP_RV635,
144 CHIP_RV670,
145 CHIP_RS780,
Alex Deucher6502fbf2009-08-04 11:24:24 -0400[diff] [blame^]146 CHIP_RS880,
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]147 CHIP_RV770,
148 CHIP_RV730,
149 CHIP_RV710,
Alex Deucher2a71ebc2009-06-12 15:53:10 +1000[diff] [blame]150 CHIP_RV740,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]151 CHIP_LAST,
152};
153
154enum radeon_cp_microcode_version {
155 UCODE_R100,
156 UCODE_R200,
157 UCODE_R300,
158};
159
160/*
161 * Chip flags
162 */
163enum radeon_chip_flags {
Dave Airlie54a56ac2006-09-22 04:25:09 +1000[diff] [blame]164 RADEON_FAMILY_MASK = 0x0000ffffUL,
165 RADEON_FLAGS_MASK = 0xffff0000UL,
166 RADEON_IS_MOBILITY = 0x00010000UL,
167 RADEON_IS_IGP = 0x00020000UL,
168 RADEON_SINGLE_CRTC = 0x00040000UL,
169 RADEON_IS_AGP = 0x00080000UL,
170 RADEON_HAS_HIERZ = 0x00100000UL,
171 RADEON_IS_PCIE = 0x00200000UL,
172 RADEON_NEW_MEMMAP = 0x00400000UL,
173 RADEON_IS_PCI = 0x00800000UL,
Dave Airlief2b04cd2007-05-08 15:19:23 +1000[diff] [blame]174 RADEON_IS_IGPGART = 0x01000000UL,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]175};
176
177typedef struct drm_radeon_freelist {
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]178 unsigned int age;
Dave Airlie056219e2007-07-11 16:17:42 +1000[diff] [blame]179 struct drm_buf *buf;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]180 struct drm_radeon_freelist *next;
181 struct drm_radeon_freelist *prev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]182} drm_radeon_freelist_t;
183
184typedef struct drm_radeon_ring_buffer {
185 u32 *start;
186 u32 *end;
187 int size;
188 int size_l2qw;
189
Roland Scheidegger576cc452008-02-07 14:59:24 +1000[diff] [blame]190 int rptr_update; /* Double Words */
191 int rptr_update_l2qw; /* log2 Quad Words */
192
193 int fetch_size; /* Double Words */
194 int fetch_size_l2ow; /* log2 Oct Words */
195
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]196 u32 tail;
197 u32 tail_mask;
198 int space;
199
200 int high_mark;
201} drm_radeon_ring_buffer_t;
202
203typedef struct drm_radeon_depth_clear_t {
204 u32 rb3d_cntl;
205 u32 rb3d_zstencilcntl;
206 u32 se_cntl;
207} drm_radeon_depth_clear_t;
208
209struct drm_radeon_driver_file_fields {
210 int64_t radeon_fb_delta;
211};
212
213struct mem_block {
214 struct mem_block *next;
215 struct mem_block *prev;
216 int start;
217 int size;
Eric Anholt6c340ea2007-08-25 20:23:09 +1000[diff] [blame]218 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]219};
220
221struct radeon_surface {
222 int refcount;
223 u32 lower;
224 u32 upper;
225 u32 flags;
226};
227
228struct radeon_virt_surface {
229 int surface_index;
230 u32 lower;
231 u32 upper;
232 u32 flags;
Eric Anholt6c340ea2007-08-25 20:23:09 +1000[diff] [blame]233 struct drm_file *file_priv;
David Miller6abf6bb2009-02-14 01:51:07 -0800[diff] [blame]234#define PCIGART_FILE_PRIV ((void *) -1L)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]235};
236
David Millerb2665032009-02-12 02:15:39 -0800[diff] [blame]237#define RADEON_FLUSH_EMITED (1 << 0)
238#define RADEON_PURGE_EMITED (1 << 1)
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]239
Dave Airlie7c1c2872008-11-28 14:22:24 +1000[diff] [blame]240struct drm_radeon_master_private {
241 drm_local_map_t *sarea;
242 drm_radeon_sarea_t *sarea_priv;
243};
244
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]245typedef struct drm_radeon_private {
246 drm_radeon_ring_buffer_t ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]247
248 u32 fb_location;
Dave Airlied5ea7022006-03-19 19:37:55 +1100[diff] [blame]249 u32 fb_size;
250 int new_memmap;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]251
252 int gart_size;
253 u32 gart_vm_start;
254 unsigned long gart_buffers_offset;
255
256 int cp_mode;
257 int cp_running;
258
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]259 drm_radeon_freelist_t *head;
260 drm_radeon_freelist_t *tail;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]261 int last_buf;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]262 int writeback_works;
263
264 int usec_timeout;
265
266 int microcode_version;
267
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]268 struct {
269 u32 boxes;
270 int freelist_timeouts;
271 int freelist_loops;
272 int requested_bufs;
273 int last_frame_reads;
274 int last_clear_reads;
275 int clears;
276 int texture_uploads;
277 } stats;
278
279 int do_boxes;
280 int page_flipping;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]281
282 u32 color_fmt;
283 unsigned int front_offset;
284 unsigned int front_pitch;
285 unsigned int back_offset;
286 unsigned int back_pitch;
287
288 u32 depth_fmt;
289 unsigned int depth_offset;
290 unsigned int depth_pitch;
291
292 u32 front_pitch_offset;
293 u32 back_pitch_offset;
294 u32 depth_pitch_offset;
295
296 drm_radeon_depth_clear_t depth_clear;
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]297
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]298 unsigned long ring_offset;
299 unsigned long ring_rptr_offset;
300 unsigned long buffers_offset;
301 unsigned long gart_textures_offset;
302
303 drm_local_map_t *sarea;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]304 drm_local_map_t *cp_ring;
305 drm_local_map_t *ring_rptr;
306 drm_local_map_t *gart_textures;
307
308 struct mem_block *gart_heap;
309 struct mem_block *fb_heap;
310
311 /* SW interrupt */
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]312 wait_queue_head_t swi_queue;
313 atomic_t swi_emitted;
Dave Airlieddbee332007-07-11 12:16:01 +1000[diff] [blame]314 int vblank_crtc;
315 uint32_t irq_enable_reg;
Dave Airliec0beb2a2008-05-28 13:52:28 +1000[diff] [blame]316 uint32_t r500_disp_irq_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]317
318 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]319 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]320
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]321 unsigned long pcigart_offset;
Dave Airlief2b04cd2007-05-08 15:19:23 +1000[diff] [blame]322 unsigned int pcigart_offset_set;
Dave Airlie55910512007-07-11 16:53:40 +1000[diff] [blame]323 struct drm_ati_pcigart_info gart_info;
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]324
Dave Airlieee4621f2006-03-19 19:45:26 +1100[diff] [blame]325 u32 scratch_ages[5];
326
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]327 /* starting from here on, data is preserved accross an open */
328 uint32_t flags; /* see radeon_chip_flags */
Benjamin Herrenschmidtd883f7f2009-02-02 16:55:45 +1100[diff] [blame]329 resource_size_t fb_aper_offset;
Alex Deucher5b92c402008-05-28 11:57:40 +1000[diff] [blame]330
331 int num_gb_pipes;
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]332 int track_flush;
Dave Airlie78538bf2008-11-11 17:56:16 +1000[diff] [blame]333 drm_local_map_t *mmio;
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]334
335 /* r6xx/r7xx pipe/shader config */
336 int r600_max_pipes;
337 int r600_max_tile_pipes;
338 int r600_max_simds;
339 int r600_max_backends;
340 int r600_max_gprs;
341 int r600_max_threads;
342 int r600_max_stack_entries;
343 int r600_max_hw_contexts;
344 int r600_max_gs_threads;
345 int r600_sx_max_export_size;
346 int r600_sx_max_export_pos_size;
347 int r600_sx_max_export_smx_size;
348 int r600_sq_num_cf_insts;
349 int r700_sx_num_of_sets;
350 int r700_sc_prim_fifo_size;
351 int r700_sc_hiz_tile_fifo_size;
352 int r700_sc_earlyz_tile_fifo_fize;
353
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]354} drm_radeon_private_t;
355
356typedef struct drm_radeon_buf_priv {
357 u32 age;
358} drm_radeon_buf_priv_t;
359
Dave Airlieb3a83632005-09-30 18:37:36 +1000[diff] [blame]360typedef struct drm_radeon_kcmd_buffer {
361 int bufsz;
362 char *buf;
363 int nbox;
Dave Airliec60ce622007-07-11 15:27:12 +1000[diff] [blame]364 struct drm_clip_rect __user *boxes;
Dave Airlieb3a83632005-09-30 18:37:36 +1000[diff] [blame]365} drm_radeon_kcmd_buffer_t;
366
Dave Airlie689b9d72005-09-30 17:09:07 +1000[diff] [blame]367extern int radeon_no_wb;
Eric Anholtc153f452007-09-03 12:06:45 +1000[diff] [blame]368extern struct drm_ioctl_desc radeon_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +1000[diff] [blame]369extern int radeon_max_ioctl;
370
David Millerb07fa022009-02-12 02:15:37 -0800[diff] [blame]371extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
372extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
373
374#define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv)
375#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)
376
=?utf-8?q?Michel_D=C3=A4nzer?=1d6bb8e2006-12-15 18:54:35 +1100[diff] [blame]377/* Check whether the given hardware address is inside the framebuffer or the
378 * GART area.
379 */
380static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
381 u64 off)
382{
383 u32 fb_start = dev_priv->fb_location;
384 u32 fb_end = fb_start + dev_priv->fb_size - 1;
385 u32 gart_start = dev_priv->gart_vm_start;
386 u32 gart_end = gart_start + dev_priv->gart_size - 1;
387
388 return ((off >= fb_start && off <= fb_end) ||
389 (off >= gart_start && off <= gart_end));
390}
391
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]392 /* radeon_cp.c */
Eric Anholtc153f452007-09-03 12:06:45 +1000[diff] [blame]393extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
394extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
395extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
396extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
397extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
398extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
399extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
400extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
401extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]402extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
Alex Deucherc05ce082009-02-24 16:22:29 -0500[diff] [blame]403extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
404extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]405extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]406
Dave Airlie84b1fd12007-07-11 15:53:27 +1000[diff] [blame]407extern void radeon_freelist_reset(struct drm_device * dev);
Dave Airlie056219e2007-07-11 16:17:42 +1000[diff] [blame]408extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]409
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]410extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]411
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]412extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]413
414extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
Dave Airlie836cf042005-07-10 19:27:04 +1000[diff] [blame]415extern int radeon_presetup(struct drm_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]416extern int radeon_driver_postcleanup(struct drm_device *dev);
417
Eric Anholtc153f452007-09-03 12:06:45 +1000[diff] [blame]418extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
419extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
420extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]421extern void radeon_mem_takedown(struct mem_block **heap);
Eric Anholt6c340ea2007-08-25 20:23:09 +1000[diff] [blame]422extern void radeon_mem_release(struct drm_file *file_priv,
423 struct mem_block *heap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]424
Alex Deucherc05ce082009-02-24 16:22:29 -0500[diff] [blame]425extern void radeon_enable_bm(struct drm_radeon_private *dev_priv);
426extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off);
427extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val);
428
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]429 /* radeon_irq.c */
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]430extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
Eric Anholtc153f452007-09-03 12:06:45 +1000[diff] [blame]431extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
432extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]433
Dave Airlie84b1fd12007-07-11 15:53:27 +1000[diff] [blame]434extern void radeon_do_release(struct drm_device * dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]435extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
436extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
437extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]438extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000[diff] [blame]439extern void radeon_driver_irq_preinstall(struct drm_device * dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]440extern int radeon_driver_irq_postinstall(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000[diff] [blame]441extern void radeon_driver_irq_uninstall(struct drm_device * dev);
Dennis Kasprzyk7ecabc52008-06-19 12:36:55 +1000[diff] [blame]442extern void radeon_enable_interrupt(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000[diff] [blame]443extern int radeon_vblank_crtc_get(struct drm_device *dev);
444extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]445
Dave Airlie22eae942005-11-10 22:16:34 +1100[diff] [blame]446extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
447extern int radeon_driver_unload(struct drm_device *dev);
448extern int radeon_driver_firstopen(struct drm_device *dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]449extern void radeon_driver_preclose(struct drm_device *dev,
450 struct drm_file *file_priv);
451extern void radeon_driver_postclose(struct drm_device *dev,
452 struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +1000[diff] [blame]453extern void radeon_driver_lastclose(struct drm_device * dev);
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]454extern int radeon_driver_open(struct drm_device *dev,
455 struct drm_file *file_priv);
Dave Airlie9a186642005-06-23 21:29:18 +1000[diff] [blame]456extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
457 unsigned long arg);
458
Dave Airlie7c1c2872008-11-28 14:22:24 +1000[diff] [blame]459extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
460extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
461extern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master);
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]462/* r300_cmdbuf.c */
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]463extern void r300_init_reg_flags(struct drm_device *dev);
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]464
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]465extern int r300_do_cp_cmdbuf(struct drm_device *dev,
Eric Anholt6c340ea2007-08-25 20:23:09 +1000[diff] [blame]466 struct drm_file *file_priv,
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]467 drm_radeon_kcmd_buffer_t *cmdbuf);
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]468
Alex Deucherc05ce082009-02-24 16:22:29 -0500[diff] [blame]469/* r600_cp.c */
470extern int r600_do_engine_reset(struct drm_device *dev);
471extern int r600_do_cleanup_cp(struct drm_device *dev);
472extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
473 struct drm_file *file_priv);
474extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv);
475extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv);
476extern void r600_do_cp_start(drm_radeon_private_t *dev_priv);
477extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv);
478extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv);
479extern int r600_cp_dispatch_indirect(struct drm_device *dev,
480 struct drm_buf *buf, int start, int end);
Alex Deucherc1556f72009-02-25 16:57:49 -0500[diff] [blame]481extern int r600_page_table_init(struct drm_device *dev);
482extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
Alex Deucherc05ce082009-02-24 16:22:29 -0500[diff] [blame]483
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]484/* Flags for stats.boxes
485 */
486#define RADEON_BOX_DMA_IDLE 0x1
487#define RADEON_BOX_RING_FULL 0x2
488#define RADEON_BOX_FLIP 0x4
489#define RADEON_BOX_WAIT_IDLE 0x8
490#define RADEON_BOX_TEXTURE_LOAD 0x10
491
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]492/* Register definitions, register access macros and drmAddMap constants
493 * for Radeon kernel driver.
494 */
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]495#define RADEON_MM_INDEX 0x0000
496#define RADEON_MM_DATA 0x0004
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]497
498#define RADEON_AGP_COMMAND 0x0f60
Dave Airlied985c102006-01-02 21:32:48 +1100[diff] [blame]499#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
500# define RADEON_AGP_ENABLE (1<<8)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]501#define RADEON_AUX_SCISSOR_CNTL 0x26f0
502# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
503# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
504# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
505# define RADEON_SCISSOR_0_ENABLE (1 << 28)
506# define RADEON_SCISSOR_1_ENABLE (1 << 29)
507# define RADEON_SCISSOR_2_ENABLE (1 << 30)
508
Alex Deucheredc6f382008-10-17 09:21:45 +1000[diff] [blame]509/*
510 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
511 * don't have an explicit bus mastering disable bit. It's handled
512 * by the PCI D-states. PMI_BM_DIS disables D-state bus master
513 * handling, not bus mastering itself.
514 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]515#define RADEON_BUS_CNTL 0x0030
Alex Deucher4e270e92008-10-28 07:48:34 +1000[diff] [blame]516/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]517# define RADEON_BUS_MASTER_DIS (1 << 6)
Alex Deucher4e270e92008-10-28 07:48:34 +1000[diff] [blame]518/* rs600/rs690/rs740 */
519# define RS600_BUS_MASTER_DIS (1 << 14)
520# define RS600_MSI_REARM (1 << 20)
521/* see RS400_MSI_REARM in AIC_CNTL for rs480 */
Alex Deucheredc6f382008-10-17 09:21:45 +1000[diff] [blame]522
523#define RADEON_BUS_CNTL1 0x0034
524# define RADEON_PMI_BM_DIS (1 << 2)
525# define RADEON_PMI_INT_DIS (1 << 3)
526
527#define RV370_BUS_CNTL 0x004c
528# define RV370_PMI_BM_DIS (1 << 5)
529# define RV370_PMI_INT_DIS (1 << 6)
530
531#define RADEON_MSI_REARM_EN 0x0160
532/* rv370/rv380, rv410, r423/r430/r480, r5xx */
533# define RV370_MSI_REARM_EN (1 << 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]534
535#define RADEON_CLOCK_CNTL_DATA 0x000c
536# define RADEON_PLL_WR_EN (1 << 7)
537#define RADEON_CLOCK_CNTL_INDEX 0x0008
538#define RADEON_CONFIG_APER_SIZE 0x0108
Dave Airlied985c102006-01-02 21:32:48 +1100[diff] [blame]539#define RADEON_CONFIG_MEMSIZE 0x00f8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]540#define RADEON_CRTC_OFFSET 0x0224
541#define RADEON_CRTC_OFFSET_CNTL 0x0228
542# define RADEON_CRTC_TILE_EN (1 << 15)
543# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
544#define RADEON_CRTC2_OFFSET 0x0324
545#define RADEON_CRTC2_OFFSET_CNTL 0x0328
546
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]547#define RADEON_PCIE_INDEX 0x0030
548#define RADEON_PCIE_DATA 0x0034
549#define RADEON_PCIE_TX_GART_CNTL 0x10
Dave Airliebc5f4522007-11-05 12:50:58 +1000[diff] [blame]550# define RADEON_PCIE_TX_GART_EN (1 << 0)
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]551# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
552# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
553# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
554# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
555# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
556# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
557# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]558#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
559#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
Dave Airliebc5f4522007-11-05 12:50:58 +1000[diff] [blame]560#define RADEON_PCIE_TX_GART_BASE 0x13
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]561#define RADEON_PCIE_TX_GART_START_LO 0x14
562#define RADEON_PCIE_TX_GART_START_HI 0x15
563#define RADEON_PCIE_TX_GART_END_LO 0x16
564#define RADEON_PCIE_TX_GART_END_HI 0x17
565
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]566#define RS480_NB_MC_INDEX 0x168
567# define RS480_NB_MC_IND_WR_EN (1 << 8)
568#define RS480_NB_MC_DATA 0x16c
Dave Airlief2b04cd2007-05-08 15:19:23 +1000[diff] [blame]569
Maciej Cencora60f92682008-02-19 21:32:45 +1000[diff] [blame]570#define RS690_MC_INDEX 0x78
571# define RS690_MC_INDEX_MASK 0x1ff
572# define RS690_MC_INDEX_WR_EN (1 << 9)
573# define RS690_MC_INDEX_WR_ACK 0x7f
574#define RS690_MC_DATA 0x7c
575
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]576/* MC indirect registers */
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]577#define RS480_MC_MISC_CNTL 0x18
578# define RS480_DISABLE_GTW (1 << 1)
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]579/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]580# define RS480_GART_INDEX_REG_EN (1 << 12)
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]581# define RS690_BLOCK_GFX_D3_EN (1 << 14)
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]582#define RS480_K8_FB_LOCATION 0x1e
583#define RS480_GART_FEATURE_ID 0x2b
584# define RS480_HANG_EN (1 << 11)
585# define RS480_TLB_ENABLE (1 << 18)
586# define RS480_P2P_ENABLE (1 << 19)
587# define RS480_GTW_LAC_EN (1 << 25)
588# define RS480_2LEVEL_GART (0 << 30)
589# define RS480_1LEVEL_GART (1 << 30)
590# define RS480_PDC_EN (1 << 31)
591#define RS480_GART_BASE 0x2c
592#define RS480_GART_CACHE_CNTRL 0x2e
593# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
594#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
595# define RS480_GART_EN (1 << 0)
596# define RS480_VA_SIZE_32MB (0 << 1)
597# define RS480_VA_SIZE_64MB (1 << 1)
598# define RS480_VA_SIZE_128MB (2 << 1)
599# define RS480_VA_SIZE_256MB (3 << 1)
600# define RS480_VA_SIZE_512MB (4 << 1)
601# define RS480_VA_SIZE_1GB (5 << 1)
602# define RS480_VA_SIZE_2GB (6 << 1)
603#define RS480_AGP_MODE_CNTL 0x39
604# define RS480_POST_GART_Q_SIZE (1 << 18)
605# define RS480_NONGART_SNOOP (1 << 19)
606# define RS480_AGP_RD_BUF_SIZE (1 << 20)
607# define RS480_REQ_TYPE_SNOOP_SHIFT 22
608# define RS480_REQ_TYPE_SNOOP_MASK 0x3
609# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
610#define RS480_MC_MISC_UMA_CNTL 0x5f
611#define RS480_MC_MCLK_CNTL 0x7a
612#define RS480_MC_UMA_DUALCH_CNTL 0x86
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]613
Maciej Cencora60f92682008-02-19 21:32:45 +1000[diff] [blame]614#define RS690_MC_FB_LOCATION 0x100
615#define RS690_MC_AGP_LOCATION 0x101
616#define RS690_MC_AGP_BASE 0x102
Dave Airlie3722bfc2008-05-28 11:28:27 +1000[diff] [blame]617#define RS690_MC_AGP_BASE_2 0x103
Maciej Cencora60f92682008-02-19 21:32:45 +1000[diff] [blame]618
Alex Deucherc1556f72009-02-25 16:57:49 -0500[diff] [blame]619#define RS600_MC_INDEX 0x70
620# define RS600_MC_ADDR_MASK 0xffff
621# define RS600_MC_IND_SEQ_RBS_0 (1 << 16)
622# define RS600_MC_IND_SEQ_RBS_1 (1 << 17)
623# define RS600_MC_IND_SEQ_RBS_2 (1 << 18)
624# define RS600_MC_IND_SEQ_RBS_3 (1 << 19)
625# define RS600_MC_IND_AIC_RBS (1 << 20)
626# define RS600_MC_IND_CITF_ARB0 (1 << 21)
627# define RS600_MC_IND_CITF_ARB1 (1 << 22)
628# define RS600_MC_IND_WR_EN (1 << 23)
629#define RS600_MC_DATA 0x74
630
631#define RS600_MC_STATUS 0x0
632# define RS600_MC_IDLE (1 << 1)
633#define RS600_MC_FB_LOCATION 0x4
634#define RS600_MC_AGP_LOCATION 0x5
635#define RS600_AGP_BASE 0x6
636#define RS600_AGP_BASE_2 0x7
637#define RS600_MC_CNTL1 0x9
638# define RS600_ENABLE_PAGE_TABLES (1 << 26)
639#define RS600_MC_PT0_CNTL 0x100
640# define RS600_ENABLE_PT (1 << 0)
641# define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15)
642# define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21)
643# define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28)
644# define RS600_INVALIDATE_L2_CACHE (1 << 29)
645#define RS600_MC_PT0_CONTEXT0_CNTL 0x102
646# define RS600_ENABLE_PAGE_TABLE (1 << 0)
647# define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1)
648#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112
649#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114
650#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c
651#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c
652#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c
653#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c
654#define RS600_MC_PT0_CLIENT0_CNTL 0x16c
655# define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0)
656# define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1)
657# define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8)
658# define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8)
659# define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8)
660# define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8)
661# define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8)
662# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10)
663# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10)
664# define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11)
665# define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14)
666# define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
667# define RS600_INVALIDATE_L1_TLB (1 << 20)
668
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]669#define R520_MC_IND_INDEX 0x70
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]670#define R520_MC_IND_WR_EN (1 << 24)
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]671#define R520_MC_IND_DATA 0x74
672
673#define RV515_MC_FB_LOCATION 0x01
674#define RV515_MC_AGP_LOCATION 0x02
Dave Airlie70b13d52008-06-19 11:40:44 +1000[diff] [blame]675#define RV515_MC_AGP_BASE 0x03
676#define RV515_MC_AGP_BASE_2 0x04
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]677
678#define R520_MC_FB_LOCATION 0x04
679#define R520_MC_AGP_LOCATION 0x05
Dave Airlie70b13d52008-06-19 11:40:44 +1000[diff] [blame]680#define R520_MC_AGP_BASE 0x06
681#define R520_MC_AGP_BASE_2 0x07
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]682
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]683#define RADEON_MPP_TB_CONFIG 0x01c0
684#define RADEON_MEM_CNTL 0x0140
685#define RADEON_MEM_SDRAM_MODE_REG 0x0158
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]686#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
687#define RS480_AGP_BASE_2 0x0164
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]688#define RADEON_AGP_BASE 0x0170
689
Alex Deucher5b92c402008-05-28 11:57:40 +1000[diff] [blame]690/* pipe config regs */
691#define R400_GB_PIPE_SELECT 0x402c
692#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
Alex Deucher5b92c402008-05-28 11:57:40 +1000[diff] [blame]693#define R300_GB_TILE_CONFIG 0x4018
694# define R300_ENABLE_TILING (1 << 0)
695# define R300_PIPE_COUNT_RV350 (0 << 1)
696# define R300_PIPE_COUNT_R300 (3 << 1)
697# define R300_PIPE_COUNT_R420_3P (6 << 1)
698# define R300_PIPE_COUNT_R420 (7 << 1)
699# define R300_TILE_SIZE_8 (0 << 4)
700# define R300_TILE_SIZE_16 (1 << 4)
701# define R300_TILE_SIZE_32 (2 << 4)
702# define R300_SUBPIXEL_1_12 (0 << 16)
703# define R300_SUBPIXEL_1_16 (1 << 16)
704#define R300_DST_PIPE_CONFIG 0x170c
705# define R300_PIPE_AUTO_CONFIG (1 << 31)
706#define R300_RB2D_DSTCACHE_MODE 0x3428
707# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
708# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
709
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]710#define RADEON_RB3D_COLOROFFSET 0x1c40
711#define RADEON_RB3D_COLORPITCH 0x1c48
712
Michel Daenzer3e14a282006-09-22 04:26:35 +1000[diff] [blame]713#define RADEON_SRC_X_Y 0x1590
714
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]715#define RADEON_DP_GUI_MASTER_CNTL 0x146c
716# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
717# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
718# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
719# define RADEON_GMC_BRUSH_NONE (15 << 4)
720# define RADEON_GMC_DST_16BPP (4 << 8)
721# define RADEON_GMC_DST_24BPP (5 << 8)
722# define RADEON_GMC_DST_32BPP (6 << 8)
723# define RADEON_GMC_DST_DATATYPE_SHIFT 8
724# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
725# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
726# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
727# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
728# define RADEON_GMC_WR_MSK_DIS (1 << 30)
729# define RADEON_ROP3_S 0x00cc0000
730# define RADEON_ROP3_P 0x00f00000
731#define RADEON_DP_WRITE_MASK 0x16cc
Michel Daenzer3e14a282006-09-22 04:26:35 +1000[diff] [blame]732#define RADEON_SRC_PITCH_OFFSET 0x1428
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]733#define RADEON_DST_PITCH_OFFSET 0x142c
734#define RADEON_DST_PITCH_OFFSET_C 0x1c80
735# define RADEON_DST_TILE_LINEAR (0 << 30)
736# define RADEON_DST_TILE_MACRO (1 << 30)
737# define RADEON_DST_TILE_MICRO (2 << 30)
738# define RADEON_DST_TILE_BOTH (3 << 30)
739
740#define RADEON_SCRATCH_REG0 0x15e0
741#define RADEON_SCRATCH_REG1 0x15e4
742#define RADEON_SCRATCH_REG2 0x15e8
743#define RADEON_SCRATCH_REG3 0x15ec
744#define RADEON_SCRATCH_REG4 0x15f0
745#define RADEON_SCRATCH_REG5 0x15f4
746#define RADEON_SCRATCH_UMSK 0x0770
747#define RADEON_SCRATCH_ADDR 0x0774
748
749#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
750
David Millerb07fa022009-02-12 02:15:37 -0800[diff] [blame]751extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
752
753#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]754
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]755#define R600_SCRATCH_REG0 0x8500
756#define R600_SCRATCH_REG1 0x8504
757#define R600_SCRATCH_REG2 0x8508
758#define R600_SCRATCH_REG3 0x850c
759#define R600_SCRATCH_REG4 0x8510
760#define R600_SCRATCH_REG5 0x8514
761#define R600_SCRATCH_REG6 0x8518
762#define R600_SCRATCH_REG7 0x851c
763#define R600_SCRATCH_UMSK 0x8540
764#define R600_SCRATCH_ADDR 0x8544
765
766#define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x))
767
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]768#define RADEON_GEN_INT_CNTL 0x0040
769# define RADEON_CRTC_VBLANK_MASK (1 << 0)
Dave Airlieddbee332007-07-11 12:16:01 +1000[diff] [blame]770# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]771# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
772# define RADEON_SW_INT_ENABLE (1 << 25)
773
774#define RADEON_GEN_INT_STATUS 0x0044
775# define RADEON_CRTC_VBLANK_STAT (1 << 0)
Dave Airliebc5f4522007-11-05 12:50:58 +1000[diff] [blame]776# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
Dave Airlieddbee332007-07-11 12:16:01 +1000[diff] [blame]777# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
Dave Airliebc5f4522007-11-05 12:50:58 +1000[diff] [blame]778# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]779# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
780# define RADEON_SW_INT_TEST (1 << 25)
Dave Airliebc5f4522007-11-05 12:50:58 +1000[diff] [blame]781# define RADEON_SW_INT_TEST_ACK (1 << 25)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]782# define RADEON_SW_INT_FIRE (1 << 26)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]783# define R500_DISPLAY_INT_STATUS (1 << 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]784
785#define RADEON_HOST_PATH_CNTL 0x0130
786# define RADEON_HDP_SOFT_RESET (1 << 26)
787# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
788# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
789
790#define RADEON_ISYNC_CNTL 0x1724
791# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
792# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
793# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
794# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
795# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
796# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
797
798#define RADEON_RBBM_GUICNTL 0x172c
799# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
800# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
801# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
802# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
803
804#define RADEON_MC_AGP_LOCATION 0x014c
805#define RADEON_MC_FB_LOCATION 0x0148
806#define RADEON_MCLK_CNTL 0x0012
807# define RADEON_FORCEON_MCLKA (1 << 16)
808# define RADEON_FORCEON_MCLKB (1 << 17)
809# define RADEON_FORCEON_YCLKA (1 << 18)
810# define RADEON_FORCEON_YCLKB (1 << 19)
811# define RADEON_FORCEON_MC (1 << 20)
812# define RADEON_FORCEON_AIC (1 << 21)
813
814#define RADEON_PP_BORDER_COLOR_0 0x1d40
815#define RADEON_PP_BORDER_COLOR_1 0x1d44
816#define RADEON_PP_BORDER_COLOR_2 0x1d48
817#define RADEON_PP_CNTL 0x1c38
818# define RADEON_SCISSOR_ENABLE (1 << 1)
819#define RADEON_PP_LUM_MATRIX 0x1d00
820#define RADEON_PP_MISC 0x1c14
821#define RADEON_PP_ROT_MATRIX_0 0x1d58
822#define RADEON_PP_TXFILTER_0 0x1c54
823#define RADEON_PP_TXOFFSET_0 0x1c5c
824#define RADEON_PP_TXFILTER_1 0x1c6c
825#define RADEON_PP_TXFILTER_2 0x1c84
826
Alex Deucher5e35eff2008-06-19 12:39:23 +1000[diff] [blame]827#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
828#define R300_DSTCACHE_CTLSTAT 0x1714
829# define R300_RB2D_DC_FLUSH (3 << 0)
830# define R300_RB2D_DC_FREE (3 << 2)
831# define R300_RB2D_DC_FLUSH_ALL 0xf
832# define R300_RB2D_DC_BUSY (1 << 31)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]833#define RADEON_RB3D_CNTL 0x1c3c
834# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
835# define RADEON_PLANE_MASK_ENABLE (1 << 1)
836# define RADEON_DITHER_ENABLE (1 << 2)
837# define RADEON_ROUND_ENABLE (1 << 3)
838# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
839# define RADEON_DITHER_INIT (1 << 5)
840# define RADEON_ROP_ENABLE (1 << 6)
841# define RADEON_STENCIL_ENABLE (1 << 7)
842# define RADEON_Z_ENABLE (1 << 8)
843# define RADEON_ZBLOCK16 (1 << 15)
844#define RADEON_RB3D_DEPTHOFFSET 0x1c24
845#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
846#define RADEON_RB3D_DEPTHPITCH 0x1c28
847#define RADEON_RB3D_PLANEMASK 0x1d84
848#define RADEON_RB3D_STENCILREFMASK 0x1d7c
849#define RADEON_RB3D_ZCACHE_MODE 0x3250
850#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
851# define RADEON_RB3D_ZC_FLUSH (1 << 0)
852# define RADEON_RB3D_ZC_FREE (1 << 2)
853# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
854# define RADEON_RB3D_ZC_BUSY (1 << 31)
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]855#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
856# define R300_ZC_FLUSH (1 << 0)
857# define R300_ZC_FREE (1 << 1)
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]858# define R300_ZC_BUSY (1 << 31)
Michel Dänzerb9b603d2006-08-07 20:41:53 +1000[diff] [blame]859#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
860# define RADEON_RB3D_DC_FLUSH (3 << 0)
861# define RADEON_RB3D_DC_FREE (3 << 2)
862# define RADEON_RB3D_DC_FLUSH_ALL 0xf
863# define RADEON_RB3D_DC_BUSY (1 << 31)
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]864#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]865# define R300_RB3D_DC_FLUSH (2 << 0)
866# define R300_RB3D_DC_FREE (2 << 2)
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]867# define R300_RB3D_DC_FINISH (1 << 4)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]868#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
869# define RADEON_Z_TEST_MASK (7 << 4)
870# define RADEON_Z_TEST_ALWAYS (7 << 4)
871# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
872# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
873# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
874# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
875# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
876# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
877# define RADEON_FORCE_Z_DIRTY (1 << 29)
878# define RADEON_Z_WRITE_ENABLE (1 << 30)
879# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
880#define RADEON_RBBM_SOFT_RESET 0x00f0
881# define RADEON_SOFT_RESET_CP (1 << 0)
882# define RADEON_SOFT_RESET_HI (1 << 1)
883# define RADEON_SOFT_RESET_SE (1 << 2)
884# define RADEON_SOFT_RESET_RE (1 << 3)
885# define RADEON_SOFT_RESET_PP (1 << 4)
886# define RADEON_SOFT_RESET_E2 (1 << 5)
887# define RADEON_SOFT_RESET_RB (1 << 6)
888# define RADEON_SOFT_RESET_HDP (1 << 7)
Roland Scheidegger576cc452008-02-07 14:59:24 +1000[diff] [blame]889/*
890 * 6:0 Available slots in the FIFO
891 * 8 Host Interface active
892 * 9 CP request active
893 * 10 FIFO request active
894 * 11 Host Interface retry active
895 * 12 CP retry active
896 * 13 FIFO retry active
897 * 14 FIFO pipeline busy
898 * 15 Event engine busy
899 * 16 CP command stream busy
900 * 17 2D engine busy
901 * 18 2D portion of render backend busy
902 * 20 3D setup engine busy
903 * 26 GA engine busy
904 * 27 CBA 2D engine busy
905 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
906 * command stream queue not empty or Ring Buffer not empty
907 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]908#define RADEON_RBBM_STATUS 0x0e40
Roland Scheidegger576cc452008-02-07 14:59:24 +1000[diff] [blame]909/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
910/* #define RADEON_RBBM_STATUS 0x1740 */
911/* bits 6:0 are dword slots available in the cmd fifo */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]912# define RADEON_RBBM_FIFOCNT_MASK 0x007f
Roland Scheidegger576cc452008-02-07 14:59:24 +1000[diff] [blame]913# define RADEON_HIRQ_ON_RBB (1 << 8)
914# define RADEON_CPRQ_ON_RBB (1 << 9)
915# define RADEON_CFRQ_ON_RBB (1 << 10)
916# define RADEON_HIRQ_IN_RTBUF (1 << 11)
917# define RADEON_CPRQ_IN_RTBUF (1 << 12)
918# define RADEON_CFRQ_IN_RTBUF (1 << 13)
919# define RADEON_PIPE_BUSY (1 << 14)
920# define RADEON_ENG_EV_BUSY (1 << 15)
921# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
922# define RADEON_E2_BUSY (1 << 17)
923# define RADEON_RB2D_BUSY (1 << 18)
924# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
925# define RADEON_VAP_BUSY (1 << 20)
926# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
927# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
928# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
929# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
930# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
931# define RADEON_GA_BUSY (1 << 26)
932# define RADEON_CBA2D_BUSY (1 << 27)
933# define RADEON_RBBM_ACTIVE (1 << 31)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]934#define RADEON_RE_LINE_PATTERN 0x1cd0
935#define RADEON_RE_MISC 0x26c4
936#define RADEON_RE_TOP_LEFT 0x26c0
937#define RADEON_RE_WIDTH_HEIGHT 0x1c44
938#define RADEON_RE_STIPPLE_ADDR 0x1cc8
939#define RADEON_RE_STIPPLE_DATA 0x1ccc
940
941#define RADEON_SCISSOR_TL_0 0x1cd8
942#define RADEON_SCISSOR_BR_0 0x1cdc
943#define RADEON_SCISSOR_TL_1 0x1ce0
944#define RADEON_SCISSOR_BR_1 0x1ce4
945#define RADEON_SCISSOR_TL_2 0x1ce8
946#define RADEON_SCISSOR_BR_2 0x1cec
947#define RADEON_SE_COORD_FMT 0x1c50
948#define RADEON_SE_CNTL 0x1c4c
949# define RADEON_FFACE_CULL_CW (0 << 0)
950# define RADEON_BFACE_SOLID (3 << 1)
951# define RADEON_FFACE_SOLID (3 << 3)
952# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
953# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
954# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
955# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
956# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
957# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
958# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
959# define RADEON_FOG_SHADE_FLAT (1 << 14)
960# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
961# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
962# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
963# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
964# define RADEON_ROUND_MODE_TRUNC (0 << 28)
965# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
966#define RADEON_SE_CNTL_STATUS 0x2140
967#define RADEON_SE_LINE_WIDTH 0x1db8
968#define RADEON_SE_VPORT_XSCALE 0x1d98
969#define RADEON_SE_ZBIAS_FACTOR 0x1db0
970#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
971#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
972#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
973# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
974# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
975#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
976#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
977# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
978#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
979#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
980#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
981#define RADEON_SURFACE_CNTL 0x0b00
982# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
983# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
984# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
985# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
986# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
987# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
988# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
989# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
990# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
991#define RADEON_SURFACE0_INFO 0x0b0c
992# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
993# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
994# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
995# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
996# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
997# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
998#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
999#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
1000# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
1001#define RADEON_SURFACE1_INFO 0x0b1c
1002#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
1003#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
1004#define RADEON_SURFACE2_INFO 0x0b2c
1005#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
1006#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
1007#define RADEON_SURFACE3_INFO 0x0b3c
1008#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
1009#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
1010#define RADEON_SURFACE4_INFO 0x0b4c
1011#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
1012#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
1013#define RADEON_SURFACE5_INFO 0x0b5c
1014#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
1015#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
1016#define RADEON_SURFACE6_INFO 0x0b6c
1017#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
1018#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
1019#define RADEON_SURFACE7_INFO 0x0b7c
1020#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
1021#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
1022#define RADEON_SW_SEMAPHORE 0x013c
1023
1024#define RADEON_WAIT_UNTIL 0x1720
1025# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
Dave Airlied985c102006-01-02 21:32:48 +1100[diff] [blame]1026# define RADEON_WAIT_2D_IDLE (1 << 14)
1027# define RADEON_WAIT_3D_IDLE (1 << 15)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1028# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
1029# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
1030# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
1031
1032#define RADEON_RB3D_ZMASKOFFSET 0x3234
1033#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
1034# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
1035# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
1036
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1037/* CP registers */
1038#define RADEON_CP_ME_RAM_ADDR 0x07d4
1039#define RADEON_CP_ME_RAM_RADDR 0x07d8
1040#define RADEON_CP_ME_RAM_DATAH 0x07dc
1041#define RADEON_CP_ME_RAM_DATAL 0x07e0
1042
1043#define RADEON_CP_RB_BASE 0x0700
1044#define RADEON_CP_RB_CNTL 0x0704
1045# define RADEON_BUF_SWAP_32BIT (2 << 16)
Michel Dänzerae1b1a482006-08-07 20:37:46 +1000[diff] [blame]1046# define RADEON_RB_NO_UPDATE (1 << 27)
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]1047# define RADEON_RB_RPTR_WR_ENA (1 << 31)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1048#define RADEON_CP_RB_RPTR_ADDR 0x070c
1049#define RADEON_CP_RB_RPTR 0x0710
1050#define RADEON_CP_RB_WPTR 0x0714
1051
1052#define RADEON_CP_RB_WPTR_DELAY 0x0718
1053# define RADEON_PRE_WRITE_TIMER_SHIFT 0
1054# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
1055
1056#define RADEON_CP_IB_BASE 0x0738
1057
1058#define RADEON_CP_CSQ_CNTL 0x0740
1059# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
1060# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
1061# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
1062# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
1063# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
1064# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
1065# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
1066
1067#define RADEON_AIC_CNTL 0x01d0
1068# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
Alex Deucher4e270e92008-10-28 07:48:34 +1000[diff] [blame]1069# define RS400_MSI_REARM (1 << 3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1070#define RADEON_AIC_STAT 0x01d4
1071#define RADEON_AIC_PT_BASE 0x01d8
1072#define RADEON_AIC_LO_ADDR 0x01dc
1073#define RADEON_AIC_HI_ADDR 0x01e0
1074#define RADEON_AIC_TLB_ADDR 0x01e4
1075#define RADEON_AIC_TLB_DATA 0x01e8
1076
1077/* CP command packets */
1078#define RADEON_CP_PACKET0 0x00000000
1079# define RADEON_ONE_REG_WR (1 << 15)
1080#define RADEON_CP_PACKET1 0x40000000
1081#define RADEON_CP_PACKET2 0x80000000
1082#define RADEON_CP_PACKET3 0xC0000000
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]1083# define RADEON_CP_NOP 0x00001000
1084# define RADEON_CP_NEXT_CHAR 0x00001900
1085# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
1086# define RADEON_CP_SET_SCISSORS 0x00001E00
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1087 /* GEN_INDX_PRIM is unsupported starting with R300 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1088# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
1089# define RADEON_WAIT_FOR_IDLE 0x00002600
1090# define RADEON_3D_DRAW_VBUF 0x00002800
1091# define RADEON_3D_DRAW_IMMD 0x00002900
1092# define RADEON_3D_DRAW_INDX 0x00002A00
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]1093# define RADEON_CP_LOAD_PALETTE 0x00002C00
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1094# define RADEON_3D_LOAD_VBPNTR 0x00002F00
1095# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
1096# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
1097# define RADEON_3D_CLEAR_ZMASK 0x00003200
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]1098# define RADEON_CP_INDX_BUFFER 0x00003300
1099# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
1100# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
1101# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1102# define RADEON_3D_CLEAR_HIZ 0x00003700
Dave Airlie414ed532005-08-16 20:43:16 +1000[diff] [blame]1103# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1104# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
1105# define RADEON_CNTL_PAINT_MULTI 0x00009A00
1106# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
1107# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
1108
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]1109# define R600_IT_INDIRECT_BUFFER 0x00003200
1110# define R600_IT_ME_INITIALIZE 0x00004400
1111# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1112# define R600_IT_EVENT_WRITE 0x00004600
1113# define R600_IT_SET_CONFIG_REG 0x00006800
1114# define R600_SET_CONFIG_REG_OFFSET 0x00008000
1115# define R600_SET_CONFIG_REG_END 0x0000ac00
1116
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1117#define RADEON_CP_PACKET_MASK 0xC0000000
1118#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
1119#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
1120#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
1121#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
1122
1123#define RADEON_VTX_Z_PRESENT (1 << 31)
1124#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
1125
1126#define RADEON_PRIM_TYPE_NONE (0 << 0)
1127#define RADEON_PRIM_TYPE_POINT (1 << 0)
1128#define RADEON_PRIM_TYPE_LINE (2 << 0)
1129#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
1130#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
1131#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
1132#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
1133#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1134#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
1135#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1136#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1137#define RADEON_PRIM_TYPE_MASK 0xf
1138#define RADEON_PRIM_WALK_IND (1 << 4)
1139#define RADEON_PRIM_WALK_LIST (2 << 4)
1140#define RADEON_PRIM_WALK_RING (3 << 4)
1141#define RADEON_COLOR_ORDER_BGRA (0 << 6)
1142#define RADEON_COLOR_ORDER_RGBA (1 << 6)
1143#define RADEON_MAOS_ENABLE (1 << 7)
1144#define RADEON_VTX_FMT_R128_MODE (0 << 8)
1145#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
1146#define RADEON_NUM_VERTICES_SHIFT 16
1147
1148#define RADEON_COLOR_FORMAT_CI8 2
1149#define RADEON_COLOR_FORMAT_ARGB1555 3
1150#define RADEON_COLOR_FORMAT_RGB565 4
1151#define RADEON_COLOR_FORMAT_ARGB8888 6
1152#define RADEON_COLOR_FORMAT_RGB332 7
1153#define RADEON_COLOR_FORMAT_RGB8 9
1154#define RADEON_COLOR_FORMAT_ARGB4444 15
1155
1156#define RADEON_TXFORMAT_I8 0
1157#define RADEON_TXFORMAT_AI88 1
1158#define RADEON_TXFORMAT_RGB332 2
1159#define RADEON_TXFORMAT_ARGB1555 3
1160#define RADEON_TXFORMAT_RGB565 4
1161#define RADEON_TXFORMAT_ARGB4444 5
1162#define RADEON_TXFORMAT_ARGB8888 6
1163#define RADEON_TXFORMAT_RGBA8888 7
1164#define RADEON_TXFORMAT_Y8 8
1165#define RADEON_TXFORMAT_VYUY422 10
1166#define RADEON_TXFORMAT_YVYU422 11
1167#define RADEON_TXFORMAT_DXT1 12
1168#define RADEON_TXFORMAT_DXT23 14
1169#define RADEON_TXFORMAT_DXT45 15
1170
1171#define R200_PP_TXCBLEND_0 0x2f00
1172#define R200_PP_TXCBLEND_1 0x2f10
1173#define R200_PP_TXCBLEND_2 0x2f20
1174#define R200_PP_TXCBLEND_3 0x2f30
1175#define R200_PP_TXCBLEND_4 0x2f40
1176#define R200_PP_TXCBLEND_5 0x2f50
1177#define R200_PP_TXCBLEND_6 0x2f60
1178#define R200_PP_TXCBLEND_7 0x2f70
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1179#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1180#define R200_PP_TFACTOR_0 0x2ee0
1181#define R200_SE_VTX_FMT_0 0x2088
1182#define R200_SE_VAP_CNTL 0x2080
1183#define R200_SE_TCL_MATRIX_SEL_0 0x2230
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1184#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1185#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1186#define R200_PP_TXFILTER_5 0x2ca0
1187#define R200_PP_TXFILTER_4 0x2c80
1188#define R200_PP_TXFILTER_3 0x2c60
1189#define R200_PP_TXFILTER_2 0x2c40
1190#define R200_PP_TXFILTER_1 0x2c20
1191#define R200_PP_TXFILTER_0 0x2c00
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1192#define R200_PP_TXOFFSET_5 0x2d78
1193#define R200_PP_TXOFFSET_4 0x2d60
1194#define R200_PP_TXOFFSET_3 0x2d48
1195#define R200_PP_TXOFFSET_2 0x2d30
1196#define R200_PP_TXOFFSET_1 0x2d18
1197#define R200_PP_TXOFFSET_0 0x2d00
1198
1199#define R200_PP_CUBIC_FACES_0 0x2c18
1200#define R200_PP_CUBIC_FACES_1 0x2c38
1201#define R200_PP_CUBIC_FACES_2 0x2c58
1202#define R200_PP_CUBIC_FACES_3 0x2c78
1203#define R200_PP_CUBIC_FACES_4 0x2c98
1204#define R200_PP_CUBIC_FACES_5 0x2cb8
1205#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1206#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1207#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1208#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1209#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1210#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1211#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1212#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1213#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1214#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1215#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1216#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1217#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1218#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1219#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1220#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1221#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1222#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1223#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1224#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1225#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1226#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1227#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1228#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1229#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1230#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1231#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1232#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1233#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1234#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1235
1236#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1237#define R200_SE_VTE_CNTL 0x20b0
1238#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1239#define R200_PP_TAM_DEBUG3 0x2d9c
1240#define R200_PP_CNTL_X 0x2cc4
1241#define R200_SE_VAP_CNTL_STATUS 0x2140
1242#define R200_RE_SCISSOR_TL_0 0x1cd8
1243#define R200_RE_SCISSOR_TL_1 0x1ce0
1244#define R200_RE_SCISSOR_TL_2 0x1ce8
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1245#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1246#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1247#define R200_SE_VTX_STATE_CNTL 0x2180
1248#define R200_RE_POINTSIZE 0x2648
1249#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1250
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1251#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1252#define RADEON_PP_TEX_SIZE_1 0x1d0c
1253#define RADEON_PP_TEX_SIZE_2 0x1d14
1254
1255#define RADEON_PP_CUBIC_FACES_0 0x1d24
1256#define RADEON_PP_CUBIC_FACES_1 0x1d28
1257#define RADEON_PP_CUBIC_FACES_2 0x1d2c
1258#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1259#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1260#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1261
Dave Airlief2a22792006-06-24 16:55:34 +1000[diff] [blame]1262#define RADEON_SE_TCL_STATE_FLUSH 0x2284
1263
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1264#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1265#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1266#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1267#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1268#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1269#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1270#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1271#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1272#define R200_3D_DRAW_IMMD_2 0xC0003500
1273#define R200_SE_VTX_FMT_1 0x208c
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1274#define R200_RE_CNTL 0x1c50
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1275
1276#define R200_RB3D_BLENDCOLOR 0x3218
1277
1278#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1279
1280#define R200_PP_TRI_PERF 0x2cf8
1281
Dave Airlie9d176012005-09-11 19:55:53 +1000[diff] [blame]1282#define R200_PP_AFS_0 0x2f80
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1283#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
Dave Airlie9d176012005-09-11 19:55:53 +1000[diff] [blame]1284
Dave Airlied6fece02006-06-24 17:04:07 +1000[diff] [blame]1285#define R200_VAP_PVS_CNTL_1 0x22D0
1286
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700[diff] [blame]1287#define RADEON_CRTC_CRNT_FRAME 0x0214
1288#define RADEON_CRTC2_CRNT_FRAME 0x0314
1289
Dave Airliec0beb2a2008-05-28 13:52:28 +1000[diff] [blame]1290#define R500_D1CRTC_STATUS 0x609c
1291#define R500_D2CRTC_STATUS 0x689c
1292#define R500_CRTC_V_BLANK (1<<0)
1293
1294#define R500_D1CRTC_FRAME_COUNT 0x60a4
1295#define R500_D2CRTC_FRAME_COUNT 0x68a4
1296
1297#define R500_D1MODE_V_COUNTER 0x6530
1298#define R500_D2MODE_V_COUNTER 0x6d30
1299
1300#define R500_D1MODE_VBLANK_STATUS 0x6534
1301#define R500_D2MODE_VBLANK_STATUS 0x6d34
1302#define R500_VBLANK_OCCURED (1<<0)
1303#define R500_VBLANK_ACK (1<<4)
1304#define R500_VBLANK_STAT (1<<12)
1305#define R500_VBLANK_INT (1<<16)
1306
1307#define R500_DxMODE_INT_MASK 0x6540
1308#define R500_D1MODE_INT_MASK (1<<0)
1309#define R500_D2MODE_INT_MASK (1<<8)
1310
1311#define R500_DISP_INTERRUPT_STATUS 0x7edc
1312#define R500_D1_VBLANK_INTERRUPT (1 << 4)
1313#define R500_D2_VBLANK_INTERRUPT (1 << 5)
1314
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]1315/* R6xx/R7xx registers */
1316#define R600_MC_VM_FB_LOCATION 0x2180
1317#define R600_MC_VM_AGP_TOP 0x2184
1318#define R600_MC_VM_AGP_BOT 0x2188
1319#define R600_MC_VM_AGP_BASE 0x218c
1320#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
1321#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
1322#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
1323
1324#define R700_MC_VM_FB_LOCATION 0x2024
1325#define R700_MC_VM_AGP_TOP 0x2028
1326#define R700_MC_VM_AGP_BOT 0x202c
1327#define R700_MC_VM_AGP_BASE 0x2030
1328#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
1329#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
1330#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
1331
1332#define R600_MCD_RD_A_CNTL 0x219c
1333#define R600_MCD_RD_B_CNTL 0x21a0
1334
1335#define R600_MCD_WR_A_CNTL 0x21a4
1336#define R600_MCD_WR_B_CNTL 0x21a8
1337
1338#define R600_MCD_RD_SYS_CNTL 0x2200
1339#define R600_MCD_WR_SYS_CNTL 0x2214
1340
1341#define R600_MCD_RD_GFX_CNTL 0x21fc
1342#define R600_MCD_RD_HDP_CNTL 0x2204
1343#define R600_MCD_RD_PDMA_CNTL 0x2208
1344#define R600_MCD_RD_SEM_CNTL 0x220c
1345#define R600_MCD_WR_GFX_CNTL 0x2210
1346#define R600_MCD_WR_HDP_CNTL 0x2218
1347#define R600_MCD_WR_PDMA_CNTL 0x221c
1348#define R600_MCD_WR_SEM_CNTL 0x2220
1349
1350# define R600_MCD_L1_TLB (1 << 0)
1351# define R600_MCD_L1_FRAG_PROC (1 << 1)
1352# define R600_MCD_L1_STRICT_ORDERING (1 << 2)
1353
1354# define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6)
1355# define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
1356# define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
1357# define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
1358# define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
1359
1360# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
1361# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
1362
1363# define R600_MCD_SEMAPHORE_MODE (1 << 10)
1364# define R600_MCD_WAIT_L2_QUERY (1 << 11)
1365# define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12)
1366# define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
1367
1368#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654
1369#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658
1370#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c
1371
1372#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
1373#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
1374#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c
1375#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
1376
1377# define R700_ENABLE_L1_TLB (1 << 0)
1378# define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
1379# define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
1380# define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
1381# define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15)
1382# define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18)
1383
1384#define R700_MC_ARB_RAMCFG 0x2760
1385# define R700_NOOFBANK_SHIFT 0
1386# define R700_NOOFBANK_MASK 0x3
1387# define R700_NOOFRANK_SHIFT 2
1388# define R700_NOOFRANK_MASK 0x1
1389# define R700_NOOFROWS_SHIFT 3
1390# define R700_NOOFROWS_MASK 0x7
1391# define R700_NOOFCOLS_SHIFT 6
1392# define R700_NOOFCOLS_MASK 0x3
1393# define R700_CHANSIZE_SHIFT 8
1394# define R700_CHANSIZE_MASK 0x1
1395# define R700_BURSTLENGTH_SHIFT 9
1396# define R700_BURSTLENGTH_MASK 0x1
1397#define R600_RAMCFG 0x2408
1398# define R600_NOOFBANK_SHIFT 0
1399# define R600_NOOFBANK_MASK 0x1
1400# define R600_NOOFRANK_SHIFT 1
1401# define R600_NOOFRANK_MASK 0x1
1402# define R600_NOOFROWS_SHIFT 2
1403# define R600_NOOFROWS_MASK 0x7
1404# define R600_NOOFCOLS_SHIFT 5
1405# define R600_NOOFCOLS_MASK 0x3
1406# define R600_CHANSIZE_SHIFT 7
1407# define R600_CHANSIZE_MASK 0x1
1408# define R600_BURSTLENGTH_SHIFT 8
1409# define R600_BURSTLENGTH_MASK 0x1
1410
1411#define R600_VM_L2_CNTL 0x1400
1412# define R600_VM_L2_CACHE_EN (1 << 0)
1413# define R600_VM_L2_FRAG_PROC (1 << 1)
1414# define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9)
1415# define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13)
1416# define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14)
1417
1418#define R600_VM_L2_CNTL2 0x1404
1419# define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0)
1420# define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1)
1421#define R600_VM_L2_CNTL3 0x1408
1422# define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0)
1423# define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5)
1424# define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10)
1425# define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0)
1426# define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6)
1427
1428#define R600_VM_L2_STATUS 0x140c
1429
1430#define R600_VM_CONTEXT0_CNTL 0x1410
1431# define R600_VM_ENABLE_CONTEXT (1 << 0)
1432# define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1)
1433
1434#define R600_VM_CONTEXT0_CNTL2 0x1430
1435#define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470
1436#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
1437#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0
1438#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
1439#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
1440#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4
1441
1442#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
1443#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
1444#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c
1445
1446#define R600_HDP_HOST_PATH_CNTL 0x2c00
1447
1448#define R600_GRBM_CNTL 0x8000
1449# define R600_GRBM_READ_TIMEOUT(x) ((x) << 0)
1450
1451#define R600_GRBM_STATUS 0x8010
1452# define R600_CMDFIFO_AVAIL_MASK 0x1f
1453# define R700_CMDFIFO_AVAIL_MASK 0xf
1454# define R600_GUI_ACTIVE (1 << 31)
1455#define R600_GRBM_STATUS2 0x8014
1456#define R600_GRBM_SOFT_RESET 0x8020
1457# define R600_SOFT_RESET_CP (1 << 0)
1458#define R600_WAIT_UNTIL 0x8040
1459
1460#define R600_CP_SEM_WAIT_TIMER 0x85bc
1461#define R600_CP_ME_CNTL 0x86d8
1462# define R600_CP_ME_HALT (1 << 28)
1463#define R600_CP_QUEUE_THRESHOLDS 0x8760
1464# define R600_ROQ_IB1_START(x) ((x) << 0)
1465# define R600_ROQ_IB2_START(x) ((x) << 8)
1466#define R600_CP_MEQ_THRESHOLDS 0x8764
1467# define R700_STQ_SPLIT(x) ((x) << 0)
1468# define R600_MEQ_END(x) ((x) << 16)
1469# define R600_ROQ_END(x) ((x) << 24)
1470#define R600_CP_PERFMON_CNTL 0x87fc
1471#define R600_CP_RB_BASE 0xc100
1472#define R600_CP_RB_CNTL 0xc104
1473# define R600_RB_BUFSZ(x) ((x) << 0)
1474# define R600_RB_BLKSZ(x) ((x) << 8)
1475# define R600_RB_NO_UPDATE (1 << 27)
1476# define R600_RB_RPTR_WR_ENA (1 << 31)
1477#define R600_CP_RB_RPTR_WR 0xc108
1478#define R600_CP_RB_RPTR_ADDR 0xc10c
1479#define R600_CP_RB_RPTR_ADDR_HI 0xc110
1480#define R600_CP_RB_WPTR 0xc114
1481#define R600_CP_RB_WPTR_ADDR 0xc118
1482#define R600_CP_RB_WPTR_ADDR_HI 0xc11c
1483#define R600_CP_RB_RPTR 0x8700
1484#define R600_CP_RB_WPTR_DELAY 0x8704
1485#define R600_CP_PFP_UCODE_ADDR 0xc150
1486#define R600_CP_PFP_UCODE_DATA 0xc154
1487#define R600_CP_ME_RAM_RADDR 0xc158
1488#define R600_CP_ME_RAM_WADDR 0xc15c
1489#define R600_CP_ME_RAM_DATA 0xc160
1490#define R600_CP_DEBUG 0xc1fc
1491
1492#define R600_PA_CL_ENHANCE 0x8a14
1493# define R600_CLIP_VTX_REORDER_ENA (1 << 0)
1494# define R600_NUM_CLIP_SEQ(x) ((x) << 1)
1495#define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10
1496#define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20
1497#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24
1498# define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1499# define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1500#define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40
1501#define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44
1502#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48
1503#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c
1504# define R600_S0_X(x) ((x) << 0)
1505# define R600_S0_Y(x) ((x) << 4)
1506# define R600_S1_X(x) ((x) << 8)
1507# define R600_S1_Y(x) ((x) << 12)
1508# define R600_S2_X(x) ((x) << 16)
1509# define R600_S2_Y(x) ((x) << 20)
1510# define R600_S3_X(x) ((x) << 24)
1511# define R600_S3_Y(x) ((x) << 28)
1512# define R600_S4_X(x) ((x) << 0)
1513# define R600_S4_Y(x) ((x) << 4)
1514# define R600_S5_X(x) ((x) << 8)
1515# define R600_S5_Y(x) ((x) << 12)
1516# define R600_S6_X(x) ((x) << 16)
1517# define R600_S6_Y(x) ((x) << 20)
1518# define R600_S7_X(x) ((x) << 24)
1519# define R600_S7_Y(x) ((x) << 28)
1520#define R600_PA_SC_FIFO_SIZE 0x8bd0
1521# define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1522# define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8)
1523# define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16)
1524#define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc
1525# define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1526# define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
1527# define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
1528#define R600_PA_SC_ENHANCE 0x8bf0
1529# define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1530# define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
1531#define R600_PA_SC_CLIPRECT_RULE 0x2820c
1532#define R700_PA_SC_EDGERULE 0x28230
1533#define R600_PA_SC_LINE_STIPPLE 0x28a0c
1534#define R600_PA_SC_MODE_CNTL 0x28a4c
1535#define R600_PA_SC_AA_CONFIG 0x28c04
1536
1537#define R600_SX_EXPORT_BUFFER_SIZES 0x900c
1538# define R600_COLOR_BUFFER_SIZE(x) ((x) << 0)
1539# define R600_POSITION_BUFFER_SIZE(x) ((x) << 8)
1540# define R600_SMX_BUFFER_SIZE(x) ((x) << 16)
1541#define R600_SX_DEBUG_1 0x9054
1542# define R600_SMX_EVENT_RELEASE (1 << 0)
1543# define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1544#define R700_SX_DEBUG_1 0x9058
1545# define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1546#define R600_SX_MISC 0x28350
1547
1548#define R600_DB_DEBUG 0x9830
1549# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
1550#define R600_DB_WATERMARKS 0x9838
1551# define R600_DEPTH_FREE(x) ((x) << 0)
1552# define R600_DEPTH_FLUSH(x) ((x) << 5)
1553# define R600_DEPTH_PENDING_FREE(x) ((x) << 15)
1554# define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20)
1555#define R700_DB_DEBUG3 0x98b0
1556# define R700_DB_CLK_OFF_DELAY(x) ((x) << 11)
1557#define RV700_DB_DEBUG4 0x9b8c
1558# define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
1559
1560#define R600_VGT_CACHE_INVALIDATION 0x88c4
1561# define R600_CACHE_INVALIDATION(x) ((x) << 0)
1562# define R600_VC_ONLY 0
1563# define R600_TC_ONLY 1
1564# define R600_VC_AND_TC 2
1565# define R700_AUTO_INVLD_EN(x) ((x) << 6)
1566# define R700_NO_AUTO 0
1567# define R700_ES_AUTO 1
1568# define R700_GS_AUTO 2
1569# define R700_ES_AND_GS_AUTO 3
1570#define R600_VGT_GS_PER_ES 0x88c8
1571#define R600_VGT_ES_PER_GS 0x88cc
1572#define R600_VGT_GS_PER_VS 0x88e8
1573#define R600_VGT_GS_VERTEX_REUSE 0x88d4
1574#define R600_VGT_NUM_INSTANCES 0x8974
1575#define R600_VGT_STRMOUT_EN 0x28ab0
1576#define R600_VGT_EVENT_INITIATOR 0x28a90
1577# define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
1578#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58
1579# define R600_VTX_REUSE_DEPTH_MASK 0xff
1580#define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c
1581# define R600_DEALLOC_DIST_MASK 0x7f
1582
1583#define R600_CB_COLOR0_BASE 0x28040
1584#define R600_CB_COLOR1_BASE 0x28044
1585#define R600_CB_COLOR2_BASE 0x28048
1586#define R600_CB_COLOR3_BASE 0x2804c
1587#define R600_CB_COLOR4_BASE 0x28050
1588#define R600_CB_COLOR5_BASE 0x28054
1589#define R600_CB_COLOR6_BASE 0x28058
1590#define R600_CB_COLOR7_BASE 0x2805c
1591#define R600_CB_COLOR7_FRAG 0x280fc
1592
1593#define R600_TC_CNTL 0x9608
1594# define R600_TC_L2_SIZE(x) ((x) << 5)
1595# define R600_L2_DISABLE_LATE_HIT (1 << 9)
1596
1597#define R600_ARB_POP 0x2418
1598# define R600_ENABLE_TC128 (1 << 30)
1599#define R600_ARB_GDEC_RD_CNTL 0x246c
1600
1601#define R600_TA_CNTL_AUX 0x9508
1602# define R600_DISABLE_CUBE_WRAP (1 << 0)
1603# define R600_DISABLE_CUBE_ANISO (1 << 1)
1604# define R700_GETLOD_SELECT(x) ((x) << 2)
1605# define R600_SYNC_GRADIENT (1 << 24)
1606# define R600_SYNC_WALKER (1 << 25)
1607# define R600_SYNC_ALIGNER (1 << 26)
1608# define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
1609# define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
1610
1611#define R700_TCP_CNTL 0x9610
1612
1613#define R600_SMX_DC_CTL0 0xa020
1614# define R700_USE_HASH_FUNCTION (1 << 0)
1615# define R700_CACHE_DEPTH(x) ((x) << 1)
1616# define R700_FLUSH_ALL_ON_EVENT (1 << 10)
1617# define R700_STALL_ON_EVENT (1 << 11)
1618#define R700_SMX_EVENT_CTL 0xa02c
1619# define R700_ES_FLUSH_CTL(x) ((x) << 0)
1620# define R700_GS_FLUSH_CTL(x) ((x) << 3)
1621# define R700_ACK_FLUSH_CTL(x) ((x) << 6)
1622# define R700_SYNC_FLUSH_CTL (1 << 8)
1623
1624#define R600_SQ_CONFIG 0x8c00
1625# define R600_VC_ENABLE (1 << 0)
1626# define R600_EXPORT_SRC_C (1 << 1)
1627# define R600_DX9_CONSTS (1 << 2)
1628# define R600_ALU_INST_PREFER_VECTOR (1 << 3)
1629# define R600_DX10_CLAMP (1 << 4)
1630# define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8)
1631# define R600_PS_PRIO(x) ((x) << 24)
1632# define R600_VS_PRIO(x) ((x) << 26)
1633# define R600_GS_PRIO(x) ((x) << 28)
1634# define R600_ES_PRIO(x) ((x) << 30)
1635#define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04
1636# define R600_NUM_PS_GPRS(x) ((x) << 0)
1637# define R600_NUM_VS_GPRS(x) ((x) << 16)
1638# define R700_DYN_GPR_ENABLE (1 << 27)
1639# define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
1640#define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08
1641# define R600_NUM_GS_GPRS(x) ((x) << 0)
1642# define R600_NUM_ES_GPRS(x) ((x) << 16)
1643#define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c
1644# define R600_NUM_PS_THREADS(x) ((x) << 0)
1645# define R600_NUM_VS_THREADS(x) ((x) << 8)
1646# define R600_NUM_GS_THREADS(x) ((x) << 16)
1647# define R600_NUM_ES_THREADS(x) ((x) << 24)
1648#define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10
1649# define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0)
1650# define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16)
1651#define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14
1652# define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0)
1653# define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16)
1654#define R600_SQ_MS_FIFO_SIZES 0x8cf0
1655# define R600_CACHE_FIFO_SIZE(x) ((x) << 0)
1656# define R600_FETCH_FIFO_HIWATER(x) ((x) << 8)
1657# define R600_DONE_FIFO_HIWATER(x) ((x) << 16)
1658# define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
1659#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0
1660# define R700_SIMDA_RING0(x) ((x) << 0)
1661# define R700_SIMDA_RING1(x) ((x) << 8)
1662# define R700_SIMDB_RING0(x) ((x) << 16)
1663# define R700_SIMDB_RING1(x) ((x) << 24)
1664#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4
1665#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8
1666#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc
1667#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0
1668#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4
1669#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8
1670#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc
1671
1672#define R600_SPI_PS_IN_CONTROL_0 0x286cc
1673# define R600_NUM_INTERP(x) ((x) << 0)
1674# define R600_POSITION_ENA (1 << 8)
1675# define R600_POSITION_CENTROID (1 << 9)
1676# define R600_POSITION_ADDR(x) ((x) << 10)
1677# define R600_PARAM_GEN(x) ((x) << 15)
1678# define R600_PARAM_GEN_ADDR(x) ((x) << 19)
1679# define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26)
1680# define R600_PERSP_GRADIENT_ENA (1 << 28)
1681# define R600_LINEAR_GRADIENT_ENA (1 << 29)
1682# define R600_POSITION_SAMPLE (1 << 30)
1683# define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
1684#define R600_SPI_PS_IN_CONTROL_1 0x286d0
1685# define R600_GEN_INDEX_PIX (1 << 0)
1686# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)
1687# define R600_FRONT_FACE_ENA (1 << 8)
1688# define R600_FRONT_FACE_CHAN(x) ((x) << 9)
1689# define R600_FRONT_FACE_ALL_BITS (1 << 11)
1690# define R600_FRONT_FACE_ADDR(x) ((x) << 12)
1691# define R600_FOG_ADDR(x) ((x) << 17)
1692# define R600_FIXED_PT_POSITION_ENA (1 << 24)
1693# define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25)
1694# define R700_POSITION_ULC (1 << 30)
1695#define R600_SPI_INPUT_Z 0x286d8
1696
1697#define R600_SPI_CONFIG_CNTL 0x9100
1698# define R600_GPR_WRITE_PRIORITY(x) ((x) << 0)
1699# define R600_DISABLE_INTERP_1 (1 << 5)
1700#define R600_SPI_CONFIG_CNTL_1 0x913c
1701# define R600_VTX_DONE_DELAY(x) ((x) << 0)
1702# define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4)
1703
1704#define R600_GB_TILING_CONFIG 0x98f0
1705# define R600_PIPE_TILING(x) ((x) << 1)
1706# define R600_BANK_TILING(x) ((x) << 4)
1707# define R600_GROUP_SIZE(x) ((x) << 6)
1708# define R600_ROW_TILING(x) ((x) << 8)
1709# define R600_BANK_SWAPS(x) ((x) << 11)
1710# define R600_SAMPLE_SPLIT(x) ((x) << 14)
1711# define R600_BACKEND_MAP(x) ((x) << 16)
1712#define R600_DCP_TILING_CONFIG 0x6ca0
1713#define R600_HDP_TILING_CONFIG 0x2f3c
1714
1715#define R600_CC_RB_BACKEND_DISABLE 0x98f4
1716#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88
1717# define R600_BACKEND_DISABLE(x) ((x) << 16)
1718
1719#define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950
1720#define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954
1721# define R600_INACTIVE_QD_PIPES(x) ((x) << 8)
1722# define R600_INACTIVE_QD_PIPES_MASK (0xff << 8)
1723# define R600_INACTIVE_SIMDS(x) ((x) << 16)
1724# define R600_INACTIVE_SIMDS_MASK (0xff << 16)
1725
1726#define R700_CGTS_SYS_TCC_DISABLE 0x3f90
1727#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94
1728#define R700_CGTS_TCC_DISABLE 0x9148
1729#define R700_CGTS_USER_TCC_DISABLE 0x914c
1730
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1731/* Constants */
1732#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1733
1734#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1735#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1736#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1737#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1738#define RADEON_LAST_DISPATCH 1
1739
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]1740#define R600_LAST_FRAME_REG R600_SCRATCH_REG0
1741#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1
1742#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2
1743#define R600_LAST_SWI_REG R600_SCRATCH_REG3
1744
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1745#define RADEON_MAX_VB_AGE 0x7fffffff
1746#define RADEON_MAX_VB_VERTS (0xffff)
1747
1748#define RADEON_RING_HIGH_MARK 128
1749
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]1750#define RADEON_PCIGART_TABLE_SIZE (32*1024)
1751
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1752#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]1753#define RADEON_WRITE(reg, val) \
1754do { \
1755 if (reg < 0x10000) { \
1756 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1757 } else { \
1758 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1759 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1760 } \
1761} while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1762#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1763#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1764
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]1765#define RADEON_WRITE_PLL(addr, val) \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1766do { \
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]1767 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1768 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]1769 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1770} while (0)
1771
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]1772#define RADEON_WRITE_PCIE(addr, val) \
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]1773do { \
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]1774 RADEON_WRITE8(RADEON_PCIE_INDEX, \
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]1775 ((addr) & 0xff)); \
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]1776 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
Dave Airlieea98a922005-09-11 20:28:11 +1000[diff] [blame]1777} while (0)
1778
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]1779#define R500_WRITE_MCIND(addr, val) \
1780do { \
1781 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1782 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1783 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1784} while (0)
1785
1786#define RS480_WRITE_MCIND(addr, val) \
1787do { \
1788 RADEON_WRITE(RS480_NB_MC_INDEX, \
1789 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1790 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1791 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1792} while (0)
Dave Airlie3d5e2c12008-02-07 15:01:05 +1000[diff] [blame]1793
Alex Deucher27359772008-05-28 12:54:16 +1000[diff] [blame]1794#define RS690_WRITE_MCIND(addr, val) \
Maciej Cencora60f92682008-02-19 21:32:45 +1000[diff] [blame]1795do { \
1796 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1797 RADEON_WRITE(RS690_MC_DATA, val); \
1798 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1799} while (0)
1800
Alex Deucherc1556f72009-02-25 16:57:49 -0500[diff] [blame]1801#define RS600_WRITE_MCIND(addr, val) \
1802do { \
1803 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \
1804 RADEON_WRITE(RS600_MC_DATA, val); \
1805} while (0)
1806
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]1807#define IGP_WRITE_MCIND(addr, val) \
1808do { \
Alex Deucherf0738e92008-10-16 17:12:02 +1000[diff] [blame]1809 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1810 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]1811 RS690_WRITE_MCIND(addr, val); \
Alex Deucherc1556f72009-02-25 16:57:49 -0500[diff] [blame]1812 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \
1813 RS600_WRITE_MCIND(addr, val); \
Alex Deucher45e51902008-05-28 13:28:59 +1000[diff] [blame]1814 else \
1815 RS480_WRITE_MCIND(addr, val); \
1816} while (0)
1817
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1818#define CP_PACKET0( reg, n ) \
1819 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1820#define CP_PACKET0_TABLE( reg, n ) \
1821 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1822#define CP_PACKET1( reg0, reg1 ) \
1823 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1824#define CP_PACKET2() \
1825 (RADEON_CP_PACKET2)
1826#define CP_PACKET3( pkt, n ) \
1827 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1828
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1829/* ================================================================
1830 * Engine control helper macros
1831 */
1832
1833#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1834 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1835 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1836 RADEON_WAIT_HOST_IDLECLEAN) ); \
1837} while (0)
1838
1839#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1840 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1841 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1842 RADEON_WAIT_HOST_IDLECLEAN) ); \
1843} while (0)
1844
1845#define RADEON_WAIT_UNTIL_IDLE() do { \
1846 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1847 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1848 RADEON_WAIT_3D_IDLECLEAN | \
1849 RADEON_WAIT_HOST_IDLECLEAN) ); \
1850} while (0)
1851
1852#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1853 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1854 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1855} while (0)
1856
1857#define RADEON_FLUSH_CACHE() do { \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1858 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1859 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1860 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1861 } else { \
1862 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]1863 OUT_RING(R300_RB3D_DC_FLUSH); \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1864 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1865} while (0)
1866
1867#define RADEON_PURGE_CACHE() do { \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1868 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1869 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]1870 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1871 } else { \
1872 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]1873 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1874 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1875} while (0)
1876
1877#define RADEON_FLUSH_ZCACHE() do { \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1878 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1879 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1880 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1881 } else { \
1882 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1883 OUT_RING(R300_ZC_FLUSH); \
1884 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1885} while (0)
1886
1887#define RADEON_PURGE_ZCACHE() do { \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1888 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1889 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]1890 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1891 } else { \
Jerome Glisse54f961a2008-08-13 09:46:31 +1000[diff] [blame]1892 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1893 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
Alex Deucher259434a2008-05-28 11:51:12 +1000[diff] [blame]1894 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1895} while (0)
1896
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1897/* ================================================================
1898 * Misc helper macros
1899 */
1900
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]1901/* Perfbox functionality only.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1902 */
1903#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1904do { \
1905 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1906 u32 head = GET_RING_HEAD( dev_priv ); \
1907 if (head == dev_priv->ring.tail) \
1908 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1909 } \
1910} while (0)
1911
1912#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
Dave Airlie7c1c2872008-11-28 14:22:24 +1000[diff] [blame]1913do { \
1914 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \
1915 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1916 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
Alex Deucherc05ce082009-02-24 16:22:29 -0500[diff] [blame]1917 int __ret; \
1918 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
1919 __ret = r600_do_cp_idle(dev_priv); \
1920 else \
1921 __ret = radeon_do_cp_idle(dev_priv); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1922 if ( __ret ) return __ret; \
1923 sarea_priv->last_dispatch = 0; \
1924 radeon_freelist_reset( dev ); \
1925 } \
1926} while (0)
1927
1928#define RADEON_DISPATCH_AGE( age ) do { \
1929 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1930 OUT_RING( age ); \
1931} while (0)
1932
1933#define RADEON_FRAME_AGE( age ) do { \
1934 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1935 OUT_RING( age ); \
1936} while (0)
1937
1938#define RADEON_CLEAR_AGE( age ) do { \
1939 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1940 OUT_RING( age ); \
1941} while (0)
1942
Alex Deucherbefb73c2009-02-24 14:02:13 -0500[diff] [blame]1943#define R600_DISPATCH_AGE(age) do { \
1944 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
1945 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
1946 OUT_RING(age); \
1947} while (0)
1948
1949#define R600_FRAME_AGE(age) do { \
1950 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
1951 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
1952 OUT_RING(age); \
1953} while (0)
1954
1955#define R600_CLEAR_AGE(age) do { \
1956 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
1957 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
1958 OUT_RING(age); \
1959} while (0)
1960
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1961/* ================================================================
1962 * Ring control
1963 */
1964
1965#define RADEON_VERBOSE 0
1966
Dave Airlie4247ca92009-02-20 13:28:34 +1000[diff] [blame]1967#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1968
Dave Airlie98638712009-06-04 07:08:13 +1000[diff] [blame]1969#define RADEON_RING_ALIGN 16
1970
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1971#define BEGIN_RING( n ) do { \
1972 if ( RADEON_VERBOSE ) { \
Márton Németh3e684ea2008-01-24 15:58:57 +1000[diff] [blame]1973 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1974 } \
Dave Airlie98638712009-06-04 07:08:13 +1000[diff] [blame]1975 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN-1)); \
1976 _align_nr += n; \
Dave Airlie4247ca92009-02-20 13:28:34 +1000[diff] [blame]1977 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1978 COMMIT_RING(); \
Dave Airlie4247ca92009-02-20 13:28:34 +1000[diff] [blame]1979 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1980 } \
1981 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1982 ring = dev_priv->ring.start; \
1983 write = dev_priv->ring.tail; \
1984 mask = dev_priv->ring.tail_mask; \
1985} while (0)
1986
1987#define ADVANCE_RING() do { \
1988 if ( RADEON_VERBOSE ) { \
1989 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1990 write, dev_priv->ring.tail ); \
1991 } \
1992 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
Dave Airliebc5f4522007-11-05 12:50:58 +1000[diff] [blame]1993 DRM_ERROR( \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1994 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1995 ((dev_priv->ring.tail + _nr) & mask), \
Dave Airlie4247ca92009-02-20 13:28:34 +1000[diff] [blame]1996 write, __LINE__); \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1997 } else \
1998 dev_priv->ring.tail = write; \
1999} while (0)
2000
Dave Airlie4247ca92009-02-20 13:28:34 +1000[diff] [blame]2001extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
2002
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2003#define COMMIT_RING() do { \
Dave Airlie4247ca92009-02-20 13:28:34 +1000[diff] [blame]2004 radeon_commit_ring(dev_priv); \
2005 } while(0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2006
2007#define OUT_RING( x ) do { \
2008 if ( RADEON_VERBOSE ) { \
2009 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
2010 (unsigned int)(x), write ); \
2011 } \
2012 ring[write++] = (x); \
2013 write &= mask; \
2014} while (0)
2015
2016#define OUT_RING_REG( reg, val ) do { \
2017 OUT_RING( CP_PACKET0( reg, 0 ) ); \
2018 OUT_RING( val ); \
2019} while (0)
2020
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2021#define OUT_RING_TABLE( tab, sz ) do { \
2022 int _size = (sz); \
2023 int *_tab = (int *)(tab); \
2024 \
2025 if (write + _size > mask) { \
2026 int _i = (mask+1) - write; \
2027 _size -= _i; \
2028 while (_i > 0 ) { \
2029 *(int *)(ring + write) = *_tab++; \
2030 write++; \
2031 _i--; \
2032 } \
2033 write = 0; \
2034 _tab += _i; \
2035 } \
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2036 while (_size > 0) { \
2037 *(ring + write) = *_tab++; \
2038 write++; \
2039 _size--; \
2040 } \
2041 write &= mask; \
2042} while (0)
2043
Dave Airlieb5e89ed2005-09-25 14:28:13 +1000[diff] [blame]2044#endif /* __RADEON_DRV_H__ */