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gerrit-public.fairphone.software / fp2-dev / kernel / msm / ac2a54ffc2f0c2273f56728ac21cfb7dfc22ecd9 / . / arch / arm / boot / dts / msm8226.dtsi
blob: 7a029bad50fa9e3eccb2e048dc11789a50e4dc07 [file] [log] [blame]
Mitchel Humpherys85d08692012-10-23 12:56:35 -0700[diff] [blame]1/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13/include/ "skeleton.dtsi"
Mitchel Humpherys52ffaec2012-10-09 15:40:13 -0700[diff] [blame]14/include/ "msm8226-ion.dtsi"
Patrick Dalye8977aa2012-11-06 15:25:58 -0800[diff] [blame]15/include/ "msm-gdsc.dtsi"
Mitchel Humpherys85d08692012-10-23 12:56:35 -0700[diff] [blame]16/include/ "msm8226-iommu.dtsi"
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]17
18/ {
19 model = "Qualcomm MSM 8226";
20 compatible = "qcom,msm8226";
21 interrupt-parent = <&intc>;
22
23 intc: interrupt-controller@f9000000 {
24 compatible = "qcom,msm-qgic2";
25 interrupt-controller;
26 #interrupt-cells = <3>;
27 reg = <0xF9000000 0x1000>,
28 <0xF9002000 0x1000>;
29 };
30
31 msmgpio: gpio@fd510000 {
32 compatible = "qcom,msm-gpio";
33 interrupt-controller;
34 #interrupt-cells = <2>;
35 reg = <0xfd510000 0x4000>;
Syed Rameez Mustafa86cccfc2012-12-10 18:06:08 -0800[diff] [blame]36 gpio-controller;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]37 #gpio-cells = <2>;
Rohit Vaswani341c2032012-11-08 18:49:29 -0800[diff] [blame]38 ngpio = <117>;
Rohit Vaswanid2001522012-12-05 19:23:44 -0800[diff] [blame]39 interrupts = <0 208 0>;
Rohit Vaswanied0a4ef2012-12-11 15:14:42 -0800[diff] [blame]40 qcom,direct-connect-irqs = <8>;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]41 };
42
43 timer {
Syed Rameez Mustafa0824d6c2012-11-29 18:53:56 -0800[diff] [blame]44 compatible = "arm,armv7-timer";
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]45 interrupts = <1 2 0 1 3 0>;
46 clock-frequency = <19200000>;
47 };
48
49 serial@f991f000 {
50 compatible = "qcom,msm-lsuart-v14";
51 reg = <0xf991f000 0x1000>;
52 interrupts = <0 109 0>;
53 status = "disabled";
54 };
55
56 serial@f995e000 {
57 compatible = "qcom,msm-lsuart-v14";
58 reg = <0xf995e000 0x1000>;
59 interrupts = <0 114 0>;
60 status = "disabled";
61 };
62
Yan He7c06ce32012-12-03 17:12:31 -0800[diff] [blame]63 qcom,sps@f9984000 {
64 compatible = "qcom,msm_sps";
65 reg = <0xf9984000 0x15000>,
66 <0xf9999000 0xb000>;
67 interrupts = <0 94 0>;
68 };
69
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]70 usb@f9a55000 {
71 compatible = "qcom,hsusb-otg";
72 reg = <0xf9a55000 0x400>;
Mayank Ranaac2a54f2013-01-17 10:14:35 +0530[diff] [blame^]73 interrupts = <0 134 0>, <0 140 0>;
74 interrupt-names = "core_irq", "async_irq";
75 HSUSB_VDDCX-supply = <&pm8026_s1>;
76 HSUSB_1p8-supply = <&pm8026_l10>;
77 HSUSB_3p3-supply = <&pm8026_l20>;
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]78
79 qcom,hsusb-otg-phy-type = <2>;
80 qcom,hsusb-otg-mode = <1>;
81 qcom,hsusb-otg-otg-control = <1>;
82 qcom,hsusb-otg-disable-reset;
83 };
84
85 android_usb {
86 compatible = "qcom,android-usb";
87 };
88
Bhalchandra Gajare555bceb2012-12-12 22:48:34 -0800[diff] [blame]89 wcd9xxx_intc: wcd9xxx-irq {
90 compatible = "qcom,wcd9xxx-irq";
91 interrupt-controller;
92 #interrupt-cells = <1>;
93 interrupt-parent = <&msmgpio>;
94 interrupts = <68 0>;
95 interrupt-names = "cdc-int";
96 };
97
Bhalchandra Gajarefb785972012-12-06 19:25:10 -0800[diff] [blame]98 slim@fe12f000 {
99 cell-index = <1>;
100 compatible = "qcom,slim-ngd";
101 reg = <0xfe12f000 0x35000>,
102 <0xfe104000 0x20000>;
103 reg-names = "slimbus_physical", "slimbus_bam_physical";
104 interrupts = <0 163 0>, <0 164 0>;
105 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
Bhalchandra Gajare555bceb2012-12-12 22:48:34 -0800[diff] [blame]106
107 tapan_codec {
108 compatible = "qcom,tapan-slim-pgd";
109 elemental-addr = [00 01 E0 00 17 02];
110
111 interrupt-parent = <&wcd9xxx_intc>;
112 interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
113 17 18 19 20 21 22 23 24 25 26 27 28>;
114 qcom,cdc-reset-gpio = <&msmgpio 72 0>;
115
116 cdc-vdd-buck-supply = <&pm8026_s4>;
117 qcom,cdc-vdd-buck-voltage = <2100000 2100000>;
118 qcom,cdc-vdd-buck-current = <650000>;
119
120 cdc-vdd-h-supply = <&pm8026_l6>;
121 qcom,cdc-vdd-h-voltage = <1800000 1800000>;
122 qcom,cdc-vdd-h-current = <25000>;
123
124 cdc-vdd-px-supply = <&pm8026_l6>;
125 qcom,cdc-vdd-px-voltage = <1800000 1800000>;
126 qcom,cdc-vdd-px-current = <25000>;
127
128 cdc-vdd-a-1p2v-supply = <&pm8026_l4>;
129 qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>;
130 qcom,cdc-vdd-a-1p2v-current = <10000>;
131
132 cdc-vdd-cx-supply = <&pm8026_l4>;
133 qcom,cdc-vdd-cx-voltage = <1200000 1200000>;
134 qcom,cdc-vdd-cx-current = <10000>;
135
136 qcom,cdc-micbias-ldoh-v = <0x3>;
137 qcom,cdc-micbias-cfilt1-mv = <1800>;
138 qcom,cdc-micbias-cfilt2-mv = <1800>;
139 qcom,cdc-micbias-cfilt3-mv = <1800>;
140
141 qcom,cdc-micbias1-cfilt-sel = <0x0>;
142 qcom,cdc-micbias2-cfilt-sel = <0x1>;
143 qcom,cdc-micbias3-cfilt-sel = <0x2>;
144
145 qcom,cdc-mclk-clk-rate = <9600000>;
146 qcom,cdc-slim-ifd = "tapan-slim-ifd";
147 qcom,cdc-slim-ifd-elemental-addr = [00 00 E0 00 17 02];
148 };
Bhalchandra Gajarefb785972012-12-06 19:25:10 -0800[diff] [blame]149 };
150
Bhalchandra Gajaree1915b82012-12-12 17:28:39 -0800[diff] [blame]151 qcom,msm-adsp-loader {
152 compatible = "qcom,adsp-loader";
153 qcom,adsp-state = <0>;
154 };
155
Bhalchandra Gajare03a40ec2012-12-17 11:38:28 -0800[diff] [blame]156 sound {
157 compatible = "qcom,msm8226-audio-tapan";
158 qcom,model = "msm8226-tapan-snd-card";
159
160 qcom,audio-routing =
161 "RX_BIAS", "MCLK",
162 "LDO_H", "MCLK",
163 "AMIC1", "MIC BIAS1 Internal1",
164 "MIC BIAS1 Internal1", "Handset Mic",
165 "AMIC2", "MIC BIAS2 External",
166 "MIC BIAS2 External", "Headset Mic",
167 "AMIC3", "MIC BIAS2 External",
168 "MIC BIAS2 External", "ANCRight Headset Mic",
169 "AMIC4", "MIC BIAS2 External",
170 "MIC BIAS2 External", "ANCLeft Headset Mic",
171 "DMIC1", "MIC BIAS1 External",
172 "MIC BIAS1 External", "Digital Mic1",
173 "DMIC2", "MIC BIAS1 External",
174 "MIC BIAS1 External", "Digital Mic2",
175 "DMIC3", "MIC BIAS3 External",
176 "MIC BIAS3 External", "Digital Mic3",
177 "DMIC4", "MIC BIAS3 External",
178 "MIC BIAS3 External", "Digital Mic4",
179 "DMIC5", "MIC BIAS4 External",
180 "MIC BIAS4 External", "Digital Mic5",
181 "DMIC6", "MIC BIAS4 External",
182 "MIC BIAS4 External", "Digital Mic6";
183 qcom,tapan-mclk-clk-freq = <9600000>;
184 };
185
186 qcom,msm-pcm {
187 compatible = "qcom,msm-pcm-dsp";
188 };
189
190 qcom,msm-pcm-routing {
191 compatible = "qcom,msm-pcm-routing";
192 };
193
194 qcom,msm-pcm-lpa {
195 compatible = "qcom,msm-pcm-lpa";
196 };
197
198 qcom,msm-compr-dsp {
199 compatible = "qcom,msm-compr-dsp";
200 };
201
202 qcom,msm-voip-dsp {
203 compatible = "qcom,msm-voip-dsp";
204 };
205
206 qcom,msm-pcm-voice {
207 compatible = "qcom,msm-pcm-voice";
208 };
209
210 qcom,msm-stub-codec {
211 compatible = "qcom,msm-stub-codec";
212 };
213
214 qcom,msm-dai-fe {
215 compatible = "qcom,msm-dai-fe";
216 };
217
218 qcom,msm-pcm-afe {
219 compatible = "qcom,msm-pcm-afe";
220 };
221
222 qcom,msm-dai-q6-hdmi {
223 compatible = "qcom,msm-dai-q6-hdmi";
224 qcom,msm-dai-q6-dev-id = <8>;
225 };
226
227 qcom,msm-dai-q6 {
228 compatible = "qcom,msm-dai-q6";
229 qcom,msm-dai-q6-sb-0-rx {
230 compatible = "qcom,msm-dai-q6-dev";
231 qcom,msm-dai-q6-dev-id = <16384>;
232 };
233
234 qcom,msm-dai-q6-sb-0-tx {
235 compatible = "qcom,msm-dai-q6-dev";
236 qcom,msm-dai-q6-dev-id = <16385>;
237 };
238
239 qcom,msm-dai-q6-sb-1-rx {
240 compatible = "qcom,msm-dai-q6-dev";
241 qcom,msm-dai-q6-dev-id = <16386>;
242 };
243
244 qcom,msm-dai-q6-sb-1-tx {
245 compatible = "qcom,msm-dai-q6-dev";
246 qcom,msm-dai-q6-dev-id = <16387>;
247 };
248
249 qcom,msm-dai-q6-sb-3-rx {
250 compatible = "qcom,msm-dai-q6-dev";
251 qcom,msm-dai-q6-dev-id = <16390>;
252 };
253
254 qcom,msm-dai-q6-sb-3-tx {
255 compatible = "qcom,msm-dai-q6-dev";
256 qcom,msm-dai-q6-dev-id = <16391>;
257 };
258
259 qcom,msm-dai-q6-sb-4-rx {
260 compatible = "qcom,msm-dai-q6-dev";
261 qcom,msm-dai-q6-dev-id = <16392>;
262 };
263
264 qcom,msm-dai-q6-sb-4-tx {
265 compatible = "qcom,msm-dai-q6-dev";
266 qcom,msm-dai-q6-dev-id = <16393>;
267 };
268
269 qcom,msm-dai-q6-bt-sco-rx {
270 compatible = "qcom,msm-dai-q6-dev";
271 qcom,msm-dai-q6-dev-id = <12288>;
272 };
273
274 qcom,msm-dai-q6-bt-sco-tx {
275 compatible = "qcom,msm-dai-q6-dev";
276 qcom,msm-dai-q6-dev-id = <12289>;
277 };
278
279 qcom,msm-dai-q6-int-fm-rx {
280 compatible = "qcom,msm-dai-q6-dev";
281 qcom,msm-dai-q6-dev-id = <12292>;
282 };
283
284 qcom,msm-dai-q6-int-fm-tx {
285 compatible = "qcom,msm-dai-q6-dev";
286 qcom,msm-dai-q6-dev-id = <12293>;
287 };
288
289 qcom,msm-dai-q6-be-afe-pcm-rx {
290 compatible = "qcom,msm-dai-q6-dev";
291 qcom,msm-dai-q6-dev-id = <224>;
292 };
293
294 qcom,msm-dai-q6-be-afe-pcm-tx {
295 compatible = "qcom,msm-dai-q6-dev";
296 qcom,msm-dai-q6-dev-id = <225>;
297 };
298
299 qcom,msm-dai-q6-afe-proxy-rx {
300 compatible = "qcom,msm-dai-q6-dev";
301 qcom,msm-dai-q6-dev-id = <241>;
302 };
303
304 qcom,msm-dai-q6-afe-proxy-tx {
305 compatible = "qcom,msm-dai-q6-dev";
306 qcom,msm-dai-q6-dev-id = <240>;
307 };
308 };
309
310 qcom,msm-pcm-hostless {
311 compatible = "qcom,msm-pcm-hostless";
312 };
313
Mitchel Humpherys5fe1c9b2012-10-09 17:30:19 -0700[diff] [blame]314 qcom,wdt@f9017000 {
315 compatible = "qcom,msm-watchdog";
316 reg = <0xf9017000 0x1000>;
317 interrupts = <0 3 0>, <0 4 0>;
318 qcom,bark-time = <11000>;
319 qcom,pet-time = <10000>;
Mitchel Humpherys1be23802012-11-16 15:52:32 -0800[diff] [blame]320 qcom,ipi-ping;
Mitchel Humpherys5fe1c9b2012-10-09 17:30:19 -0700[diff] [blame]321 };
322
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]323 qcom,smem@fa00000 {
324 compatible = "qcom,smem";
325 reg = <0xfa00000 0x200000>,
326 <0xfa006000 0x1000>,
327 <0xfc428000 0x4000>;
328 reg-names = "smem", "irq-reg-base", "aux-mem1";
329
330 qcom,smd-modem {
331 compatible = "qcom,smd";
332 qcom,smd-edge = <0>;
333 qcom,smd-irq-offset = <0x8>;
334 qcom,smd-irq-bitmask = <0x1000>;
335 qcom,pil-string = "modem";
336 interrupts = <0 25 1>;
David Ngb715e322012-12-01 12:57:08 -0800[diff] [blame]337 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]338
339 qcom,smsm-modem {
340 compatible = "qcom,smsm";
341 qcom,smsm-edge = <0>;
342 qcom,smsm-irq-offset = <0x8>;
343 qcom,smsm-irq-bitmask = <0x2000>;
344 interrupts = <0 26 1>;
David Ngb715e322012-12-01 12:57:08 -0800[diff] [blame]345 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]346
347 qcom,smd-adsp {
348 compatible = "qcom,smd";
349 qcom,smd-edge = <1>;
350 qcom,smd-irq-offset = <0x8>;
351 qcom,smd-irq-bitmask = <0x100>;
352 qcom,pil-string = "adsp";
353 interrupts = <0 156 1>;
David Ngb715e322012-12-01 12:57:08 -0800[diff] [blame]354 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]355
356 qcom,smsm-adsp {
357 compatible = "qcom,smsm";
358 qcom,smsm-edge = <1>;
359 qcom,smsm-irq-offset = <0x8>;
360 qcom,smsm-irq-bitmask = <0x200>;
361 interrupts = <0 157 1>;
David Ngb715e322012-12-01 12:57:08 -0800[diff] [blame]362 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]363
364 qcom,smd-wcnss {
365 compatible = "qcom,smd";
366 qcom,smd-edge = <6>;
367 qcom,smd-irq-offset = <0x8>;
368 qcom,smd-irq-bitmask = <0x20000>;
369 qcom,pil-string = "wcnss";
370 interrupts = <0 142 1>;
David Ngb715e322012-12-01 12:57:08 -0800[diff] [blame]371 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]372
373 qcom,smsm-wcnss {
374 compatible = "qcom,smsm";
375 qcom,smsm-edge = <6>;
376 qcom,smsm-irq-offset = <0x8>;
377 qcom,smsm-irq-bitmask = <0x80000>;
378 interrupts = <0 144 1>;
David Ngb715e322012-12-01 12:57:08 -0800[diff] [blame]379 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]380
381 qcom,smd-rpm {
382 compatible = "qcom,smd";
383 qcom,smd-edge = <15>;
384 qcom,smd-irq-offset = <0x8>;
385 qcom,smd-irq-bitmask = <0x1>;
386 interrupts = <0 168 1>;
387 qcom,irq-no-suspend;
David Ngb715e322012-12-01 12:57:08 -0800[diff] [blame]388 };
Jeff Hugo7f9705b62012-10-12 10:38:26 -0600[diff] [blame]389 };
390
Asutosh Das99912e62012-12-06 12:38:46 +0530[diff] [blame]391 sdcc1: qcom,sdcc@f9824000 {
392 cell-index = <1>; /* SDC1 eMMC slot */
393 compatible = "qcom,msm-sdcc";
394
Asutosh Das6b82fc52012-11-23 12:00:26 +0530[diff] [blame]395 reg = <0xf9824000 0x800>,
396 <0xf9824800 0x100>,
397 <0xf9804000 0x7000>;
398 reg-names = "core_mem", "dml_mem", "bam_mem";
399 interrupts = <0 123 0>, <0 137 0>;
400 interrupt-names = "core_irq", "bam_irq";
Asutosh Das99912e62012-12-06 12:38:46 +0530[diff] [blame]401
402 qcom,bus-width = <8>;
403 status = "disabled";
404 };
405
406 sdcc2: qcom,sdcc@f98a4000 {
407 cell-index = <2>; /* SDC2 SD card slot */
408 compatible = "qcom,msm-sdcc";
409
Asutosh Das6b82fc52012-11-23 12:00:26 +0530[diff] [blame]410 reg = <0xf98a4000 0x800>,
411 <0xf98a4800 0x100>,
412 <0xf9884000 0x7000>;
413 reg-names = "core_mem", "dml_mem", "bam_mem";
414 interrupts = <0 125 0>, <0 220 0>;
415 interrupt-names = "core_irq", "bam_irq";
Asutosh Das99912e62012-12-06 12:38:46 +0530[diff] [blame]416
417 qcom,bus-width = <4>;
418 status = "disabled";
419 };
Kenneth Heitkee5804002012-11-15 17:50:07 -0700[diff] [blame]420
421 spmi_bus: qcom,spmi@fc4c0000 {
422 cell-index = <0>;
423 compatible = "qcom,spmi-pmic-arb";
424 reg = <0xfc4cf000 0x1000>,
425 <0Xfc4cb000 0x1000>;
426 /* 190,ee0_krait_hlos_spmi_periph_irq */
427 /* 187,channel_0_krait_hlos_trans_done_irq */
428 interrupts = <0 190 0>, <0 187 0>;
429 qcom,not-wakeup;
430 qcom,pmic-arb-ee = <0>;
431 qcom,pmic-arb-channel = <0>;
432 qcom,pmic-arb-ppid-map = <0x001000a0>, /* PM8026_0 */
433 <0x005000a2>, /* INTERRUPT */
434 <0x006000a3>, /* SPMI_0 */
435 <0x00800000>, /* PON0 */
436 <0x00a000a5>, /* VREF_LPDDR3 */
437 <0x01000001>, /* SMBB_CHG */
438 <0x01100002>, /* SMBB_BUCK */
439 <0x01200003>, /* SMBB_BIF */
440 <0x01300004>, /* SMBB_USB */
441 <0x01500005>, /* SMBB_BOOST */
442 <0x01600006>, /* SMBB_MISC */
443 <0x02800009>, /* COINCELL */
444 <0x02c000a6>, /* MBG */
445 <0x0310000a>, /* VADC1_USR */
446 <0x03200041>, /* VADC1_MDM */
447 <0x0330000b>, /* VADC1_BMS */
448 <0x0340000c>, /* VADC2_BTM */
449 <0x0360000d>, /* IADC1_USR */
450 <0x03700042>, /* IADC1_MDM */
451 <0x0380000e>, /* IADC1_BMS */
452 <0x0400000f>, /* BMS_1 */
453 <0x050000a7>, /* SHARED_XO */
454 <0x051000a8>, /* BB_CLK1 */
455 <0x05200010>, /* BB_CLK2 */
456 <0x05a000ac>, /* SLEEP_CLK */
457 <0x06000045>, /* RTC_RW */
458 <0x06100012>, /* RTC_ALARM */
459 <0x070000ae>, /* PBS_CORE */
460 <0x071000af>, /* PBS_CLIENT_1 */
461 <0x072000b0>, /* PBS_CLIENT_2 */
462 <0x073000b1>, /* PBS_CLIENT_3 */
463 <0x074000b2>, /* PBS_CLIENT_4 */
464 <0x075000b3>, /* PBS_CLIENT_5 */
465 <0x076000b4>, /* PBS_CLIENT_6 */
466 <0x07700046>, /* PBS_CLIENT_7 */
467 <0x07800047>, /* PBS_CLIENT_8 */
468 <0x079000b5>, /* PBS_CLIENT_9 */
469 <0x07a000b6>, /* PBS_CLIENT_10 */
470 <0x07b000b7>, /* PBS_CLIENT_11 */
471 <0x07c000b8>, /* PBS_CLIENT_12 */
472 <0x07d000b9>, /* PBS_CLIENT_13 */
473 <0x07e000ba>, /* PBS_CLIENT_14 */
474 <0x07f000bb>, /* PBS_CLIENT_15 */
475 <0x0a0000bd>, /* MPP_1 */
476 <0x0a100014>, /* MPP_2 */
477 <0x0a200015>, /* MPP_3 */
478 <0x0a300016>, /* MPP_4 */
479 <0x0a400048>, /* MPP_5 */
480 <0x0a500017>, /* MPP_6 */
481 <0x0a600018>, /* MPP_7 */
482 <0x0a700049>, /* MPP_8 */
483 <0x0c000019>, /* GPIO_1 */
484 <0x0c10001a>, /* GPIO_2 */
485 <0x0c20004a>, /* GPIO_3 */
486 <0x0c30004b>, /* GPIO_4 */
487 <0x0c40001b>, /* GPIO_5 */
488 <0x0c50001c>, /* GPIO_6 */
489 <0x0c60001d>, /* GPIO_7 */
490 <0x0c70004c>, /* GPIO_8 */
491 <0x0fe000be>, /* TRIM_0 */
492 <0x110000bf>, /* BUCK_CMN_1 */
493 <0x114000c0>, /* SMPS1 */
494 <0x115000c1>, /* FTPS1_1 */
495 <0x116000c2>, /* BUCK_FREQ_1 */
496 <0x1170001e>, /* SMPS2 */
497 <0x1180001f>, /* FTPS1_2 */
498 <0x11900020>, /* BUCK_FREQ_2 */
499 <0x11a000c3>, /* SMPS3 */
500 <0x11b000c4>, /* SMPS_3_PS1 */
501 <0x11c000c5>, /* BUCK_FREQ_3 */
502 <0x11d000c6>, /* SMPS4 */
503 <0x11e000c7>, /* SMPS_4_PS1 */
504 <0x11f000c8>, /* BUCK_FREQ_4 */
505 <0x120000c9>, /* SMPS5 */
506 <0x121000ca>, /* SMPS_5_PS1 */
507 <0x122000cb>, /* BUCK_FREQ_5 */
508 <0x140000cc>, /* LDO_1 */
509 <0x141000cd>, /* LDO_2 */
510 <0x142000ce>, /* LDO_3 */
511 <0x143000cf>, /* LDO_4 */
512 <0x144000d0>, /* LDO_5 */
513 <0x145000d1>, /* LDO_6 */
514 <0x146000d2>, /* LDO_7 */
515 <0x147000d3>, /* LDO_8 */
516 <0x148000d4>, /* LDO_9 */
517 <0x149000d5>, /* LDO_10 */
518 <0x14a000d6>, /* LDO_11 */
519 <0x14b000d7>, /* LDO_12 */
520 <0x14c000d8>, /* LDO_13 */
521 <0x14d000d9>, /* LDO_14 */
522 <0x14e000da>, /* LDO_15 */
523 <0x14f000db>, /* LDO_16 */
524 <0x150000dc>, /* LDO_17 */
525 <0x151000dd>, /* LDO_18 */
526 <0x152000de>, /* LDO_19 */
527 <0x153000df>, /* LDO_20 */
528 <0x154000e0>, /* LDO_21 */
529 <0x155000e1>, /* LDO_22 */
530 <0x156000e2>, /* LDO_23 */
531 <0x157000e3>, /* LDO_24 */
532 <0x158000e4>, /* LDO_25 */
533 <0x159000e5>, /* LDO_26 */
534 <0x15a000e6>, /* LDO_27 */
535 <0x15b000e7>, /* LDO_28 */
536 <0x180000e8>, /* LVS_1 */
537 <0x1b0000e9>, /* LPG_LUT */
538 <0x1b1000ea>, /* LPG_CHAN_1 */
539 <0x1b200023>, /* LPG_CHAN_2 */
540 <0x1b300024>, /* LPG_CHAN_3 */
541 <0x1b400025>, /* LPG_CHAN_4 */
542 <0x1b500026>, /* LPG_CHAN_5 */
543 <0x1b600027>, /* LPG_CHAN_6 */
544 <0x1bc00028>, /* PWM_3D */
545 <0x1c000029>, /* VIB1 */
546 <0x1d30002a>, /* FLASH_DRV */
547 <0x1d80002b>; /* WLED */
548 };
549
Gilad Avidov28e18eb2012-11-21 18:13:25 -0700[diff] [blame]550 i2c@f9926000 { /* BLSP-1 QUP-4 */
551 cell-index = <0>;
552 compatible = "qcom,i2c-qup";
553 reg = <0xf9926000 0x1000>;
554 #address-cells = <1>;
555 #size-cells = <0>;
556 reg-names = "qup_phys_addr";
557 interrupts = <0 98 0>;
558 interrupt-names = "qup_err_intr";
559 qcom,i2c-bus-freq = <100000>;
560 };
Syed Rameez Mustafa332018f2012-10-11 18:01:59 -0700[diff] [blame]561};
David Collins37ddb972012-10-17 15:00:26 -0700[diff] [blame]562
Patrick Dalye8977aa2012-11-06 15:25:58 -0800[diff] [blame]563&gdsc_venus {
564 status = "ok";
565};
566
567&gdsc_mdss {
568 status = "ok";
569};
570
571&gdsc_jpeg {
572 status = "ok";
573};
574
575&gdsc_vfe {
576 status = "ok";
577};
578
579&gdsc_oxili_cx {
580 status = "ok";
581};
582
583&gdsc_usb_hsic {
584 status = "ok";
585};
586
David Collins37ddb972012-10-17 15:00:26 -0700[diff] [blame]587/include/ "msm8226-regulator.dtsi"
Kenneth Heitkee5804002012-11-15 17:50:07 -0700[diff] [blame]588/include/ "msm-pm8026.dtsi"