| Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-2009 Analog Devices Inc. |
| 3 | * |
| 4 | * Licensed under the GPL-2 or later |
| 5 | */ |
| 6 | |
| Michael Hennerich | 5610db6 | 2007-07-12 12:32:52 +0800 | [diff] [blame] | 7 | #ifndef _MACH_PORTMUX_H_ |
| 8 | #define _MACH_PORTMUX_H_ |
| 9 | |
| Mike Frysinger | 812ae98 | 2010-07-05 08:40:41 +0000 | [diff] [blame] | 10 | #define MAX_RESOURCES MAX_BLACKFIN_GPIOS |
| Michael Hennerich | fac3cf4 | 2007-12-24 20:07:03 +0800 | [diff] [blame] | 11 | |
| Michael Hennerich | 5610db6 | 2007-07-12 12:32:52 +0800 | [diff] [blame] | 12 | #define P_PPI0_CLK (P_DONTCARE) |
| 13 | #define P_PPI0_FS1 (P_DONTCARE) |
| 14 | #define P_PPI0_FS2 (P_DONTCARE) |
| 15 | #define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3)) |
| 16 | #define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4)) |
| 17 | #define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5)) |
| 18 | #define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6)) |
| 19 | #define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7)) |
| 20 | #define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8)) |
| 21 | #define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9)) |
| 22 | #define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10)) |
| 23 | #define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11)) |
| 24 | #define P_PPI0_D0 (P_DONTCARE) |
| 25 | #define P_PPI0_D1 (P_DONTCARE) |
| 26 | #define P_PPI0_D2 (P_DONTCARE) |
| 27 | #define P_PPI0_D3 (P_DONTCARE) |
| 28 | #define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15)) |
| 29 | #define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14)) |
| 30 | #define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13)) |
| 31 | #define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12)) |
| 32 | |
| 33 | #define P_SPORT1_TSCLK (P_DONTCARE) |
| 34 | #define P_SPORT1_RSCLK (P_DONTCARE) |
| 35 | #define P_SPORT0_TSCLK (P_DONTCARE) |
| 36 | #define P_SPORT0_RSCLK (P_DONTCARE) |
| 37 | #define P_UART0_RX (P_DONTCARE) |
| 38 | #define P_UART0_TX (P_DONTCARE) |
| 39 | #define P_SPORT1_DRSEC (P_DONTCARE) |
| 40 | #define P_SPORT1_RFS (P_DONTCARE) |
| 41 | #define P_SPORT1_DTPRI (P_DONTCARE) |
| 42 | #define P_SPORT1_DTSEC (P_DONTCARE) |
| 43 | #define P_SPORT1_TFS (P_DONTCARE) |
| 44 | #define P_SPORT1_DRPRI (P_DONTCARE) |
| 45 | #define P_SPORT0_DRSEC (P_DONTCARE) |
| 46 | #define P_SPORT0_RFS (P_DONTCARE) |
| 47 | #define P_SPORT0_DTPRI (P_DONTCARE) |
| 48 | #define P_SPORT0_DTSEC (P_DONTCARE) |
| 49 | #define P_SPORT0_TFS (P_DONTCARE) |
| 50 | #define P_SPORT0_DRPRI (P_DONTCARE) |
| 51 | |
| 52 | #define P_SPI0_MOSI (P_DONTCARE) |
| Michael Hennerich | cc2f81a | 2007-12-04 23:45:13 -0800 | [diff] [blame] | 53 | #define P_SPI0_MISO (P_DONTCARE) |
| Michael Hennerich | 5610db6 | 2007-07-12 12:32:52 +0800 | [diff] [blame] | 54 | #define P_SPI0_SCK (P_DONTCARE) |
| 55 | #define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7)) |
| 56 | #define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6)) |
| 57 | #define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5)) |
| 58 | #define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4)) |
| 59 | #define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3)) |
| 60 | #define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2)) |
| 61 | #define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1)) |
| 62 | #define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0)) |
| Mike Frysinger | 306208f | 2010-06-08 19:53:45 +0000 | [diff] [blame] | 63 | #define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2 |
| Sonic Zhang | b52dae3 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 64 | #define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2 |
| Michael Hennerich | 5610db6 | 2007-07-12 12:32:52 +0800 | [diff] [blame] | 65 | |
| 66 | #define P_TMR2 (P_DONTCARE) |
| 67 | #define P_TMR1 (P_DONTCARE) |
| 68 | #define P_TMR0 (P_DONTCARE) |
| 69 | #define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1)) |
| 70 | |
| Michael Hennerich | 5610db6 | 2007-07-12 12:32:52 +0800 | [diff] [blame] | 71 | #endif /* _MACH_PORTMUX_H_ */ |