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Michael Hennerichdb682542008-04-24 03:18:59 +08001/*
Robin Getz96f10502009-09-24 14:11:24 +00002 * Copyright 2004-2009 Analog Devices Inc.
3 * 2008-2009 Bluetechnix
4 * 2005 National ICT Australia (NICTA)
5 * Aidan Williams <aidan@nicta.com.au>
Michael Hennerichdb682542008-04-24 03:18:59 +08006 *
Robin Getz96f10502009-09-24 14:11:24 +00007 * Licensed under the GPL-2 or later.
Michael Hennerichdb682542008-04-24 03:18:59 +08008 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
Mike Frysinger2de73e72008-11-18 17:48:22 +080014#include <linux/mtd/physmap.h>
Michael Hennerichdb682542008-04-24 03:18:59 +080015#include <linux/spi/spi.h>
16#include <linux/spi/flash.h>
17#include <linux/irq.h>
18#include <linux/interrupt.h>
19#include <linux/usb/musb.h>
20#include <asm/bfin5xx_spi.h>
Michael Hennerichdb682542008-04-24 03:18:59 +080021#include <asm/dma.h>
22#include <asm/gpio.h>
23#include <asm/nand.h>
24#include <asm/portmux.h>
Mike Frysinger8d8921a2009-01-07 23:14:39 +080025#include <asm/bfin_sdh.h>
Bryan Wu639f6572008-08-27 10:51:02 +080026#include <mach/bf54x_keys.h>
Michael Hennerich14b03202008-05-07 11:41:26 +080027#include <asm/dpmc.h>
Michael Hennerichdb682542008-04-24 03:18:59 +080028#include <linux/input.h>
29#include <linux/spi/ad7877.h>
30
31/*
32 * Name the Board for the /proc/cpuinfo
33 */
34const char bfin_board_name[] = "Bluetechnix CM-BF548";
35
36/*
37 * Driver needs to know address, irq and flag pin.
38 */
39
40#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
41
Bryan Wu639f6572008-08-27 10:51:02 +080042#include <mach/bf54x-lq043.h>
Michael Hennerichdb682542008-04-24 03:18:59 +080043
44static struct bfin_bf54xfb_mach_info bf54x_lq043_data = {
45 .width = 480,
46 .height = 272,
47 .xres = {480, 480, 480},
48 .yres = {272, 272, 272},
49 .bpp = {24, 24, 24},
50 .disp = GPIO_PE3,
51};
52
53static struct resource bf54x_lq043_resources[] = {
54 {
55 .start = IRQ_EPPI0_ERR,
56 .end = IRQ_EPPI0_ERR,
57 .flags = IORESOURCE_IRQ,
58 },
59};
60
61static struct platform_device bf54x_lq043_device = {
62 .name = "bf54x-lq043",
63 .id = -1,
64 .num_resources = ARRAY_SIZE(bf54x_lq043_resources),
65 .resource = bf54x_lq043_resources,
66 .dev = {
67 .platform_data = &bf54x_lq043_data,
68 },
69};
70#endif
71
72#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
73static unsigned int bf548_keymap[] = {
74 KEYVAL(0, 0, KEY_ENTER),
75 KEYVAL(0, 1, KEY_HELP),
76 KEYVAL(0, 2, KEY_0),
77 KEYVAL(0, 3, KEY_BACKSPACE),
78 KEYVAL(1, 0, KEY_TAB),
79 KEYVAL(1, 1, KEY_9),
80 KEYVAL(1, 2, KEY_8),
81 KEYVAL(1, 3, KEY_7),
82 KEYVAL(2, 0, KEY_DOWN),
83 KEYVAL(2, 1, KEY_6),
84 KEYVAL(2, 2, KEY_5),
85 KEYVAL(2, 3, KEY_4),
86 KEYVAL(3, 0, KEY_UP),
87 KEYVAL(3, 1, KEY_3),
88 KEYVAL(3, 2, KEY_2),
89 KEYVAL(3, 3, KEY_1),
90};
91
92static struct bfin_kpad_platform_data bf54x_kpad_data = {
93 .rows = 4,
94 .cols = 4,
95 .keymap = bf548_keymap,
96 .keymapsize = ARRAY_SIZE(bf548_keymap),
97 .repeat = 0,
98 .debounce_time = 5000, /* ns (5ms) */
99 .coldrive_time = 1000, /* ns (1ms) */
100 .keyup_test_interval = 50, /* ms (50ms) */
101};
102
103static struct resource bf54x_kpad_resources[] = {
104 {
105 .start = IRQ_KEY,
106 .end = IRQ_KEY,
107 .flags = IORESOURCE_IRQ,
108 },
109};
110
111static struct platform_device bf54x_kpad_device = {
112 .name = "bf54x-keys",
113 .id = -1,
114 .num_resources = ARRAY_SIZE(bf54x_kpad_resources),
115 .resource = bf54x_kpad_resources,
116 .dev = {
117 .platform_data = &bf54x_kpad_data,
118 },
119};
120#endif
121
122#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
123static struct platform_device rtc_device = {
124 .name = "rtc-bfin",
125 .id = -1,
126};
127#endif
128
129#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
Michael Hennerichdb682542008-04-24 03:18:59 +0800130#ifdef CONFIG_SERIAL_BFIN_UART0
Sonic Zhang6bd1fbe2009-09-09 10:46:19 +0000131static struct resource bfin_uart0_resources[] = {
Michael Hennerichdb682542008-04-24 03:18:59 +0800132 {
Sonic Zhang6bd1fbe2009-09-09 10:46:19 +0000133 .start = UART0_DLL,
134 .end = UART0_RBR+2,
Michael Hennerichdb682542008-04-24 03:18:59 +0800135 .flags = IORESOURCE_MEM,
136 },
Sonic Zhang6bd1fbe2009-09-09 10:46:19 +0000137 {
138 .start = IRQ_UART0_RX,
139 .end = IRQ_UART0_RX+1,
140 .flags = IORESOURCE_IRQ,
141 },
142 {
143 .start = IRQ_UART0_ERROR,
144 .end = IRQ_UART0_ERROR,
145 .flags = IORESOURCE_IRQ,
146 },
147 {
148 .start = CH_UART0_TX,
149 .end = CH_UART0_TX,
150 .flags = IORESOURCE_DMA,
151 },
152 {
153 .start = CH_UART0_RX,
154 .end = CH_UART0_RX,
155 .flags = IORESOURCE_DMA,
156 },
157};
158
Mike Frysingera8b19882010-11-24 09:23:04 +0000159static unsigned short bfin_uart0_peripherals[] = {
Sonic Zhang6bd1fbe2009-09-09 10:46:19 +0000160 P_UART0_TX, P_UART0_RX, 0
161};
162
163static struct platform_device bfin_uart0_device = {
164 .name = "bfin-uart",
165 .id = 0,
166 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
167 .resource = bfin_uart0_resources,
168 .dev = {
169 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
170 },
171};
Michael Hennerichdb682542008-04-24 03:18:59 +0800172#endif
173#ifdef CONFIG_SERIAL_BFIN_UART1
Sonic Zhang6bd1fbe2009-09-09 10:46:19 +0000174static struct resource bfin_uart1_resources[] = {
Michael Hennerichdb682542008-04-24 03:18:59 +0800175 {
Sonic Zhang6bd1fbe2009-09-09 10:46:19 +0000176 .start = UART1_DLL,
177 .end = UART1_RBR+2,
Michael Hennerichdb682542008-04-24 03:18:59 +0800178 .flags = IORESOURCE_MEM,
179 },
Michael Hennerichdb682542008-04-24 03:18:59 +0800180 {
Sonic Zhang6bd1fbe2009-09-09 10:46:19 +0000181 .start = IRQ_UART1_RX,
182 .end = IRQ_UART1_RX+1,
183 .flags = IORESOURCE_IRQ,
Michael Hennerichdb682542008-04-24 03:18:59 +0800184 },
Michael Hennerichdb682542008-04-24 03:18:59 +0800185 {
Sonic Zhang6bd1fbe2009-09-09 10:46:19 +0000186 .start = IRQ_UART1_ERROR,
187 .end = IRQ_UART1_ERROR,
188 .flags = IORESOURCE_IRQ,
189 },
190 {
191 .start = CH_UART1_TX,
192 .end = CH_UART1_TX,
193 .flags = IORESOURCE_DMA,
194 },
195 {
196 .start = CH_UART1_RX,
197 .end = CH_UART1_RX,
198 .flags = IORESOURCE_DMA,
199 },
200#ifdef CONFIG_BFIN_UART1_CTSRTS
201 { /* CTS pin -- 0 means not supported */
202 .start = GPIO_PE10,
203 .end = GPIO_PE10,
204 .flags = IORESOURCE_IO,
205 },
206 { /* RTS pin -- 0 means not supported */
207 .start = GPIO_PE9,
208 .end = GPIO_PE9,
209 .flags = IORESOURCE_IO,
Michael Hennerichdb682542008-04-24 03:18:59 +0800210 },
211#endif
212};
213
Mike Frysingera8b19882010-11-24 09:23:04 +0000214static unsigned short bfin_uart1_peripherals[] = {
Sonic Zhang6bd1fbe2009-09-09 10:46:19 +0000215 P_UART1_TX, P_UART1_RX,
216#ifdef CONFIG_BFIN_UART1_CTSRTS
217 P_UART1_RTS, P_UART1_CTS,
218#endif
219 0
220};
221
222static struct platform_device bfin_uart1_device = {
Michael Hennerichdb682542008-04-24 03:18:59 +0800223 .name = "bfin-uart",
224 .id = 1,
Sonic Zhang6bd1fbe2009-09-09 10:46:19 +0000225 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
226 .resource = bfin_uart1_resources,
227 .dev = {
228 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
229 },
Michael Hennerichdb682542008-04-24 03:18:59 +0800230};
231#endif
Sonic Zhang6bd1fbe2009-09-09 10:46:19 +0000232#ifdef CONFIG_SERIAL_BFIN_UART2
233static struct resource bfin_uart2_resources[] = {
234 {
235 .start = UART2_DLL,
236 .end = UART2_RBR+2,
237 .flags = IORESOURCE_MEM,
238 },
239 {
240 .start = IRQ_UART2_RX,
241 .end = IRQ_UART2_RX+1,
242 .flags = IORESOURCE_IRQ,
243 },
244 {
245 .start = IRQ_UART2_ERROR,
246 .end = IRQ_UART2_ERROR,
247 .flags = IORESOURCE_IRQ,
248 },
249 {
250 .start = CH_UART2_TX,
251 .end = CH_UART2_TX,
252 .flags = IORESOURCE_DMA,
253 },
254 {
255 .start = CH_UART2_RX,
256 .end = CH_UART2_RX,
257 .flags = IORESOURCE_DMA,
258 },
259};
260
Mike Frysingera8b19882010-11-24 09:23:04 +0000261static unsigned short bfin_uart2_peripherals[] = {
Sonic Zhang6bd1fbe2009-09-09 10:46:19 +0000262 P_UART2_TX, P_UART2_RX, 0
263};
264
265static struct platform_device bfin_uart2_device = {
266 .name = "bfin-uart",
267 .id = 2,
268 .num_resources = ARRAY_SIZE(bfin_uart2_resources),
269 .resource = bfin_uart2_resources,
270 .dev = {
271 .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
272 },
273};
274#endif
275#ifdef CONFIG_SERIAL_BFIN_UART3
276static struct resource bfin_uart3_resources[] = {
277 {
278 .start = UART3_DLL,
279 .end = UART3_RBR+2,
280 .flags = IORESOURCE_MEM,
281 },
282 {
283 .start = IRQ_UART3_RX,
284 .end = IRQ_UART3_RX+1,
285 .flags = IORESOURCE_IRQ,
286 },
287 {
288 .start = IRQ_UART3_ERROR,
289 .end = IRQ_UART3_ERROR,
290 .flags = IORESOURCE_IRQ,
291 },
292 {
293 .start = CH_UART3_TX,
294 .end = CH_UART3_TX,
295 .flags = IORESOURCE_DMA,
296 },
297 {
298 .start = CH_UART3_RX,
299 .end = CH_UART3_RX,
300 .flags = IORESOURCE_DMA,
301 },
302#ifdef CONFIG_BFIN_UART3_CTSRTS
303 { /* CTS pin -- 0 means not supported */
304 .start = GPIO_PB3,
305 .end = GPIO_PB3,
306 .flags = IORESOURCE_IO,
307 },
308 { /* RTS pin -- 0 means not supported */
309 .start = GPIO_PB2,
310 .end = GPIO_PB2,
311 .flags = IORESOURCE_IO,
312 },
313#endif
314};
315
Mike Frysingera8b19882010-11-24 09:23:04 +0000316static unsigned short bfin_uart3_peripherals[] = {
Sonic Zhang6bd1fbe2009-09-09 10:46:19 +0000317 P_UART3_TX, P_UART3_RX,
318#ifdef CONFIG_BFIN_UART3_CTSRTS
319 P_UART3_RTS, P_UART3_CTS,
320#endif
321 0
322};
323
324static struct platform_device bfin_uart3_device = {
325 .name = "bfin-uart",
326 .id = 3,
327 .num_resources = ARRAY_SIZE(bfin_uart3_resources),
328 .resource = bfin_uart3_resources,
329 .dev = {
330 .platform_data = &bfin_uart3_peripherals, /* Passed to driver */
331 },
332};
333#endif
334#endif
Michael Hennerichdb682542008-04-24 03:18:59 +0800335
Graf Yang5be36d22008-04-25 03:09:15 +0800336#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
Graf Yang5be36d22008-04-25 03:09:15 +0800337#ifdef CONFIG_BFIN_SIR0
Graf Yang42bd8bc2009-01-07 23:14:39 +0800338static struct resource bfin_sir0_resources[] = {
Graf Yang5be36d22008-04-25 03:09:15 +0800339 {
340 .start = 0xFFC00400,
341 .end = 0xFFC004FF,
342 .flags = IORESOURCE_MEM,
343 },
Graf Yang42bd8bc2009-01-07 23:14:39 +0800344 {
345 .start = IRQ_UART0_RX,
346 .end = IRQ_UART0_RX+1,
347 .flags = IORESOURCE_IRQ,
348 },
349 {
350 .start = CH_UART0_RX,
351 .end = CH_UART0_RX+1,
352 .flags = IORESOURCE_DMA,
353 },
354};
355static struct platform_device bfin_sir0_device = {
356 .name = "bfin_sir",
357 .id = 0,
358 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
359 .resource = bfin_sir0_resources,
360};
Graf Yang5be36d22008-04-25 03:09:15 +0800361#endif
362#ifdef CONFIG_BFIN_SIR1
Graf Yang42bd8bc2009-01-07 23:14:39 +0800363static struct resource bfin_sir1_resources[] = {
Graf Yang5be36d22008-04-25 03:09:15 +0800364 {
365 .start = 0xFFC02000,
366 .end = 0xFFC020FF,
367 .flags = IORESOURCE_MEM,
368 },
Graf Yang42bd8bc2009-01-07 23:14:39 +0800369 {
370 .start = IRQ_UART1_RX,
371 .end = IRQ_UART1_RX+1,
372 .flags = IORESOURCE_IRQ,
373 },
374 {
375 .start = CH_UART1_RX,
376 .end = CH_UART1_RX+1,
377 .flags = IORESOURCE_DMA,
378 },
379};
380static struct platform_device bfin_sir1_device = {
381 .name = "bfin_sir",
382 .id = 1,
383 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
384 .resource = bfin_sir1_resources,
385};
Graf Yang5be36d22008-04-25 03:09:15 +0800386#endif
387#ifdef CONFIG_BFIN_SIR2
Graf Yang42bd8bc2009-01-07 23:14:39 +0800388static struct resource bfin_sir2_resources[] = {
Graf Yang5be36d22008-04-25 03:09:15 +0800389 {
390 .start = 0xFFC02100,
391 .end = 0xFFC021FF,
392 .flags = IORESOURCE_MEM,
393 },
Graf Yang42bd8bc2009-01-07 23:14:39 +0800394 {
395 .start = IRQ_UART2_RX,
396 .end = IRQ_UART2_RX+1,
397 .flags = IORESOURCE_IRQ,
398 },
399 {
400 .start = CH_UART2_RX,
401 .end = CH_UART2_RX+1,
402 .flags = IORESOURCE_DMA,
403 },
404};
405static struct platform_device bfin_sir2_device = {
406 .name = "bfin_sir",
407 .id = 2,
408 .num_resources = ARRAY_SIZE(bfin_sir2_resources),
409 .resource = bfin_sir2_resources,
410};
Graf Yang5be36d22008-04-25 03:09:15 +0800411#endif
412#ifdef CONFIG_BFIN_SIR3
Graf Yang42bd8bc2009-01-07 23:14:39 +0800413static struct resource bfin_sir3_resources[] = {
Graf Yang5be36d22008-04-25 03:09:15 +0800414 {
415 .start = 0xFFC03100,
416 .end = 0xFFC031FF,
417 .flags = IORESOURCE_MEM,
418 },
Graf Yang42bd8bc2009-01-07 23:14:39 +0800419 {
420 .start = IRQ_UART3_RX,
421 .end = IRQ_UART3_RX+1,
422 .flags = IORESOURCE_IRQ,
423 },
424 {
425 .start = CH_UART3_RX,
426 .end = CH_UART3_RX+1,
427 .flags = IORESOURCE_DMA,
428 },
Graf Yang5be36d22008-04-25 03:09:15 +0800429};
Graf Yang42bd8bc2009-01-07 23:14:39 +0800430static struct platform_device bfin_sir3_device = {
Graf Yang5be36d22008-04-25 03:09:15 +0800431 .name = "bfin_sir",
Graf Yang42bd8bc2009-01-07 23:14:39 +0800432 .id = 3,
433 .num_resources = ARRAY_SIZE(bfin_sir3_resources),
434 .resource = bfin_sir3_resources,
Graf Yang5be36d22008-04-25 03:09:15 +0800435};
436#endif
Graf Yang42bd8bc2009-01-07 23:14:39 +0800437#endif
Graf Yang5be36d22008-04-25 03:09:15 +0800438
Michael Hennerichdb682542008-04-24 03:18:59 +0800439#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
Harald Krapfenbauer9c214532009-09-10 15:30:03 +0000440#include <linux/smsc911x.h>
441
Michael Hennerichdb682542008-04-24 03:18:59 +0800442static struct resource smsc911x_resources[] = {
443 {
444 .name = "smsc911x-memory",
445 .start = 0x24000000,
446 .end = 0x24000000 + 0xFF,
447 .flags = IORESOURCE_MEM,
448 },
449 {
450 .start = IRQ_PE6,
451 .end = IRQ_PE6,
452 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
453 },
454};
Harald Krapfenbauer9c214532009-09-10 15:30:03 +0000455
456static struct smsc911x_platform_config smsc911x_config = {
457 .flags = SMSC911X_USE_16BIT,
458 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
459 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
460 .phy_interface = PHY_INTERFACE_MODE_MII,
461};
462
Michael Hennerichdb682542008-04-24 03:18:59 +0800463static struct platform_device smsc911x_device = {
464 .name = "smsc911x",
465 .id = 0,
466 .num_resources = ARRAY_SIZE(smsc911x_resources),
467 .resource = smsc911x_resources,
Harald Krapfenbauer9c214532009-09-10 15:30:03 +0000468 .dev = {
469 .platform_data = &smsc911x_config,
470 },
Michael Hennerichdb682542008-04-24 03:18:59 +0800471};
472#endif
473
474#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
475static struct resource musb_resources[] = {
476 [0] = {
477 .start = 0xFFC03C00,
478 .end = 0xFFC040FF,
479 .flags = IORESOURCE_MEM,
480 },
481 [1] = { /* general IRQ */
482 .start = IRQ_USB_INT0,
483 .end = IRQ_USB_INT0,
484 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
Hema Kalliguddifcf173e2010-09-29 11:26:39 -0500485 .name = "mc"
Michael Hennerichdb682542008-04-24 03:18:59 +0800486 },
487 [2] = { /* DMA IRQ */
488 .start = IRQ_USB_DMA,
489 .end = IRQ_USB_DMA,
490 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
Hema Kalliguddifcf173e2010-09-29 11:26:39 -0500491 .name = "dma"
Michael Hennerichdb682542008-04-24 03:18:59 +0800492 },
493};
494
Bryan Wu50041ac2008-10-08 13:39:40 +0800495static struct musb_hdrc_config musb_config = {
496 .multipoint = 0,
497 .dyn_fifo = 0,
498 .soft_con = 1,
499 .dma = 1,
Bryan Wufea05da2009-01-07 23:14:39 +0800500 .num_eps = 8,
501 .dma_channels = 8,
Bryan Wu50041ac2008-10-08 13:39:40 +0800502 .gpio_vrsel = GPIO_PH6,
Cliff Cai85eb0e42010-01-22 04:02:46 +0000503 /* Some custom boards need to be active low, just set it to "0"
504 * if it is the case.
505 */
506 .gpio_vrsel_active = 1,
Bob Liu759a3f32010-09-17 11:09:57 +0000507 .clkin = 24, /* musb CLKIN in MHZ */
Bryan Wu50041ac2008-10-08 13:39:40 +0800508};
509
Michael Hennerichdb682542008-04-24 03:18:59 +0800510static struct musb_hdrc_platform_data musb_plat = {
511#if defined(CONFIG_USB_MUSB_OTG)
512 .mode = MUSB_OTG,
513#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
514 .mode = MUSB_HOST,
515#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
516 .mode = MUSB_PERIPHERAL,
517#endif
Bryan Wu50041ac2008-10-08 13:39:40 +0800518 .config = &musb_config,
Michael Hennerichdb682542008-04-24 03:18:59 +0800519};
520
521static u64 musb_dmamask = ~(u32)0;
522
523static struct platform_device musb_device = {
Felipe Balbi9cb03082010-12-02 09:21:05 +0200524 .name = "musb-blackfin",
Michael Hennerichdb682542008-04-24 03:18:59 +0800525 .id = 0,
526 .dev = {
527 .dma_mask = &musb_dmamask,
528 .coherent_dma_mask = 0xffffffff,
529 .platform_data = &musb_plat,
530 },
531 .num_resources = ARRAY_SIZE(musb_resources),
532 .resource = musb_resources,
533};
534#endif
535
Sonic Zhangdf5de262009-09-23 05:01:56 +0000536#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
537#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
538static struct resource bfin_sport0_uart_resources[] = {
539 {
540 .start = SPORT0_TCR1,
541 .end = SPORT0_MRCS3+4,
542 .flags = IORESOURCE_MEM,
543 },
544 {
545 .start = IRQ_SPORT0_RX,
546 .end = IRQ_SPORT0_RX+1,
547 .flags = IORESOURCE_IRQ,
548 },
549 {
550 .start = IRQ_SPORT0_ERROR,
551 .end = IRQ_SPORT0_ERROR,
552 .flags = IORESOURCE_IRQ,
553 },
554};
555
Mike Frysingera8b19882010-11-24 09:23:04 +0000556static unsigned short bfin_sport0_peripherals[] = {
Sonic Zhangdf5de262009-09-23 05:01:56 +0000557 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
Sonic Zhange54b6732010-11-12 02:45:38 +0000558 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
Sonic Zhangdf5de262009-09-23 05:01:56 +0000559};
560
561static struct platform_device bfin_sport0_uart_device = {
562 .name = "bfin-sport-uart",
563 .id = 0,
564 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
565 .resource = bfin_sport0_uart_resources,
566 .dev = {
567 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
568 },
569};
570#endif
571#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
572static struct resource bfin_sport1_uart_resources[] = {
573 {
574 .start = SPORT1_TCR1,
575 .end = SPORT1_MRCS3+4,
576 .flags = IORESOURCE_MEM,
577 },
578 {
579 .start = IRQ_SPORT1_RX,
580 .end = IRQ_SPORT1_RX+1,
581 .flags = IORESOURCE_IRQ,
582 },
583 {
584 .start = IRQ_SPORT1_ERROR,
585 .end = IRQ_SPORT1_ERROR,
586 .flags = IORESOURCE_IRQ,
587 },
588};
589
Mike Frysingera8b19882010-11-24 09:23:04 +0000590static unsigned short bfin_sport1_peripherals[] = {
Sonic Zhangdf5de262009-09-23 05:01:56 +0000591 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
Sonic Zhange54b6732010-11-12 02:45:38 +0000592 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
Sonic Zhangdf5de262009-09-23 05:01:56 +0000593};
594
595static struct platform_device bfin_sport1_uart_device = {
596 .name = "bfin-sport-uart",
597 .id = 1,
598 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
599 .resource = bfin_sport1_uart_resources,
600 .dev = {
601 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
602 },
603};
604#endif
605#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
606static struct resource bfin_sport2_uart_resources[] = {
607 {
608 .start = SPORT2_TCR1,
609 .end = SPORT2_MRCS3+4,
610 .flags = IORESOURCE_MEM,
611 },
612 {
613 .start = IRQ_SPORT2_RX,
614 .end = IRQ_SPORT2_RX+1,
615 .flags = IORESOURCE_IRQ,
616 },
617 {
618 .start = IRQ_SPORT2_ERROR,
619 .end = IRQ_SPORT2_ERROR,
620 .flags = IORESOURCE_IRQ,
621 },
622};
623
Mike Frysingera8b19882010-11-24 09:23:04 +0000624static unsigned short bfin_sport2_peripherals[] = {
Sonic Zhangdf5de262009-09-23 05:01:56 +0000625 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
626 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
627};
628
629static struct platform_device bfin_sport2_uart_device = {
630 .name = "bfin-sport-uart",
631 .id = 2,
632 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
633 .resource = bfin_sport2_uart_resources,
634 .dev = {
635 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
636 },
637};
638#endif
639#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
640static struct resource bfin_sport3_uart_resources[] = {
641 {
642 .start = SPORT3_TCR1,
643 .end = SPORT3_MRCS3+4,
644 .flags = IORESOURCE_MEM,
645 },
646 {
647 .start = IRQ_SPORT3_RX,
648 .end = IRQ_SPORT3_RX+1,
649 .flags = IORESOURCE_IRQ,
650 },
651 {
652 .start = IRQ_SPORT3_ERROR,
653 .end = IRQ_SPORT3_ERROR,
654 .flags = IORESOURCE_IRQ,
655 },
656};
657
Mike Frysingera8b19882010-11-24 09:23:04 +0000658static unsigned short bfin_sport3_peripherals[] = {
Sonic Zhangdf5de262009-09-23 05:01:56 +0000659 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
660 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
661};
662
663static struct platform_device bfin_sport3_uart_device = {
664 .name = "bfin-sport-uart",
665 .id = 3,
666 .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
667 .resource = bfin_sport3_uart_resources,
668 .dev = {
669 .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
670 },
671};
672#endif
673#endif
674
Michael Hennerichdb682542008-04-24 03:18:59 +0800675#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
676static struct resource bfin_atapi_resources[] = {
677 {
678 .start = 0xFFC03800,
679 .end = 0xFFC0386F,
680 .flags = IORESOURCE_MEM,
681 },
682 {
683 .start = IRQ_ATAPI_ERR,
684 .end = IRQ_ATAPI_ERR,
685 .flags = IORESOURCE_IRQ,
686 },
687};
688
689static struct platform_device bfin_atapi_device = {
690 .name = "pata-bf54x",
691 .id = -1,
692 .num_resources = ARRAY_SIZE(bfin_atapi_resources),
693 .resource = bfin_atapi_resources,
694};
695#endif
696
697#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
698static struct mtd_partition partition_info[] = {
699 {
Robin Getzaa582972008-08-05 17:47:29 +0800700 .name = "linux kernel(nand)",
Michael Hennerichdb682542008-04-24 03:18:59 +0800701 .offset = 0,
Mike Frysingerf4585a02008-10-13 14:45:21 +0800702 .size = 4 * 1024 * 1024,
Michael Hennerichdb682542008-04-24 03:18:59 +0800703 },
704 {
Robin Getzaa582972008-08-05 17:47:29 +0800705 .name = "file system(nand)",
Mike Frysingerf4585a02008-10-13 14:45:21 +0800706 .offset = 4 * 1024 * 1024,
707 .size = (256 - 4) * 1024 * 1024,
Michael Hennerichdb682542008-04-24 03:18:59 +0800708 },
709};
710
711static struct bf5xx_nand_platform bf5xx_nand_platform = {
Michael Hennerichdb682542008-04-24 03:18:59 +0800712 .data_width = NFC_NWIDTH_8,
713 .partitions = partition_info,
714 .nr_partitions = ARRAY_SIZE(partition_info),
715 .rd_dly = 3,
716 .wr_dly = 3,
717};
718
719static struct resource bf5xx_nand_resources[] = {
720 {
721 .start = 0xFFC03B00,
722 .end = 0xFFC03B4F,
723 .flags = IORESOURCE_MEM,
724 },
725 {
726 .start = CH_NFC,
727 .end = CH_NFC,
728 .flags = IORESOURCE_IRQ,
729 },
730};
731
732static struct platform_device bf5xx_nand_device = {
733 .name = "bf5xx-nand",
734 .id = 0,
735 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
736 .resource = bf5xx_nand_resources,
737 .dev = {
738 .platform_data = &bf5xx_nand_platform,
739 },
740};
741#endif
742
743#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
Mike Frysinger8d8921a2009-01-07 23:14:39 +0800744static struct bfin_sd_host bfin_sdh_data = {
745 .dma_chan = CH_SDH,
746 .irq_int0 = IRQ_SDH_MASK0,
747 .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0},
748};
749
Michael Hennerichdb682542008-04-24 03:18:59 +0800750static struct platform_device bf54x_sdh_device = {
751 .name = "bfin-sdh",
752 .id = 0,
Mike Frysinger8d8921a2009-01-07 23:14:39 +0800753 .dev = {
754 .platform_data = &bfin_sdh_data,
755 },
Michael Hennerichdb682542008-04-24 03:18:59 +0800756};
757#endif
758
Michael Hennerichbf80caf2010-04-16 13:53:23 +0000759#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
Mike Frysingera8b19882010-11-24 09:23:04 +0000760static unsigned short bfin_can_peripherals[] = {
Michael Hennerichbf80caf2010-04-16 13:53:23 +0000761 P_CAN0_RX, P_CAN0_TX, 0
762};
763
764static struct resource bfin_can_resources[] = {
765 {
766 .start = 0xFFC02A00,
767 .end = 0xFFC02FFF,
768 .flags = IORESOURCE_MEM,
769 },
770 {
771 .start = IRQ_CAN0_RX,
772 .end = IRQ_CAN0_RX,
773 .flags = IORESOURCE_IRQ,
774 },
775 {
776 .start = IRQ_CAN0_TX,
777 .end = IRQ_CAN0_TX,
778 .flags = IORESOURCE_IRQ,
779 },
780 {
781 .start = IRQ_CAN0_ERROR,
782 .end = IRQ_CAN0_ERROR,
783 .flags = IORESOURCE_IRQ,
784 },
785};
786
787static struct platform_device bfin_can_device = {
788 .name = "bfin_can",
789 .num_resources = ARRAY_SIZE(bfin_can_resources),
790 .resource = bfin_can_resources,
791 .dev = {
792 .platform_data = &bfin_can_peripherals, /* Passed to driver */
793 },
794};
795#endif
796
Mike Frysinger2de73e72008-11-18 17:48:22 +0800797#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
798static struct mtd_partition para_partitions[] = {
799 {
800 .name = "bootloader(nor)",
801 .size = 0x40000,
802 .offset = 0,
803 }, {
804 .name = "linux kernel(nor)",
Harald Krapfenbauer9c214532009-09-10 15:30:03 +0000805 .size = 0x100000,
Mike Frysinger2de73e72008-11-18 17:48:22 +0800806 .offset = MTDPART_OFS_APPEND,
807 }, {
808 .name = "file system(nor)",
809 .size = MTDPART_SIZ_FULL,
810 .offset = MTDPART_OFS_APPEND,
811 }
812};
813
814static struct physmap_flash_data para_flash_data = {
815 .width = 2,
816 .parts = para_partitions,
817 .nr_parts = ARRAY_SIZE(para_partitions),
818};
819
820static struct resource para_flash_resource = {
821 .start = 0x20000000,
822 .end = 0x207fffff,
823 .flags = IORESOURCE_MEM,
824};
825
826static struct platform_device para_flash_device = {
827 .name = "physmap-flash",
828 .id = 0,
829 .dev = {
830 .platform_data = &para_flash_data,
831 },
832 .num_resources = 1,
833 .resource = &para_flash_resource,
834};
835#endif
836
Michael Hennerichdb682542008-04-24 03:18:59 +0800837#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
838/* all SPI peripherals info goes here */
839#if defined(CONFIG_MTD_M25P80) \
840 || defined(CONFIG_MTD_M25P80_MODULE)
841/* SPI flash chip (m25p16) */
842static struct mtd_partition bfin_spi_flash_partitions[] = {
843 {
Robin Getzaa582972008-08-05 17:47:29 +0800844 .name = "bootloader(spi)",
Michael Hennerichdb682542008-04-24 03:18:59 +0800845 .size = 0x00040000,
846 .offset = 0,
847 .mask_flags = MTD_CAP_ROM
848 }, {
Robin Getzaa582972008-08-05 17:47:29 +0800849 .name = "linux kernel(spi)",
Michael Hennerichdb682542008-04-24 03:18:59 +0800850 .size = 0x1c0000,
851 .offset = 0x40000
852 }
853};
854
855static struct flash_platform_data bfin_spi_flash_data = {
856 .name = "m25p80",
857 .parts = bfin_spi_flash_partitions,
858 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
859 .type = "m25p16",
860};
861
862static struct bfin5xx_spi_chip spi_flash_chip_info = {
863 .enable_dma = 0, /* use dma transfer with this chip*/
864 .bits_per_word = 8,
Michael Hennerichdb682542008-04-24 03:18:59 +0800865};
866#endif
867
868#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
869static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
Michael Hennerichdb682542008-04-24 03:18:59 +0800870 .enable_dma = 0,
871 .bits_per_word = 16,
872};
873
874static const struct ad7877_platform_data bfin_ad7877_ts_info = {
875 .model = 7877,
876 .vref_delay_usecs = 50, /* internal, no capacitor */
877 .x_plate_ohms = 419,
878 .y_plate_ohms = 486,
879 .pressure_max = 1000,
880 .pressure_min = 0,
881 .stopacq_polarity = 1,
882 .first_conversion_delay = 3,
883 .acquisition_time = 1,
884 .averaging = 1,
885 .pen_down_acc_interval = 1,
886};
887#endif
888
889#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
890static struct bfin5xx_spi_chip spidev_chip_info = {
891 .enable_dma = 0,
892 .bits_per_word = 8,
893};
894#endif
895
896static struct spi_board_info bf54x_spi_board_info[] __initdata = {
897#if defined(CONFIG_MTD_M25P80) \
898 || defined(CONFIG_MTD_M25P80_MODULE)
899 {
900 /* the modalias must be the same as spi device driver name */
901 .modalias = "m25p80", /* Name of spi_driver for this device */
902 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
903 .bus_num = 0, /* Framework bus number */
904 .chip_select = 1, /* SPI_SSEL1*/
905 .platform_data = &bfin_spi_flash_data,
906 .controller_data = &spi_flash_chip_info,
907 .mode = SPI_MODE_3,
908 },
909#endif
910#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
911{
912 .modalias = "ad7877",
913 .platform_data = &bfin_ad7877_ts_info,
914 .irq = IRQ_PJ11,
915 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
916 .bus_num = 0,
917 .chip_select = 2,
918 .controller_data = &spi_ad7877_chip_info,
919},
920#endif
921#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
922 {
923 .modalias = "spidev",
924 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
925 .bus_num = 0,
926 .chip_select = 1,
927 .controller_data = &spidev_chip_info,
928 },
929#endif
930};
931
932/* SPI (0) */
933static struct resource bfin_spi0_resource[] = {
934 [0] = {
935 .start = SPI0_REGBASE,
936 .end = SPI0_REGBASE + 0xFF,
937 .flags = IORESOURCE_MEM,
938 },
939 [1] = {
940 .start = CH_SPI0,
941 .end = CH_SPI0,
Yi Li53122692009-06-05 12:11:11 +0000942 .flags = IORESOURCE_DMA,
943 },
944 [2] = {
945 .start = IRQ_SPI0,
946 .end = IRQ_SPI0,
Michael Hennerichdb682542008-04-24 03:18:59 +0800947 .flags = IORESOURCE_IRQ,
948 }
949};
950
951/* SPI (1) */
952static struct resource bfin_spi1_resource[] = {
953 [0] = {
954 .start = SPI1_REGBASE,
955 .end = SPI1_REGBASE + 0xFF,
956 .flags = IORESOURCE_MEM,
957 },
958 [1] = {
959 .start = CH_SPI1,
960 .end = CH_SPI1,
Yi Li53122692009-06-05 12:11:11 +0000961 .flags = IORESOURCE_DMA,
962 },
963 [2] = {
964 .start = IRQ_SPI1,
965 .end = IRQ_SPI1,
Michael Hennerichdb682542008-04-24 03:18:59 +0800966 .flags = IORESOURCE_IRQ,
967 }
968};
969
970/* SPI controller data */
971static struct bfin5xx_spi_master bf54x_spi_master_info0 = {
Mike Frysingerc5af5452010-06-16 19:29:51 +0000972 .num_chipselect = 4,
Michael Hennerichdb682542008-04-24 03:18:59 +0800973 .enable_dma = 1, /* master has the ability to do dma transfer */
974 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
975};
976
977static struct platform_device bf54x_spi_master0 = {
978 .name = "bfin-spi",
979 .id = 0, /* Bus number */
980 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
981 .resource = bfin_spi0_resource,
982 .dev = {
983 .platform_data = &bf54x_spi_master_info0, /* Passed to driver */
984 },
985};
986
987static struct bfin5xx_spi_master bf54x_spi_master_info1 = {
Mike Frysingerc5af5452010-06-16 19:29:51 +0000988 .num_chipselect = 4,
Michael Hennerichdb682542008-04-24 03:18:59 +0800989 .enable_dma = 1, /* master has the ability to do dma transfer */
990 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
991};
992
993static struct platform_device bf54x_spi_master1 = {
994 .name = "bfin-spi",
995 .id = 1, /* Bus number */
996 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
997 .resource = bfin_spi1_resource,
998 .dev = {
999 .platform_data = &bf54x_spi_master_info1, /* Passed to driver */
1000 },
1001};
1002#endif /* spi master and devices */
1003
1004#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
1005static struct resource bfin_twi0_resource[] = {
1006 [0] = {
1007 .start = TWI0_REGBASE,
1008 .end = TWI0_REGBASE + 0xFF,
1009 .flags = IORESOURCE_MEM,
1010 },
1011 [1] = {
1012 .start = IRQ_TWI0,
1013 .end = IRQ_TWI0,
1014 .flags = IORESOURCE_IRQ,
1015 },
1016};
1017
1018static struct platform_device i2c_bfin_twi0_device = {
1019 .name = "i2c-bfin-twi",
1020 .id = 0,
1021 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
1022 .resource = bfin_twi0_resource,
1023};
1024
1025#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
1026static struct resource bfin_twi1_resource[] = {
1027 [0] = {
1028 .start = TWI1_REGBASE,
1029 .end = TWI1_REGBASE + 0xFF,
1030 .flags = IORESOURCE_MEM,
1031 },
1032 [1] = {
1033 .start = IRQ_TWI1,
1034 .end = IRQ_TWI1,
1035 .flags = IORESOURCE_IRQ,
1036 },
1037};
1038
1039static struct platform_device i2c_bfin_twi1_device = {
1040 .name = "i2c-bfin-twi",
1041 .id = 1,
1042 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
1043 .resource = bfin_twi1_resource,
1044};
1045#endif
1046#endif
1047
1048#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1049#include <linux/gpio_keys.h>
1050
1051static struct gpio_keys_button bfin_gpio_keys_table[] = {
1052 {BTN_0, GPIO_PH7, 1, "gpio-keys: BTN0"},
1053};
1054
1055static struct gpio_keys_platform_data bfin_gpio_keys_data = {
1056 .buttons = bfin_gpio_keys_table,
1057 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
1058};
1059
1060static struct platform_device bfin_device_gpiokeys = {
1061 .name = "gpio-keys",
1062 .dev = {
1063 .platform_data = &bfin_gpio_keys_data,
1064 },
1065};
1066#endif
1067
Michael Hennerich14b03202008-05-07 11:41:26 +08001068static const unsigned int cclk_vlev_datasheet[] =
1069{
1070/*
1071 * Internal VLEV BF54XSBBC1533
1072 ****temporarily using these values until data sheet is updated
1073 */
1074 VRPAIR(VLEV_085, 150000000),
1075 VRPAIR(VLEV_090, 250000000),
1076 VRPAIR(VLEV_110, 276000000),
1077 VRPAIR(VLEV_115, 301000000),
1078 VRPAIR(VLEV_120, 525000000),
1079 VRPAIR(VLEV_125, 550000000),
1080 VRPAIR(VLEV_130, 600000000),
1081};
1082
1083static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
1084 .tuple_tab = cclk_vlev_datasheet,
1085 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
1086 .vr_settling_time = 25 /* us */,
1087};
1088
1089static struct platform_device bfin_dpmc = {
1090 .name = "bfin dpmc",
1091 .dev = {
1092 .platform_data = &bfin_dmpc_vreg_data,
1093 },
1094};
1095
Michael Hennerichdb682542008-04-24 03:18:59 +08001096static struct platform_device *cm_bf548_devices[] __initdata = {
Michael Hennerich14b03202008-05-07 11:41:26 +08001097
1098 &bfin_dpmc,
1099
Michael Hennerichdb682542008-04-24 03:18:59 +08001100#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
1101 &rtc_device,
1102#endif
1103
1104#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
Sonic Zhang6bd1fbe2009-09-09 10:46:19 +00001105#ifdef CONFIG_SERIAL_BFIN_UART0
1106 &bfin_uart0_device,
1107#endif
1108#ifdef CONFIG_SERIAL_BFIN_UART1
1109 &bfin_uart1_device,
1110#endif
1111#ifdef CONFIG_SERIAL_BFIN_UART2
1112 &bfin_uart2_device,
1113#endif
1114#ifdef CONFIG_SERIAL_BFIN_UART3
1115 &bfin_uart3_device,
1116#endif
Michael Hennerichdb682542008-04-24 03:18:59 +08001117#endif
1118
Graf Yang5be36d22008-04-25 03:09:15 +08001119#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
Graf Yang42bd8bc2009-01-07 23:14:39 +08001120#ifdef CONFIG_BFIN_SIR0
1121 &bfin_sir0_device,
1122#endif
1123#ifdef CONFIG_BFIN_SIR1
1124 &bfin_sir1_device,
1125#endif
1126#ifdef CONFIG_BFIN_SIR2
1127 &bfin_sir2_device,
1128#endif
1129#ifdef CONFIG_BFIN_SIR3
1130 &bfin_sir3_device,
1131#endif
Graf Yang5be36d22008-04-25 03:09:15 +08001132#endif
1133
Michael Hennerichdb682542008-04-24 03:18:59 +08001134#if defined(CONFIG_FB_BF54X_LQ043) || defined(CONFIG_FB_BF54X_LQ043_MODULE)
1135 &bf54x_lq043_device,
1136#endif
1137
1138#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
1139 &smsc911x_device,
1140#endif
1141
1142#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
1143 &musb_device,
1144#endif
1145
Sonic Zhangdf5de262009-09-23 05:01:56 +00001146#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
1147#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1148 &bfin_sport0_uart_device,
1149#endif
1150#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1151 &bfin_sport1_uart_device,
1152#endif
1153#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1154 &bfin_sport2_uart_device,
1155#endif
1156#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
1157 &bfin_sport3_uart_device,
1158#endif
1159#endif
1160
Michael Hennerichdb682542008-04-24 03:18:59 +08001161#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
1162 &bfin_atapi_device,
1163#endif
1164
1165#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
1166 &bf5xx_nand_device,
1167#endif
1168
1169#if defined(CONFIG_SDH_BFIN) || defined(CONFIG_SDH_BFIN_MODULE)
1170 &bf54x_sdh_device,
1171#endif
1172
1173#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1174 &bf54x_spi_master0,
1175 &bf54x_spi_master1,
1176#endif
1177
1178#if defined(CONFIG_KEYBOARD_BFIN) || defined(CONFIG_KEYBOARD_BFIN_MODULE)
1179 &bf54x_kpad_device,
1180#endif
1181
1182#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
Mike Frysinger10a88a22008-11-18 17:48:22 +08001183 &i2c_bfin_twi0_device,
Michael Hennerichdb682542008-04-24 03:18:59 +08001184#if !defined(CONFIG_BF542)
1185 &i2c_bfin_twi1_device,
1186#endif
1187#endif
1188
1189#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1190 &bfin_device_gpiokeys,
1191#endif
Mike Frysinger2de73e72008-11-18 17:48:22 +08001192
1193#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
1194 &para_flash_device,
1195#endif
Michael Hennerichbf80caf2010-04-16 13:53:23 +00001196
1197#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1198 &bfin_can_device,
1199#endif
1200
Michael Hennerichdb682542008-04-24 03:18:59 +08001201};
1202
1203static int __init cm_bf548_init(void)
1204{
Michael Hennerichf086f232008-05-20 16:42:39 +08001205 printk(KERN_INFO "%s(): registering device resources\n", __func__);
Michael Hennerichdb682542008-04-24 03:18:59 +08001206 platform_add_devices(cm_bf548_devices, ARRAY_SIZE(cm_bf548_devices));
1207
1208#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
1209 spi_register_board_info(bf54x_spi_board_info,
1210 ARRAY_SIZE(bf54x_spi_board_info));
1211#endif
1212
1213 return 0;
1214}
1215
1216arch_initcall(cm_bf548_init);
Sonic Zhangc13ce9f2009-09-23 09:37:46 +00001217
1218static struct platform_device *cm_bf548_early_devices[] __initdata = {
1219#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1220#ifdef CONFIG_SERIAL_BFIN_UART0
1221 &bfin_uart0_device,
1222#endif
1223#ifdef CONFIG_SERIAL_BFIN_UART1
1224 &bfin_uart1_device,
1225#endif
1226#ifdef CONFIG_SERIAL_BFIN_UART2
1227 &bfin_uart2_device,
1228#endif
1229#ifdef CONFIG_SERIAL_BFIN_UART3
1230 &bfin_uart3_device,
1231#endif
1232#endif
1233
1234#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
1235#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
1236 &bfin_sport0_uart_device,
1237#endif
1238#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
1239 &bfin_sport1_uart_device,
1240#endif
1241#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
1242 &bfin_sport2_uart_device,
1243#endif
1244#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
1245 &bfin_sport3_uart_device,
1246#endif
1247#endif
1248};
1249
1250void __init native_machine_early_platform_add_devices(void)
1251{
1252 printk(KERN_INFO "register early platform devices\n");
1253 early_platform_add_devices(cm_bf548_early_devices,
1254 ARRAY_SIZE(cm_bf548_early_devices));
1255}