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Chris Leechc13c8262006-05-23 17:18:44 -07001#
2# DMA engine configuration
3#
4
Shannon Nelson2ed6dc32007-10-16 01:27:42 -07005menuconfig DMADEVICES
Haavard Skinnemoen6d4f5872007-11-28 16:21:43 -08006 bool "DMA Engine support"
Dan Williamsdaf42192009-07-01 16:12:53 -07007 depends on HAS_DMA
Shannon Nelson2ed6dc32007-10-16 01:27:42 -07008 help
Haavard Skinnemoen6d4f5872007-11-28 16:21:43 -08009 DMA engines can do asynchronous data transfers without
10 involving the host CPU. Currently, this framework can be
11 used to offload memory copies in the network stack and
Dan Williams9c402f42008-06-27 01:21:11 -070012 RAID operations in the MD driver. This menu only presents
13 DMA Device drivers supported by the configured arch, it may
14 be empty in some cases.
Chris Leechc13c8262006-05-23 17:18:44 -070015
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070016if DMADEVICES
Chris Leechdb217332006-06-17 21:24:58 -070017
Chris Leech0bbd5f42006-05-23 17:35:34 -070018comment "DMA Devices"
19
20config INTEL_IOATDMA
21 tristate "Intel I/OAT DMA support"
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070022 depends on PCI && X86
23 select DMA_ENGINE
24 select DCA
25 help
26 Enable support for the Intel(R) I/OAT DMA engine present
27 in recent Intel Xeon chipsets.
28
29 Say Y here if you have such a chipset.
30
31 If unsure, say N.
Dan Williamsc2110922007-01-02 13:52:26 -070032
33config INTEL_IOP_ADMA
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070034 tristate "Intel IOP ADMA support"
35 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070036 select DMA_ENGINE
37 help
38 Enable support for the Intel(R) IOP Series RAID engines.
Dan Williamsc2110922007-01-02 13:52:26 -070039
Haavard Skinnemoen3bfb1d22008-07-08 11:59:42 -070040config DW_DMAC
41 tristate "Synopsys DesignWare AHB DMA support"
42 depends on AVR32
43 select DMA_ENGINE
44 default y if CPU_AT32AP7000
45 help
46 Support the Synopsys DesignWare AHB DMA controller. This
47 can be integrated in chips such as the Atmel AT32ap7000.
48
Nicolas Ferredc78baa2009-07-03 19:24:33 +020049config AT_HDMAC
50 tristate "Atmel AHB DMA support"
51 depends on ARCH_AT91SAM9RL
52 select DMA_ENGINE
53 help
54 Support the Atmel AHB DMA controller. This can be integrated in
55 chips such as the Atmel AT91SAM9RL.
56
Zhang Wei173acc72008-03-01 07:42:48 -070057config FSL_DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -070058 tristate "Freescale Elo and Elo Plus DMA support"
59 depends on FSL_SOC
Zhang Wei173acc72008-03-01 07:42:48 -070060 select DMA_ENGINE
61 ---help---
Timur Tabi77cd62e2008-09-26 17:00:11 -070062 Enable support for the Freescale Elo and Elo Plus DMA controllers.
63 The Elo is the DMA controller on some 82xx and 83xx parts, and the
64 Elo Plus is the DMA controller on 85xx and 86xx parts.
Zhang Wei173acc72008-03-01 07:42:48 -070065
Saeed Bisharaff7b0472008-07-08 11:58:36 -070066config MV_XOR
67 bool "Marvell XOR engine support"
68 depends on PLAT_ORION
Saeed Bisharaff7b0472008-07-08 11:58:36 -070069 select DMA_ENGINE
70 ---help---
71 Enable support for the Marvell XOR engine.
72
Guennadi Liakhovetski5296b562009-01-19 15:36:21 -070073config MX3_IPU
74 bool "MX3x Image Processing Unit support"
75 depends on ARCH_MX3
76 select DMA_ENGINE
77 default y
78 help
79 If you plan to use the Image Processing unit in the i.MX3x, say
80 Y here. If unsure, select Y.
81
82config MX3_IPU_IRQS
83 int "Number of dynamically mapped interrupts for IPU"
84 depends on MX3_IPU
85 range 2 137
86 default 4
87 help
88 Out of 137 interrupt sources on i.MX31 IPU only very few are used.
89 To avoid bloating the irq_desc[] array we allocate a sufficient
90 number of IRQ slots and map them dynamically to specific sources.
91
Shannon Nelson2ed6dc32007-10-16 01:27:42 -070092config DMA_ENGINE
93 bool
94
95comment "DMA Clients"
96 depends on DMA_ENGINE
97
98config NET_DMA
99 bool "Network: TCP receive copy offload"
100 depends on DMA_ENGINE && NET
Dan Williams9c402f42008-06-27 01:21:11 -0700101 default (INTEL_IOATDMA || FSL_DMA)
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700102 help
103 This enables the use of DMA engines in the network stack to
104 offload receive copy-to-user operations, freeing CPU cycles.
Dan Williams9c402f42008-06-27 01:21:11 -0700105
106 Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
107 say N.
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700108
Dan Williams729b5d12009-03-25 09:13:25 -0700109config ASYNC_TX_DMA
110 bool "Async_tx: Offload support for the async_tx api"
Dan Williamsdaf42192009-07-01 16:12:53 -0700111 depends on DMA_ENGINE && !HIGHMEM64G
Dan Williams729b5d12009-03-25 09:13:25 -0700112 help
113 This allows the async_tx api to take advantage of offload engines for
114 memcpy, memset, xor, and raid6 p+q operations. If your platform has
115 a dma engine that can perform raid operations and you have enabled
116 MD_RAID456 say Y.
117
118 If unsure, say N.
119
Haavard Skinnemoen4a776f02008-07-08 11:58:45 -0700120config DMATEST
121 tristate "DMA Test client"
122 depends on DMA_ENGINE
123 help
124 Simple DMA test client. Say N unless you're debugging a
125 DMA Device driver.
126
Shannon Nelson2ed6dc32007-10-16 01:27:42 -0700127endif