blob: 156ae347c617eb4b7148f216a3cf46c940094463 [file] [log] [blame]
Sujithf1dc5602008-10-29 10:16:30 +05301/*
Sujithcee075a2009-03-13 09:07:23 +05302 * Copyright (c) 2008-2009 Atheros Communications Inc.
Sujithf1dc5602008-10-29 10:16:30 +05303 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -070017#include "hw.h"
Felix Fietkau641d9922010-04-15 17:38:49 -040018#include "hw-ops.h"
Luis R. Rodriguez8fe65362010-04-15 17:38:14 -040019#include "ar9002_phy.h"
Sujithf1dc5602008-10-29 10:16:30 +053020
Sujithf1dc5602008-10-29 10:16:30 +053021/* We can tune this as we go by monitoring really low values */
22#define ATH9K_NF_TOO_LOW -60
Vivek Natarajan53bc7aa2010-04-05 14:48:04 +053023#define AR9285_CLCAL_REDO_THRESH 1
Sujithf1dc5602008-10-29 10:16:30 +053024
25/* AR5416 may return very high value (like -31 dBm), in those cases the nf
26 * is incorrect and we should use the static NF value. Later we can try to
27 * find out why they are reporting these values */
28
Sujithcbe61d82009-02-09 13:27:12 +053029static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
Sujithf1dc5602008-10-29 10:16:30 +053030{
31 if (nf > ATH9K_NF_TOO_LOW) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -070032 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
33 "noise floor value detected (%d) is "
34 "lower than what we think is a "
35 "reasonable value (%d)\n",
36 nf, ATH9K_NF_TOO_LOW);
Sujithf1dc5602008-10-29 10:16:30 +053037 return false;
38 }
39 return true;
40}
41
42static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
43{
44 int16_t nfval;
45 int16_t sort[ATH9K_NF_CAL_HIST_MAX];
46 int i, j;
47
48 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
49 sort[i] = nfCalBuffer[i];
50
51 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
52 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
53 if (sort[j] > sort[j - 1]) {
54 nfval = sort[j];
55 sort[j] = sort[j - 1];
56 sort[j - 1] = nfval;
57 }
58 }
59 }
60 nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
61
62 return nfval;
63}
64
65static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h,
66 int16_t *nfarray)
67{
68 int i;
69
70 for (i = 0; i < NUM_NF_READINGS; i++) {
71 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
72
73 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
74 h[i].currIndex = 0;
75
76 if (h[i].invalidNFcount > 0) {
77 if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE ||
78 nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
79 h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX;
80 } else {
81 h[i].invalidNFcount--;
82 h[i].privNF = nfarray[i];
83 }
84 } else {
85 h[i].privNF =
86 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
87 }
88 }
89 return;
90}
91
Sujithcbe61d82009-02-09 13:27:12 +053092static bool getNoiseFloorThresh(struct ath_hw *ah,
Luis R. Rodriguez76061ab2008-12-23 15:58:41 -080093 enum ieee80211_band band,
Sujithf1dc5602008-10-29 10:16:30 +053094 int16_t *nft)
95{
Luis R. Rodriguez76061ab2008-12-23 15:58:41 -080096 switch (band) {
97 case IEEE80211_BAND_5GHZ:
Sujithf74df6f2009-02-09 13:27:24 +053098 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5);
Sujithf1dc5602008-10-29 10:16:30 +053099 break;
Luis R. Rodriguez76061ab2008-12-23 15:58:41 -0800100 case IEEE80211_BAND_2GHZ:
Sujithf74df6f2009-02-09 13:27:24 +0530101 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2);
Sujithf1dc5602008-10-29 10:16:30 +0530102 break;
103 default:
Luis R. Rodriguez76061ab2008-12-23 15:58:41 -0800104 BUG_ON(1);
Sujithf1dc5602008-10-29 10:16:30 +0530105 return false;
106 }
107
108 return true;
109}
110
Sujithcbe61d82009-02-09 13:27:12 +0530111static void ath9k_hw_setup_calibration(struct ath_hw *ah,
Sujithcbfe9462009-04-13 21:56:56 +0530112 struct ath9k_cal_list *currCal)
Sujithf1dc5602008-10-29 10:16:30 +0530113{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700114 struct ath_common *common = ath9k_hw_common(ah);
115
Sujithf1dc5602008-10-29 10:16:30 +0530116 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
117 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
118 currCal->calData->calCountMax);
119
120 switch (currCal->calData->calType) {
121 case IQ_MISMATCH_CAL:
122 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700123 ath_print(common, ATH_DBG_CALIBRATE,
124 "starting IQ Mismatch Calibration\n");
Sujithf1dc5602008-10-29 10:16:30 +0530125 break;
126 case ADC_GAIN_CAL:
127 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700128 ath_print(common, ATH_DBG_CALIBRATE,
129 "starting ADC Gain Calibration\n");
Sujithf1dc5602008-10-29 10:16:30 +0530130 break;
131 case ADC_DC_CAL:
132 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700133 ath_print(common, ATH_DBG_CALIBRATE,
134 "starting ADC DC Calibration\n");
Sujithf1dc5602008-10-29 10:16:30 +0530135 break;
136 case ADC_DC_INIT_CAL:
137 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700138 ath_print(common, ATH_DBG_CALIBRATE,
139 "starting Init ADC DC Calibration\n");
Sujithf1dc5602008-10-29 10:16:30 +0530140 break;
141 }
142
143 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
144 AR_PHY_TIMING_CTRL4_DO_CAL);
145}
146
Sujithcbe61d82009-02-09 13:27:12 +0530147static void ath9k_hw_reset_calibration(struct ath_hw *ah,
Sujithcbfe9462009-04-13 21:56:56 +0530148 struct ath9k_cal_list *currCal)
Sujithf1dc5602008-10-29 10:16:30 +0530149{
Sujithf1dc5602008-10-29 10:16:30 +0530150 int i;
151
152 ath9k_hw_setup_calibration(ah, currCal);
153
154 currCal->calState = CAL_RUNNING;
155
156 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
Sujith2660b812009-02-09 13:27:26 +0530157 ah->meas0.sign[i] = 0;
158 ah->meas1.sign[i] = 0;
159 ah->meas2.sign[i] = 0;
160 ah->meas3.sign[i] = 0;
Sujithf1dc5602008-10-29 10:16:30 +0530161 }
162
Sujith2660b812009-02-09 13:27:26 +0530163 ah->cal_samples = 0;
Sujithf1dc5602008-10-29 10:16:30 +0530164}
165
Sujith379f0442009-04-13 21:56:48 +0530166static bool ath9k_hw_per_calibration(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530167 struct ath9k_channel *ichan,
168 u8 rxchainmask,
Sujithcbfe9462009-04-13 21:56:56 +0530169 struct ath9k_cal_list *currCal)
Sujithf1dc5602008-10-29 10:16:30 +0530170{
Sujith379f0442009-04-13 21:56:48 +0530171 bool iscaldone = false;
Sujithf1dc5602008-10-29 10:16:30 +0530172
173 if (currCal->calState == CAL_RUNNING) {
174 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
175 AR_PHY_TIMING_CTRL4_DO_CAL)) {
176
177 currCal->calData->calCollect(ah);
Sujith2660b812009-02-09 13:27:26 +0530178 ah->cal_samples++;
Sujithf1dc5602008-10-29 10:16:30 +0530179
Sujith2660b812009-02-09 13:27:26 +0530180 if (ah->cal_samples >= currCal->calData->calNumSamples) {
Sujithf1dc5602008-10-29 10:16:30 +0530181 int i, numChains = 0;
182 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
183 if (rxchainmask & (1 << i))
184 numChains++;
185 }
186
187 currCal->calData->calPostProc(ah, numChains);
188 ichan->CalValid |= currCal->calData->calType;
189 currCal->calState = CAL_DONE;
Sujith379f0442009-04-13 21:56:48 +0530190 iscaldone = true;
Sujithf1dc5602008-10-29 10:16:30 +0530191 } else {
192 ath9k_hw_setup_calibration(ah, currCal);
193 }
194 }
195 } else if (!(ichan->CalValid & currCal->calData->calType)) {
196 ath9k_hw_reset_calibration(ah, currCal);
197 }
Sujith379f0442009-04-13 21:56:48 +0530198
199 return iscaldone;
Sujithf1dc5602008-10-29 10:16:30 +0530200}
201
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800202/* Assumes you are talking about the currently configured channel */
Sujithcbe61d82009-02-09 13:27:12 +0530203static bool ath9k_hw_iscal_supported(struct ath_hw *ah,
Sujithcbfe9462009-04-13 21:56:56 +0530204 enum ath9k_cal_types calType)
Sujithf1dc5602008-10-29 10:16:30 +0530205{
Luis R. Rodriguezb002a4a2009-09-13 00:03:27 -0700206 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
Sujithf1dc5602008-10-29 10:16:30 +0530207
Sujith2660b812009-02-09 13:27:26 +0530208 switch (calType & ah->supp_cals) {
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800209 case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */
210 return true;
Sujithf1dc5602008-10-29 10:16:30 +0530211 case ADC_GAIN_CAL:
212 case ADC_DC_CAL:
Sujitha451aa62009-04-13 21:56:43 +0530213 if (!(conf->channel->band == IEEE80211_BAND_2GHZ &&
214 conf_is_ht20(conf)))
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800215 return true;
Sujithf1dc5602008-10-29 10:16:30 +0530216 break;
217 }
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800218 return false;
Sujithf1dc5602008-10-29 10:16:30 +0530219}
220
Sujithcbe61d82009-02-09 13:27:12 +0530221static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530222{
Sujithf1dc5602008-10-29 10:16:30 +0530223 int i;
224
225 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
Sujith2660b812009-02-09 13:27:26 +0530226 ah->totalPowerMeasI[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530227 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
Sujith2660b812009-02-09 13:27:26 +0530228 ah->totalPowerMeasQ[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530229 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
Sujith2660b812009-02-09 13:27:26 +0530230 ah->totalIqCorrMeas[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530231 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700232 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
233 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
234 ah->cal_samples, i, ah->totalPowerMeasI[i],
235 ah->totalPowerMeasQ[i],
236 ah->totalIqCorrMeas[i]);
Sujithf1dc5602008-10-29 10:16:30 +0530237 }
238}
239
Sujithcbe61d82009-02-09 13:27:12 +0530240static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530241{
Sujithf1dc5602008-10-29 10:16:30 +0530242 int i;
243
244 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
Sujith2660b812009-02-09 13:27:26 +0530245 ah->totalAdcIOddPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530246 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
Sujith2660b812009-02-09 13:27:26 +0530247 ah->totalAdcIEvenPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530248 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
Sujith2660b812009-02-09 13:27:26 +0530249 ah->totalAdcQOddPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530250 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
Sujith2660b812009-02-09 13:27:26 +0530251 ah->totalAdcQEvenPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530252 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
253
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700254 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
255 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
256 "oddq=0x%08x; evenq=0x%08x;\n",
257 ah->cal_samples, i,
258 ah->totalAdcIOddPhase[i],
259 ah->totalAdcIEvenPhase[i],
260 ah->totalAdcQOddPhase[i],
261 ah->totalAdcQEvenPhase[i]);
Sujithf1dc5602008-10-29 10:16:30 +0530262 }
263}
264
Sujithcbe61d82009-02-09 13:27:12 +0530265static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530266{
Sujithf1dc5602008-10-29 10:16:30 +0530267 int i;
268
269 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
Sujith2660b812009-02-09 13:27:26 +0530270 ah->totalAdcDcOffsetIOddPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530271 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
Sujith2660b812009-02-09 13:27:26 +0530272 ah->totalAdcDcOffsetIEvenPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530273 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
Sujith2660b812009-02-09 13:27:26 +0530274 ah->totalAdcDcOffsetQOddPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530275 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
Sujith2660b812009-02-09 13:27:26 +0530276 ah->totalAdcDcOffsetQEvenPhase[i] +=
Sujithf1dc5602008-10-29 10:16:30 +0530277 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
278
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700279 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
280 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
281 "oddq=0x%08x; evenq=0x%08x;\n",
282 ah->cal_samples, i,
283 ah->totalAdcDcOffsetIOddPhase[i],
284 ah->totalAdcDcOffsetIEvenPhase[i],
285 ah->totalAdcDcOffsetQOddPhase[i],
286 ah->totalAdcDcOffsetQEvenPhase[i]);
Sujithf1dc5602008-10-29 10:16:30 +0530287 }
288}
289
Sujithcbe61d82009-02-09 13:27:12 +0530290static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
Sujithf1dc5602008-10-29 10:16:30 +0530291{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700292 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530293 u32 powerMeasQ, powerMeasI, iqCorrMeas;
294 u32 qCoffDenom, iCoffDenom;
295 int32_t qCoff, iCoff;
296 int iqCorrNeg, i;
297
298 for (i = 0; i < numChains; i++) {
Sujith2660b812009-02-09 13:27:26 +0530299 powerMeasI = ah->totalPowerMeasI[i];
300 powerMeasQ = ah->totalPowerMeasQ[i];
301 iqCorrMeas = ah->totalIqCorrMeas[i];
Sujithf1dc5602008-10-29 10:16:30 +0530302
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700303 ath_print(common, ATH_DBG_CALIBRATE,
304 "Starting IQ Cal and Correction for Chain %d\n",
305 i);
Sujithf1dc5602008-10-29 10:16:30 +0530306
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700307 ath_print(common, ATH_DBG_CALIBRATE,
308 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
309 i, ah->totalIqCorrMeas[i]);
Sujithf1dc5602008-10-29 10:16:30 +0530310
311 iqCorrNeg = 0;
312
313 if (iqCorrMeas > 0x80000000) {
314 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
315 iqCorrNeg = 1;
316 }
317
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700318 ath_print(common, ATH_DBG_CALIBRATE,
319 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
320 ath_print(common, ATH_DBG_CALIBRATE,
321 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
322 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
323 iqCorrNeg);
Sujithf1dc5602008-10-29 10:16:30 +0530324
325 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
326 qCoffDenom = powerMeasQ / 64;
327
Vivek Natarajan0b98eaa2009-09-18 15:03:42 +0530328 if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
329 (qCoffDenom != 0)) {
Sujithf1dc5602008-10-29 10:16:30 +0530330 iCoff = iqCorrMeas / iCoffDenom;
331 qCoff = powerMeasI / qCoffDenom - 64;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700332 ath_print(common, ATH_DBG_CALIBRATE,
333 "Chn %d iCoff = 0x%08x\n", i, iCoff);
334 ath_print(common, ATH_DBG_CALIBRATE,
335 "Chn %d qCoff = 0x%08x\n", i, qCoff);
Sujithf1dc5602008-10-29 10:16:30 +0530336
337 iCoff = iCoff & 0x3f;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700338 ath_print(common, ATH_DBG_CALIBRATE,
339 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
Sujithf1dc5602008-10-29 10:16:30 +0530340 if (iqCorrNeg == 0x0)
341 iCoff = 0x40 - iCoff;
342
343 if (qCoff > 15)
344 qCoff = 15;
345 else if (qCoff <= -16)
346 qCoff = 16;
347
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700348 ath_print(common, ATH_DBG_CALIBRATE,
349 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
350 i, iCoff, qCoff);
Sujithf1dc5602008-10-29 10:16:30 +0530351
352 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
353 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
354 iCoff);
355 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
356 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
357 qCoff);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700358 ath_print(common, ATH_DBG_CALIBRATE,
359 "IQ Cal and Correction done for Chain %d\n",
360 i);
Sujithf1dc5602008-10-29 10:16:30 +0530361 }
362 }
363
364 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
365 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
366}
367
Sujithcbe61d82009-02-09 13:27:12 +0530368static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
Sujithf1dc5602008-10-29 10:16:30 +0530369{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700370 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530371 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
372 u32 qGainMismatch, iGainMismatch, val, i;
373
374 for (i = 0; i < numChains; i++) {
Sujith2660b812009-02-09 13:27:26 +0530375 iOddMeasOffset = ah->totalAdcIOddPhase[i];
376 iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
377 qOddMeasOffset = ah->totalAdcQOddPhase[i];
378 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
Sujithf1dc5602008-10-29 10:16:30 +0530379
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700380 ath_print(common, ATH_DBG_CALIBRATE,
381 "Starting ADC Gain Cal for Chain %d\n", i);
Sujithf1dc5602008-10-29 10:16:30 +0530382
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700383 ath_print(common, ATH_DBG_CALIBRATE,
384 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
385 iOddMeasOffset);
386 ath_print(common, ATH_DBG_CALIBRATE,
387 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
388 iEvenMeasOffset);
389 ath_print(common, ATH_DBG_CALIBRATE,
390 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
391 qOddMeasOffset);
392 ath_print(common, ATH_DBG_CALIBRATE,
393 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
394 qEvenMeasOffset);
Sujithf1dc5602008-10-29 10:16:30 +0530395
396 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
397 iGainMismatch =
398 ((iEvenMeasOffset * 32) /
399 iOddMeasOffset) & 0x3f;
400 qGainMismatch =
401 ((qOddMeasOffset * 32) /
402 qEvenMeasOffset) & 0x3f;
403
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700404 ath_print(common, ATH_DBG_CALIBRATE,
405 "Chn %d gain_mismatch_i = 0x%08x\n", i,
406 iGainMismatch);
407 ath_print(common, ATH_DBG_CALIBRATE,
408 "Chn %d gain_mismatch_q = 0x%08x\n", i,
409 qGainMismatch);
Sujithf1dc5602008-10-29 10:16:30 +0530410
411 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
412 val &= 0xfffff000;
413 val |= (qGainMismatch) | (iGainMismatch << 6);
414 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
415
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700416 ath_print(common, ATH_DBG_CALIBRATE,
417 "ADC Gain Cal done for Chain %d\n", i);
Sujithf1dc5602008-10-29 10:16:30 +0530418 }
419 }
420
421 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
422 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
423 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
424}
425
Sujithcbe61d82009-02-09 13:27:12 +0530426static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
Sujithf1dc5602008-10-29 10:16:30 +0530427{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700428 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530429 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
430 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
Sujithcbfe9462009-04-13 21:56:56 +0530431 const struct ath9k_percal_data *calData =
Sujith2660b812009-02-09 13:27:26 +0530432 ah->cal_list_curr->calData;
Sujithf1dc5602008-10-29 10:16:30 +0530433 u32 numSamples =
434 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
435
436 for (i = 0; i < numChains; i++) {
Sujith2660b812009-02-09 13:27:26 +0530437 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
438 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
439 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
440 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
Sujithf1dc5602008-10-29 10:16:30 +0530441
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700442 ath_print(common, ATH_DBG_CALIBRATE,
443 "Starting ADC DC Offset Cal for Chain %d\n", i);
Sujithf1dc5602008-10-29 10:16:30 +0530444
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700445 ath_print(common, ATH_DBG_CALIBRATE,
446 "Chn %d pwr_meas_odd_i = %d\n", i,
447 iOddMeasOffset);
448 ath_print(common, ATH_DBG_CALIBRATE,
449 "Chn %d pwr_meas_even_i = %d\n", i,
450 iEvenMeasOffset);
451 ath_print(common, ATH_DBG_CALIBRATE,
452 "Chn %d pwr_meas_odd_q = %d\n", i,
453 qOddMeasOffset);
454 ath_print(common, ATH_DBG_CALIBRATE,
455 "Chn %d pwr_meas_even_q = %d\n", i,
456 qEvenMeasOffset);
Sujithf1dc5602008-10-29 10:16:30 +0530457
458 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
459 numSamples) & 0x1ff;
460 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
461 numSamples) & 0x1ff;
462
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700463 ath_print(common, ATH_DBG_CALIBRATE,
464 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
465 iDcMismatch);
466 ath_print(common, ATH_DBG_CALIBRATE,
467 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
468 qDcMismatch);
Sujithf1dc5602008-10-29 10:16:30 +0530469
470 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
471 val &= 0xc0000fff;
472 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
473 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
474
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700475 ath_print(common, ATH_DBG_CALIBRATE,
476 "ADC DC Offset Cal done for Chain %d\n", i);
Sujithf1dc5602008-10-29 10:16:30 +0530477 }
478
479 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
480 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
481 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
482}
483
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800484/* This is done for the currently configured channel */
Sujithcbe61d82009-02-09 13:27:12 +0530485bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530486{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700487 struct ath_common *common = ath9k_hw_common(ah);
488 struct ieee80211_conf *conf = &common->hw->conf;
Sujithcbfe9462009-04-13 21:56:56 +0530489 struct ath9k_cal_list *currCal = ah->cal_list_curr;
Sujithf1dc5602008-10-29 10:16:30 +0530490
Sujith2660b812009-02-09 13:27:26 +0530491 if (!ah->curchan)
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800492 return true;
Sujithf1dc5602008-10-29 10:16:30 +0530493
494 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800495 return true;
Sujithf1dc5602008-10-29 10:16:30 +0530496
497 if (currCal == NULL)
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800498 return true;
Sujithf1dc5602008-10-29 10:16:30 +0530499
500 if (currCal->calState != CAL_DONE) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700501 ath_print(common, ATH_DBG_CALIBRATE,
502 "Calibration state incorrect, %d\n",
503 currCal->calState);
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800504 return true;
Sujithf1dc5602008-10-29 10:16:30 +0530505 }
506
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800507 if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
508 return true;
Sujithf1dc5602008-10-29 10:16:30 +0530509
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700510 ath_print(common, ATH_DBG_CALIBRATE,
511 "Resetting Cal %d state for channel %u\n",
512 currCal->calData->calType, conf->channel->center_freq);
Sujithf1dc5602008-10-29 10:16:30 +0530513
Sujith2660b812009-02-09 13:27:26 +0530514 ah->curchan->CalValid &= ~currCal->calData->calType;
Sujithf1dc5602008-10-29 10:16:30 +0530515 currCal->calState = CAL_WAITING;
516
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -0800517 return false;
Sujithf1dc5602008-10-29 10:16:30 +0530518}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400519EXPORT_SYMBOL(ath9k_hw_reset_calvalid);
Sujithf1dc5602008-10-29 10:16:30 +0530520
Sujithcbe61d82009-02-09 13:27:12 +0530521void ath9k_hw_start_nfcal(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530522{
523 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
524 AR_PHY_AGC_CONTROL_ENABLE_NF);
525 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
526 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
527 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
528}
529
Sujithcbe61d82009-02-09 13:27:12 +0530530void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +0530531{
532 struct ath9k_nfcal_hist *h;
533 int i, j;
534 int32_t val;
535 const u32 ar5416_cca_regs[6] = {
536 AR_PHY_CCA,
537 AR_PHY_CH1_CCA,
538 AR_PHY_CH2_CCA,
539 AR_PHY_EXT_CCA,
540 AR_PHY_CH1_EXT_CCA,
541 AR_PHY_CH2_EXT_CCA
542 };
Senthil Balasubramaniance143bb2009-09-17 09:27:33 +0530543 u8 chainmask, rx_chain_status;
Sujithf1dc5602008-10-29 10:16:30 +0530544
Senthil Balasubramaniance143bb2009-09-17 09:27:33 +0530545 rx_chain_status = REG_READ(ah, AR_PHY_RX_CHAINMASK);
Sujith6398dc02010-03-17 14:25:19 +0530546 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
Sujith5dad40c2009-01-23 11:20:55 +0530547 chainmask = 0x9;
Senthil Balasubramaniance143bb2009-09-17 09:27:33 +0530548 else if (AR_SREV_9280(ah) || AR_SREV_9287(ah)) {
549 if ((rx_chain_status & 0x2) || (rx_chain_status & 0x4))
550 chainmask = 0x1B;
551 else
552 chainmask = 0x09;
553 } else {
554 if (rx_chain_status & 0x4)
555 chainmask = 0x3F;
556 else if (rx_chain_status & 0x2)
557 chainmask = 0x1B;
558 else
559 chainmask = 0x09;
560 }
Sujithf1dc5602008-10-29 10:16:30 +0530561
Sujithf1dc5602008-10-29 10:16:30 +0530562 h = ah->nfCalHist;
Sujithf1dc5602008-10-29 10:16:30 +0530563
564 for (i = 0; i < NUM_NF_READINGS; i++) {
565 if (chainmask & (1 << i)) {
566 val = REG_READ(ah, ar5416_cca_regs[i]);
567 val &= 0xFFFFFE00;
568 val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
569 REG_WRITE(ah, ar5416_cca_regs[i], val);
570 }
571 }
572
573 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
574 AR_PHY_AGC_CONTROL_ENABLE_NF);
575 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
576 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
577 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
578
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +0530579 for (j = 0; j < 5; j++) {
Sujithf1dc5602008-10-29 10:16:30 +0530580 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
581 AR_PHY_AGC_CONTROL_NF) == 0)
582 break;
Senthil Balasubramanian63a75b92009-09-18 15:07:03 +0530583 udelay(50);
Sujithf1dc5602008-10-29 10:16:30 +0530584 }
585
586 for (i = 0; i < NUM_NF_READINGS; i++) {
587 if (chainmask & (1 << i)) {
588 val = REG_READ(ah, ar5416_cca_regs[i]);
589 val &= 0xFFFFFE00;
590 val |= (((u32) (-50) << 1) & 0x1ff);
591 REG_WRITE(ah, ar5416_cca_regs[i], val);
592 }
593 }
594}
595
Sujithcbe61d82009-02-09 13:27:12 +0530596int16_t ath9k_hw_getnf(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +0530597 struct ath9k_channel *chan)
598{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700599 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530600 int16_t nf, nfThresh;
601 int16_t nfarray[NUM_NF_READINGS] = { 0 };
602 struct ath9k_nfcal_hist *h;
Luis R. Rodriguez76061ab2008-12-23 15:58:41 -0800603 struct ieee80211_channel *c = chan->chan;
Sujithf1dc5602008-10-29 10:16:30 +0530604
605 chan->channelFlags &= (~CHANNEL_CW_INT);
606 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700607 ath_print(common, ATH_DBG_CALIBRATE,
608 "NF did not complete in calibration window\n");
Sujithf1dc5602008-10-29 10:16:30 +0530609 nf = 0;
610 chan->rawNoiseFloor = nf;
611 return chan->rawNoiseFloor;
612 } else {
613 ath9k_hw_do_getnf(ah, nfarray);
614 nf = nfarray[0];
Luis R. Rodriguez76061ab2008-12-23 15:58:41 -0800615 if (getNoiseFloorThresh(ah, c->band, &nfThresh)
Sujithf1dc5602008-10-29 10:16:30 +0530616 && nf > nfThresh) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700617 ath_print(common, ATH_DBG_CALIBRATE,
618 "noise floor failed detected; "
619 "detected %d, threshold %d\n",
620 nf, nfThresh);
Sujithf1dc5602008-10-29 10:16:30 +0530621 chan->channelFlags |= CHANNEL_CW_INT;
622 }
623 }
624
Sujithf1dc5602008-10-29 10:16:30 +0530625 h = ah->nfCalHist;
Sujithf1dc5602008-10-29 10:16:30 +0530626
627 ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
628 chan->rawNoiseFloor = h[0].privNF;
629
630 return chan->rawNoiseFloor;
631}
632
Sujithcbe61d82009-02-09 13:27:12 +0530633void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530634{
635 int i, j;
Senthil Balasubramaniana59b5a52009-07-14 20:17:07 -0400636 s16 noise_floor;
637
638 if (AR_SREV_9280(ah))
639 noise_floor = AR_PHY_CCA_MAX_AR9280_GOOD_VALUE;
Sujith6398dc02010-03-17 14:25:19 +0530640 else if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
Senthil Balasubramaniana59b5a52009-07-14 20:17:07 -0400641 noise_floor = AR_PHY_CCA_MAX_AR9285_GOOD_VALUE;
Vivek Natarajan6170cd52009-09-17 09:24:24 +0530642 else if (AR_SREV_9287(ah))
643 noise_floor = AR_PHY_CCA_MAX_AR9287_GOOD_VALUE;
Senthil Balasubramaniana59b5a52009-07-14 20:17:07 -0400644 else
645 noise_floor = AR_PHY_CCA_MAX_AR5416_GOOD_VALUE;
Sujithf1dc5602008-10-29 10:16:30 +0530646
647 for (i = 0; i < NUM_NF_READINGS; i++) {
648 ah->nfCalHist[i].currIndex = 0;
Senthil Balasubramaniana59b5a52009-07-14 20:17:07 -0400649 ah->nfCalHist[i].privNF = noise_floor;
Sujithf1dc5602008-10-29 10:16:30 +0530650 ah->nfCalHist[i].invalidNFcount =
651 AR_PHY_CCA_FILTERWINDOW_LENGTH;
652 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
Senthil Balasubramaniana59b5a52009-07-14 20:17:07 -0400653 ah->nfCalHist[i].nfCalBuffer[j] = noise_floor;
Sujithf1dc5602008-10-29 10:16:30 +0530654 }
655 }
Sujithf1dc5602008-10-29 10:16:30 +0530656}
657
Sujithcbe61d82009-02-09 13:27:12 +0530658s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +0530659{
Sujithf1dc5602008-10-29 10:16:30 +0530660 s16 nf;
661
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -0800662 if (chan->rawNoiseFloor == 0)
Luis R. Rodrigueze56db712008-12-23 15:58:47 -0800663 nf = -96;
664 else
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -0800665 nf = chan->rawNoiseFloor;
Sujithf1dc5602008-10-29 10:16:30 +0530666
667 if (!ath9k_hw_nf_in_range(ah, nf))
668 nf = ATH_DEFAULT_NOISE_FLOOR;
669
670 return nf;
671}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400672EXPORT_SYMBOL(ath9k_hw_getchan_noise);
Sujithf1dc5602008-10-29 10:16:30 +0530673
Vivek Natarajan0b98eaa2009-09-18 15:03:42 +0530674static void ath9k_olc_temp_compensation_9287(struct ath_hw *ah)
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530675{
Vivek Natarajan0b98eaa2009-09-18 15:03:42 +0530676 u32 rddata;
677 int32_t delta, currPDADC, slope;
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530678
679 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530680 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
681
Vivek Natarajan0b98eaa2009-09-18 15:03:42 +0530682 if (ah->initPDADC == 0 || currPDADC == 0) {
683 /*
684 * Zero value indicates that no frames have been transmitted yet,
685 * can't do temperature compensation until frames are transmitted.
686 */
687 return;
688 } else {
689 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
690
691 if (slope == 0) { /* to avoid divide by zero case */
692 delta = 0;
693 } else {
694 delta = ((currPDADC - ah->initPDADC)*4) / slope;
695 }
696 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
697 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
698 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
699 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
700 }
701}
702
703static void ath9k_olc_temp_compensation(struct ath_hw *ah)
704{
705 u32 rddata, i;
706 int delta, currPDADC, regval;
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530707
Vivek Natarajandb91f2e2009-08-14 11:27:16 +0530708 if (OLC_FOR_AR9287_10_LATER) {
Vivek Natarajan0b98eaa2009-09-18 15:03:42 +0530709 ath9k_olc_temp_compensation_9287(ah);
710 } else {
711 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
712 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
713
Vivek Natarajandb91f2e2009-08-14 11:27:16 +0530714 if (ah->initPDADC == 0 || currPDADC == 0) {
715 return;
716 } else {
Vivek Natarajan0b98eaa2009-09-18 15:03:42 +0530717 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
718 delta = (currPDADC - ah->initPDADC + 4) / 8;
Vivek Natarajandb91f2e2009-08-14 11:27:16 +0530719 else
Vivek Natarajan0b98eaa2009-09-18 15:03:42 +0530720 delta = (currPDADC - ah->initPDADC + 5) / 10;
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530721
Vivek Natarajan0b98eaa2009-09-18 15:03:42 +0530722 if (delta != ah->PDADCdelta) {
723 ah->PDADCdelta = delta;
724 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
725 regval = ah->originalGain[i] - delta;
726 if (regval < 0)
727 regval = 0;
Vivek Natarajandb91f2e2009-08-14 11:27:16 +0530728
Vivek Natarajan0b98eaa2009-09-18 15:03:42 +0530729 REG_RMW_FIELD(ah,
730 AR_PHY_TX_GAIN_TBL1 + i * 4,
731 AR_PHY_TX_GAIN, regval);
732 }
Vivek Natarajandb91f2e2009-08-14 11:27:16 +0530733 }
Senthil Balasubramanian8bd1d072009-02-12 13:57:03 +0530734 }
735 }
736}
737
Luis R. Rodriguez62268112009-10-07 16:22:19 -0400738static void ath9k_hw_9271_pa_cal(struct ath_hw *ah, bool is_reset)
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400739{
740 u32 regVal;
741 unsigned int i;
742 u32 regList [][2] = {
743 { 0x786c, 0 },
744 { 0x7854, 0 },
745 { 0x7820, 0 },
746 { 0x7824, 0 },
747 { 0x7868, 0 },
748 { 0x783c, 0 },
749 { 0x7838, 0 } ,
750 { 0x7828, 0 } ,
751 };
752
753 for (i = 0; i < ARRAY_SIZE(regList); i++)
754 regList[i][1] = REG_READ(ah, regList[i][0]);
755
756 regVal = REG_READ(ah, 0x7834);
757 regVal &= (~(0x1));
758 REG_WRITE(ah, 0x7834, regVal);
759 regVal = REG_READ(ah, 0x9808);
760 regVal |= (0x1 << 27);
761 REG_WRITE(ah, 0x9808, regVal);
762
763 /* 786c,b23,1, pwddac=1 */
764 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
765 /* 7854, b5,1, pdrxtxbb=1 */
766 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
767 /* 7854, b7,1, pdv2i=1 */
768 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
769 /* 7854, b8,1, pddacinterface=1 */
770 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
771 /* 7824,b12,0, offcal=0 */
772 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
773 /* 7838, b1,0, pwddb=0 */
774 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
775 /* 7820,b11,0, enpacal=0 */
776 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
777 /* 7820,b25,1, pdpadrv1=0 */
778 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
779 /* 7820,b24,0, pdpadrv2=0 */
780 REG_RMW_FIELD(ah, AR9285_AN_RF2G1,AR9285_AN_RF2G1_PDPADRV2,0);
781 /* 7820,b23,0, pdpaout=0 */
782 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
783 /* 783c,b14-16,7, padrvgn2tab_0=7 */
784 REG_RMW_FIELD(ah, AR9285_AN_RF2G8,AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
785 /*
786 * 7838,b29-31,0, padrvgn1tab_0=0
787 * does not matter since we turn it off
788 */
789 REG_RMW_FIELD(ah, AR9285_AN_RF2G7,AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
790
791 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
792
793 /* Set:
794 * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
795 * txon=1,paon=1,oscon=1,synthon_force=1
796 */
797 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
798 udelay(30);
799 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
800
801 /* find off_6_1; */
Luis R. Rodriguez1d9c1852009-10-27 12:59:37 -0400802 for (i = 6; i > 0; i--) {
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400803 regVal = REG_READ(ah, 0x7834);
804 regVal |= (1 << (20 + i));
805 REG_WRITE(ah, 0x7834, regVal);
806 udelay(1);
807 //regVal = REG_READ(ah, 0x7834);
808 regVal &= (~(0x1 << (20 + i)));
809 regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
810 << (20 + i));
811 REG_WRITE(ah, 0x7834, regVal);
812 }
813
Luis R. Rodriguez62268112009-10-07 16:22:19 -0400814 regVal = (regVal >>20) & 0x7f;
815
816 /* Update PA cal info */
817 if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
818 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
819 ah->pacal_info.max_skipcount =
820 2 * ah->pacal_info.max_skipcount;
821 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
822 } else {
823 ah->pacal_info.max_skipcount = 1;
824 ah->pacal_info.skipcount = 0;
825 ah->pacal_info.prev_offset = regVal;
826 }
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400827
828 regVal = REG_READ(ah, 0x7834);
829 regVal |= 0x1;
830 REG_WRITE(ah, 0x7834, regVal);
831 regVal = REG_READ(ah, 0x9808);
832 regVal &= (~(0x1 << 27));
833 REG_WRITE(ah, 0x9808, regVal);
834
835 for (i = 0; i < ARRAY_SIZE(regList); i++)
836 REG_WRITE(ah, regList[i][0], regList[i][1]);
837}
838
Sujitha13883b2009-08-26 08:39:40 +0530839static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530840{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700841 struct ath_common *common = ath9k_hw_common(ah);
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530842 u32 regVal;
843 int i, offset, offs_6_1, offs_0;
844 u32 ccomp_org, reg_field;
845 u32 regList[][2] = {
846 { 0x786c, 0 },
847 { 0x7854, 0 },
848 { 0x7820, 0 },
849 { 0x7824, 0 },
850 { 0x7868, 0 },
851 { 0x783c, 0 },
852 { 0x7838, 0 },
853 };
854
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700855 ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
Sujitha13883b2009-08-26 08:39:40 +0530856
Sujith20caf0d2009-08-26 08:39:52 +0530857 /* PA CAL is not needed for high power solution */
858 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
859 AR5416_EEP_TXGAIN_HIGH_POWER)
860 return;
861
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530862 if (AR_SREV_9285_11(ah)) {
863 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
864 udelay(10);
865 }
866
867 for (i = 0; i < ARRAY_SIZE(regList); i++)
868 regList[i][1] = REG_READ(ah, regList[i][0]);
869
870 regVal = REG_READ(ah, 0x7834);
871 regVal &= (~(0x1));
872 REG_WRITE(ah, 0x7834, regVal);
873 regVal = REG_READ(ah, 0x9808);
874 regVal |= (0x1 << 27);
875 REG_WRITE(ah, 0x9808, regVal);
876
877 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
878 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
879 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
880 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
881 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
882 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
883 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
Sujith0abb0962009-08-26 08:39:50 +0530884 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530885 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
886 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
887 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
888 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
889 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
Sujith0abb0962009-08-26 08:39:50 +0530890 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530891
892 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
893 udelay(30);
894 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
895 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
896
897 for (i = 6; i > 0; i--) {
898 regVal = REG_READ(ah, 0x7834);
899 regVal |= (1 << (19 + i));
900 REG_WRITE(ah, 0x7834, regVal);
901 udelay(1);
Sujithedbf51f2009-09-17 09:28:41 +0530902 regVal = REG_READ(ah, 0x7834);
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530903 regVal &= (~(0x1 << (19 + i)));
904 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
905 regVal |= (reg_field << (19 + i));
906 REG_WRITE(ah, 0x7834, regVal);
907 }
908
909 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
910 udelay(1);
911 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
912 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
913 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
914 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
915
916 offset = (offs_6_1<<1) | offs_0;
917 offset = offset - 0;
918 offs_6_1 = offset>>1;
919 offs_0 = offset & 1;
920
Sujitha13883b2009-08-26 08:39:40 +0530921 if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
922 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
923 ah->pacal_info.max_skipcount =
924 2 * ah->pacal_info.max_skipcount;
925 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
926 } else {
927 ah->pacal_info.max_skipcount = 1;
928 ah->pacal_info.skipcount = 0;
929 ah->pacal_info.prev_offset = offset;
930 }
931
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530932 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
933 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
934
935 regVal = REG_READ(ah, 0x7834);
936 regVal |= 0x1;
937 REG_WRITE(ah, 0x7834, regVal);
938 regVal = REG_READ(ah, 0x9808);
939 regVal &= (~(0x1 << 27));
940 REG_WRITE(ah, 0x9808, regVal);
941
942 for (i = 0; i < ARRAY_SIZE(regList); i++)
943 REG_WRITE(ah, regList[i][0], regList[i][1]);
944
945 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
946
947 if (AR_SREV_9285_11(ah))
948 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
949
950}
951
Luis R. Rodriguez4d001d12010-04-15 17:38:51 -0400952static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
953{
954 if (AR_SREV_9271(ah)) {
955 if (is_reset || !ah->pacal_info.skipcount)
956 ath9k_hw_9271_pa_cal(ah, is_reset);
957 else
958 ah->pacal_info.skipcount--;
959 } else if (AR_SREV_9285_11_OR_LATER(ah)) {
960 if (is_reset || !ah->pacal_info.skipcount)
961 ath9k_hw_9285_pa_cal(ah, is_reset);
962 else
963 ah->pacal_info.skipcount--;
964 }
965}
966
Luis R. Rodrigueze83a1132010-04-15 17:38:52 -0400967static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
968{
969 if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER)
970 ath9k_olc_temp_compensation(ah);
971}
972
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530973bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
Sujith379f0442009-04-13 21:56:48 +0530974 u8 rxchainmask, bool longcal)
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530975{
Sujith379f0442009-04-13 21:56:48 +0530976 bool iscaldone = true;
Sujithcbfe9462009-04-13 21:56:56 +0530977 struct ath9k_cal_list *currCal = ah->cal_list_curr;
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530978
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530979 if (currCal &&
980 (currCal->calState == CAL_RUNNING ||
981 currCal->calState == CAL_WAITING)) {
Sujith379f0442009-04-13 21:56:48 +0530982 iscaldone = ath9k_hw_per_calibration(ah, chan,
983 rxchainmask, currCal);
984 if (iscaldone) {
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530985 ah->cal_list_curr = currCal = currCal->calNext;
986
987 if (currCal->calState == CAL_WAITING) {
Sujith379f0442009-04-13 21:56:48 +0530988 iscaldone = false;
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530989 ath9k_hw_reset_calibration(ah, currCal);
990 }
991 }
992 }
993
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400994 /* Do NF cal only at longer intervals */
Senthil Balasubramanian4e845162009-03-06 11:24:10 +0530995 if (longcal) {
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400996 /* Do periodic PAOffset Cal */
Luis R. Rodriguez4d001d12010-04-15 17:38:51 -0400997 ar9002_hw_pa_cal(ah, false);
Luis R. Rodrigueze83a1132010-04-15 17:38:52 -0400998 ar9002_hw_olc_temp_compensation(ah);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -0400999
1000 /* Get the value from the previous NF cal and update history buffer */
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301001 ath9k_hw_getnf(ah, chan);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001002
1003 /*
1004 * Load the NF from history buffer of the current channel.
1005 * NF is slow time-variant, so it is OK to use a historical value.
1006 */
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301007 ath9k_hw_loadnf(ah, ah->curchan);
Luis R. Rodriguezd7e7d222009-08-03 23:14:12 -04001008
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301009 ath9k_hw_start_nfcal(ah);
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301010 }
1011
Sujith379f0442009-04-13 21:56:48 +05301012 return iscaldone;
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301013}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -04001014EXPORT_SYMBOL(ath9k_hw_calibrate);
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301015
Luis R. Rodriguezb57df122009-10-07 16:22:18 -04001016/* Carrier leakage Calibration fix */
Vivek Natarajan53bc7aa2010-04-05 14:48:04 +05301017static bool ar9285_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301018{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001019 struct ath_common *common = ath9k_hw_common(ah);
1020
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301021 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
Sujithdb2f63f2009-04-13 21:56:41 +05301022 if (IS_CHAN_HT20(chan)) {
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301023 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
1024 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
1025 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1026 AR_PHY_AGC_CONTROL_FLTR_CAL);
1027 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
1028 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1029 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1030 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001031 ath_print(common, ATH_DBG_CALIBRATE, "offset "
1032 "calibration failed to complete in "
1033 "1ms; noisy ??\n");
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301034 return false;
1035 }
1036 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
1037 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
1038 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1039 }
1040 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
1041 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
1042 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
1043 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1044 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1045 0, AH_WAIT_TIMEOUT)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001046 ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
1047 "failed to complete in 1ms; noisy ??\n");
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301048 return false;
1049 }
1050
1051 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
1052 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
1053 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
1054
1055 return true;
1056}
1057
Vivek Natarajan53bc7aa2010-04-05 14:48:04 +05301058static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1059{
1060 int i;
1061 u_int32_t txgain_max;
1062 u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
1063 u_int32_t reg_clc_I0, reg_clc_Q0;
1064 u_int32_t i0_num = 0;
1065 u_int32_t q0_num = 0;
1066 u_int32_t total_num = 0;
1067 u_int32_t reg_rf2g5_org;
1068 bool retv = true;
1069
1070 if (!(ar9285_cl_cal(ah, chan)))
1071 return false;
1072
1073 txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
1074 AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
1075
1076 for (i = 0; i < (txgain_max+1); i++) {
1077 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
1078 AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
1079 if (!(gain_mask & (1 << clc_gain))) {
1080 gain_mask |= (1 << clc_gain);
1081 clc_num++;
1082 }
1083 }
1084
1085 for (i = 0; i < clc_num; i++) {
1086 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
1087 & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
1088 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
1089 & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
1090 if (reg_clc_I0 == 0)
1091 i0_num++;
1092
1093 if (reg_clc_Q0 == 0)
1094 q0_num++;
1095 }
1096 total_num = i0_num + q0_num;
1097 if (total_num > AR9285_CLCAL_REDO_THRESH) {
1098 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
1099 if (AR_SREV_9285E_20(ah)) {
1100 REG_WRITE(ah, AR9285_RF2G5,
1101 (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
1102 AR9285_RF2G5_IC50TX_XE_SET);
1103 } else {
1104 REG_WRITE(ah, AR9285_RF2G5,
1105 (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
1106 AR9285_RF2G5_IC50TX_SET);
1107 }
1108 retv = ar9285_cl_cal(ah, chan);
1109 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
1110 }
1111 return retv;
1112}
1113
Sujith04d19dd2009-04-13 21:56:59 +05301114bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
Sujithf1dc5602008-10-29 10:16:30 +05301115{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001116 struct ath_common *common = ath9k_hw_common(ah);
1117
Luis R. Rodriguezb57df122009-10-07 16:22:18 -04001118 if (AR_SREV_9271(ah) || AR_SREV_9285_12_OR_LATER(ah)) {
Senthil Balasubramanian4e845162009-03-06 11:24:10 +05301119 if (!ar9285_clc(ah, chan))
1120 return false;
Sujith04d19dd2009-04-13 21:56:59 +05301121 } else {
1122 if (AR_SREV_9280_10_OR_LATER(ah)) {
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05301123 if (!AR_SREV_9287_10_OR_LATER(ah))
1124 REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
1125 AR_PHY_ADC_CTL_OFF_PWDADC);
1126 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1127 AR_PHY_AGC_CONTROL_FLTR_CAL);
Sujith04d19dd2009-04-13 21:56:59 +05301128 }
Sujithedf7c062009-02-12 10:06:49 +05301129
Sujith04d19dd2009-04-13 21:56:59 +05301130 /* Calibrate the AGC */
Sujithedf7c062009-02-12 10:06:49 +05301131 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
Sujith04d19dd2009-04-13 21:56:59 +05301132 REG_READ(ah, AR_PHY_AGC_CONTROL) |
1133 AR_PHY_AGC_CONTROL_CAL);
Sujithedf7c062009-02-12 10:06:49 +05301134
Sujith04d19dd2009-04-13 21:56:59 +05301135 /* Poll for offset calibration complete */
1136 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1137 0, AH_WAIT_TIMEOUT)) {
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001138 ath_print(common, ATH_DBG_CALIBRATE,
1139 "offset calibration failed to "
1140 "complete in 1ms; noisy environment?\n");
Sujithedf7c062009-02-12 10:06:49 +05301141 return false;
1142 }
1143
Sujith04d19dd2009-04-13 21:56:59 +05301144 if (AR_SREV_9280_10_OR_LATER(ah)) {
Vivek Natarajanac88b6e2009-07-23 10:59:57 +05301145 if (!AR_SREV_9287_10_OR_LATER(ah))
1146 REG_SET_BIT(ah, AR_PHY_ADC_CTL,
1147 AR_PHY_ADC_CTL_OFF_PWDADC);
1148 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1149 AR_PHY_AGC_CONTROL_FLTR_CAL);
Sujith04d19dd2009-04-13 21:56:59 +05301150 }
Sujithedf7c062009-02-12 10:06:49 +05301151 }
1152
1153 /* Do PA Calibration */
Luis R. Rodriguez4d001d12010-04-15 17:38:51 -04001154 ar9002_hw_pa_cal(ah, true);
Senthil Balasubramaniane7594072008-12-08 19:43:48 +05301155
Sujith04d19dd2009-04-13 21:56:59 +05301156 /* Do NF Calibration after DC offset and other calibrations */
Sujithf1dc5602008-10-29 10:16:30 +05301157 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
Sujith04d19dd2009-04-13 21:56:59 +05301158 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
Sujithf1dc5602008-10-29 10:16:30 +05301159
Sujith2660b812009-02-09 13:27:26 +05301160 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
Sujithf1dc5602008-10-29 10:16:30 +05301161
Sujith04d19dd2009-04-13 21:56:59 +05301162 /* Enable IQ, ADC Gain and ADC DC offset CALs */
Sujithf1dc5602008-10-29 10:16:30 +05301163 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -08001164 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
Sujith2660b812009-02-09 13:27:26 +05301165 INIT_CAL(&ah->adcgain_caldata);
1166 INSERT_CAL(ah, &ah->adcgain_caldata);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001167 ath_print(common, ATH_DBG_CALIBRATE,
1168 "enabling ADC Gain Calibration.\n");
Sujithf1dc5602008-10-29 10:16:30 +05301169 }
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -08001170 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
Sujith2660b812009-02-09 13:27:26 +05301171 INIT_CAL(&ah->adcdc_caldata);
1172 INSERT_CAL(ah, &ah->adcdc_caldata);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001173 ath_print(common, ATH_DBG_CALIBRATE,
1174 "enabling ADC DC Calibration.\n");
Sujithf1dc5602008-10-29 10:16:30 +05301175 }
Luis R. Rodriguezc9e27d92008-12-23 15:58:42 -08001176 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
Sujith2660b812009-02-09 13:27:26 +05301177 INIT_CAL(&ah->iq_caldata);
1178 INSERT_CAL(ah, &ah->iq_caldata);
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -07001179 ath_print(common, ATH_DBG_CALIBRATE,
1180 "enabling IQ Calibration.\n");
Sujithf1dc5602008-10-29 10:16:30 +05301181 }
1182
Sujith2660b812009-02-09 13:27:26 +05301183 ah->cal_list_curr = ah->cal_list;
Sujithf1dc5602008-10-29 10:16:30 +05301184
Sujith2660b812009-02-09 13:27:26 +05301185 if (ah->cal_list_curr)
1186 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
Sujithf1dc5602008-10-29 10:16:30 +05301187 }
1188
Luis R. Rodriguez5f8e0772009-01-22 15:16:48 -08001189 chan->CalValid = 0;
Sujithf1dc5602008-10-29 10:16:30 +05301190
1191 return true;
1192}
1193
Sujithcbfe9462009-04-13 21:56:56 +05301194const struct ath9k_percal_data iq_cal_multi_sample = {
Sujithf1dc5602008-10-29 10:16:30 +05301195 IQ_MISMATCH_CAL,
1196 MAX_CAL_SAMPLES,
1197 PER_MIN_LOG_COUNT,
1198 ath9k_hw_iqcal_collect,
1199 ath9k_hw_iqcalibrate
1200};
Sujithcbfe9462009-04-13 21:56:56 +05301201const struct ath9k_percal_data iq_cal_single_sample = {
Sujithf1dc5602008-10-29 10:16:30 +05301202 IQ_MISMATCH_CAL,
1203 MIN_CAL_SAMPLES,
1204 PER_MAX_LOG_COUNT,
1205 ath9k_hw_iqcal_collect,
1206 ath9k_hw_iqcalibrate
1207};
Sujithcbfe9462009-04-13 21:56:56 +05301208const struct ath9k_percal_data adc_gain_cal_multi_sample = {
Sujithf1dc5602008-10-29 10:16:30 +05301209 ADC_GAIN_CAL,
1210 MAX_CAL_SAMPLES,
1211 PER_MIN_LOG_COUNT,
1212 ath9k_hw_adc_gaincal_collect,
1213 ath9k_hw_adc_gaincal_calibrate
1214};
Sujithcbfe9462009-04-13 21:56:56 +05301215const struct ath9k_percal_data adc_gain_cal_single_sample = {
Sujithf1dc5602008-10-29 10:16:30 +05301216 ADC_GAIN_CAL,
1217 MIN_CAL_SAMPLES,
1218 PER_MAX_LOG_COUNT,
1219 ath9k_hw_adc_gaincal_collect,
1220 ath9k_hw_adc_gaincal_calibrate
1221};
Sujithcbfe9462009-04-13 21:56:56 +05301222const struct ath9k_percal_data adc_dc_cal_multi_sample = {
Sujithf1dc5602008-10-29 10:16:30 +05301223 ADC_DC_CAL,
1224 MAX_CAL_SAMPLES,
1225 PER_MIN_LOG_COUNT,
1226 ath9k_hw_adc_dccal_collect,
1227 ath9k_hw_adc_dccal_calibrate
1228};
Sujithcbfe9462009-04-13 21:56:56 +05301229const struct ath9k_percal_data adc_dc_cal_single_sample = {
Sujithf1dc5602008-10-29 10:16:30 +05301230 ADC_DC_CAL,
1231 MIN_CAL_SAMPLES,
1232 PER_MAX_LOG_COUNT,
1233 ath9k_hw_adc_dccal_collect,
1234 ath9k_hw_adc_dccal_calibrate
1235};
Sujithcbfe9462009-04-13 21:56:56 +05301236const struct ath9k_percal_data adc_init_dc_cal = {
Sujithf1dc5602008-10-29 10:16:30 +05301237 ADC_DC_INIT_CAL,
1238 MIN_CAL_SAMPLES,
1239 INIT_LOG_COUNT,
1240 ath9k_hw_adc_dccal_collect,
1241 ath9k_hw_adc_dccal_calibrate
1242};