Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 1 | /* |
Mike Frysinger | fa48f84 | 2009-06-17 11:25:06 -0400 | [diff] [blame^] | 2 | * BF548 memory map |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 3 | * |
Mike Frysinger | fa48f84 | 2009-06-17 11:25:06 -0400 | [diff] [blame^] | 4 | * Copyright 2004-2009 Analog Devices Inc. |
| 5 | * Licensed under the GPL-2 or later. |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 6 | */ |
| 7 | |
Mike Frysinger | fa48f84 | 2009-06-17 11:25:06 -0400 | [diff] [blame^] | 8 | #ifndef __BFIN_MACH_MEM_MAP_H__ |
| 9 | #define __BFIN_MACH_MEM_MAP_H__ |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 10 | |
Mike Frysinger | fa48f84 | 2009-06-17 11:25:06 -0400 | [diff] [blame^] | 11 | #ifndef __BFIN_MEM_MAP_H__ |
| 12 | # error "do not include mach/mem_map.h directly -- use asm/mem_map.h" |
| 13 | #endif |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 14 | |
| 15 | /* Async Memory Banks */ |
| 16 | #define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */ |
| 17 | #define ASYNC_BANK3_SIZE 0x04000000 /* 64M */ |
| 18 | #define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */ |
| 19 | #define ASYNC_BANK2_SIZE 0x04000000 /* 64M */ |
| 20 | #define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */ |
| 21 | #define ASYNC_BANK1_SIZE 0x04000000 /* 64M */ |
| 22 | #define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ |
| 23 | #define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ |
| 24 | |
| 25 | /* Boot ROM Memory */ |
| 26 | |
| 27 | #define BOOT_ROM_START 0xEF000000 |
Mike Frysinger | c3a9f43 | 2007-11-21 16:12:12 +0800 | [diff] [blame] | 28 | #define BOOT_ROM_LENGTH 0x1000 |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 29 | |
Mike Frysinger | b018785 | 2007-11-21 16:14:03 +0800 | [diff] [blame] | 30 | /* L1 Instruction ROM */ |
| 31 | |
| 32 | #define L1_ROM_START 0xFFA14000 |
| 33 | #define L1_ROM_LENGTH 0x10000 |
| 34 | |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 35 | /* Level 1 Memory */ |
| 36 | |
| 37 | /* Memory Map for ADSP-BF548 processors */ |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 38 | #ifdef CONFIG_BFIN_ICACHE |
| 39 | #define BFIN_ICACHESIZE (16*1024) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 40 | #else |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 41 | #define BFIN_ICACHESIZE (0*1024) |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 42 | #endif |
| 43 | |
| 44 | #define L1_CODE_START 0xFFA00000 |
| 45 | #define L1_DATA_A_START 0xFF800000 |
| 46 | #define L1_DATA_B_START 0xFF900000 |
| 47 | |
| 48 | #define L1_CODE_LENGTH 0xC000 |
| 49 | |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 50 | #ifdef CONFIG_BFIN_DCACHE |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 51 | |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 52 | #ifdef CONFIG_BFIN_DCACHE_BANKA |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 53 | #define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) |
| 54 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) |
| 55 | #define L1_DATA_B_LENGTH 0x8000 |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 56 | #define BFIN_DCACHESIZE (16*1024) |
| 57 | #define BFIN_DSUPBANKS 1 |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 58 | #else |
| 59 | #define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) |
| 60 | #define L1_DATA_A_LENGTH (0x8000 - 0x4000) |
| 61 | #define L1_DATA_B_LENGTH (0x8000 - 0x4000) |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 62 | #define BFIN_DCACHESIZE (32*1024) |
| 63 | #define BFIN_DSUPBANKS 2 |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 64 | #endif |
| 65 | |
| 66 | #else |
| 67 | #define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) |
| 68 | #define L1_DATA_A_LENGTH 0x8000 |
| 69 | #define L1_DATA_B_LENGTH 0x8000 |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 70 | #define BFIN_DCACHESIZE (0*1024) |
| 71 | #define BFIN_DSUPBANKS 0 |
| 72 | #endif /*CONFIG_BFIN_DCACHE*/ |
Roy Huang | 088eec1 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 73 | |
Mike Frysinger | c3a9f43 | 2007-11-21 16:12:12 +0800 | [diff] [blame] | 74 | /* Level 2 Memory */ |
Mike Frysinger | ad5dd97 | 2008-10-10 21:17:11 +0800 | [diff] [blame] | 75 | #define L2_START 0xFEB00000 |
| 76 | #if defined(CONFIG_BF542) |
| 77 | # define L2_LENGTH 0 |
| 78 | #elif defined(CONFIG_BF544) |
| 79 | # define L2_LENGTH 0x10000 |
| 80 | #else |
| 81 | # define L2_LENGTH 0x20000 |
Mike Frysinger | c3a9f43 | 2007-11-21 16:12:12 +0800 | [diff] [blame] | 82 | #endif |
| 83 | |
Mike Frysinger | fa48f84 | 2009-06-17 11:25:06 -0400 | [diff] [blame^] | 84 | #endif |