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Ivo van Doorn95ea3622007-09-25 17:57:13 -07001/*
Ivo van Doorn811aa9c2008-02-03 15:42:53 +01002 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
Ivo van Doorn95ea3622007-09-25 17:57:13 -07003 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
Ivo van Doorn95ea3622007-09-25 17:57:13 -070027#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2400pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
Adam Baker0e14f6d2007-10-27 13:41:25 +020052static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
Ivo van Doorn95ea3622007-09-25 17:57:13 -070053{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
Adam Baker0e14f6d2007-10-27 13:41:25 +020067static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -070068 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
Adam Baker0e14f6d2007-10-27 13:41:25 +020093static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -070094 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
Adam Baker0e14f6d2007-10-27 13:41:25 +0200130static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
Adam Baker0e14f6d2007-10-27 13:41:25 +0200193static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
Adam Baker0e14f6d2007-10-27 13:41:25 +0200199static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2400PCI_RFKILL
235static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
Ivo van Doorn81873e92007-10-06 14:14:06 +0200242#else
243#define rt2400pci_rfkill_poll NULL
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700244#endif /* CONFIG_RT2400PCI_RFKILL */
245
Ivo van Doorna9450b72008-02-03 15:53:40 +0100246#ifdef CONFIG_RT2400PCI_LEDS
Ivo van Doorna2e1d522008-03-31 15:53:44 +0200247static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
Ivo van Doorna9450b72008-02-03 15:53:40 +0100248 enum led_brightness brightness)
249{
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
Ivo van Doorna9450b72008-02-03 15:53:40 +0100253 u32 reg;
254
255 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
256
Ivo van Doorna2e1d522008-03-31 15:53:44 +0200257 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
Ivo van Doorna9450b72008-02-03 15:53:40 +0100258 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
Ivo van Doorna2e1d522008-03-31 15:53:44 +0200259 else if (led->type == LED_TYPE_ACTIVITY)
260 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
Ivo van Doorna9450b72008-02-03 15:53:40 +0100261
262 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
263}
Ivo van Doorna2e1d522008-03-31 15:53:44 +0200264
265static int rt2400pci_blink_set(struct led_classdev *led_cdev,
266 unsigned long *delay_on,
267 unsigned long *delay_off)
268{
269 struct rt2x00_led *led =
270 container_of(led_cdev, struct rt2x00_led, led_dev);
271 u32 reg;
272
273 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
274 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
275 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
276 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
277
278 return 0;
279}
Ivo van Doorna9450b72008-02-03 15:53:40 +0100280#endif /* CONFIG_RT2400PCI_LEDS */
281
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700282/*
283 * Configuration handlers.
284 */
Ivo van Doorn3a643d22008-03-25 14:13:18 +0100285static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
286 const unsigned int filter_flags)
287{
288 u32 reg;
289
290 /*
291 * Start configuration steps.
292 * Note that the version error will always be dropped
293 * since there is no filter for it at this time.
294 */
295 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
296 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
297 !(filter_flags & FIF_FCSFAIL));
298 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
299 !(filter_flags & FIF_PLCPFAIL));
300 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
301 !(filter_flags & FIF_CONTROL));
302 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
303 !(filter_flags & FIF_PROMISC_IN_BSS));
304 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
Ivo van Doorne0b005f2008-03-31 15:24:53 +0200305 !(filter_flags & FIF_PROMISC_IN_BSS) &&
306 !rt2x00dev->intf_ap_count);
Ivo van Doorn3a643d22008-03-25 14:13:18 +0100307 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
308 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
309}
310
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100311static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
312 struct rt2x00_intf *intf,
313 struct rt2x00intf_conf *conf,
314 const unsigned int flags)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700315{
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100316 unsigned int bcn_preload;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700317 u32 reg;
318
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100319 if (flags & CONFIG_UPDATE_TYPE) {
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100320 /*
321 * Enable beacon config
322 */
323 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
324 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
325 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
326 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700327
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100328 /*
329 * Enable synchronisation.
330 */
331 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
Ivo van Doornfd3c91c2008-03-09 22:47:43 +0100332 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100333 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
Ivo van Doornfd3c91c2008-03-09 22:47:43 +0100334 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100335 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
336 }
337
338 if (flags & CONFIG_UPDATE_MAC)
339 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
340 conf->mac, sizeof(conf->mac));
341
342 if (flags & CONFIG_UPDATE_BSSID)
343 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
344 conf->bssid, sizeof(conf->bssid));
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700345}
346
Ivo van Doorn3a643d22008-03-25 14:13:18 +0100347static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
348 struct rt2x00lib_erp *erp)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700349{
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200350 int preamble_mask;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700351 u32 reg;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700352
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200353 /*
354 * When short preamble is enabled, we should set bit 0x08
355 */
Ivo van Doorn72810372008-03-09 22:46:18 +0100356 preamble_mask = erp->short_preamble << 3;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700357
358 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
Ivo van Doorn72810372008-03-09 22:46:18 +0100359 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
360 erp->ack_timeout);
361 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
362 erp->ack_consume_time);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700363 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
364
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700365 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
Ivo van Doorn44a98092008-04-21 19:00:17 +0200366 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700367 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
368 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
369 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
370
371 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200372 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700373 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
374 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
375 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
376
377 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200378 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700379 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
380 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
381 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
382
383 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200384 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700385 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
386 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
387 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
388}
389
390static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200391 const int basic_rate_mask)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700392{
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200393 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700394}
395
396static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200397 struct rf_channel *rf)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700398{
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700399 /*
400 * Switch on tuning bits.
401 */
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200402 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
403 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700404
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200405 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
406 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
407 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700408
409 /*
410 * RF2420 chipset don't need any additional actions.
411 */
412 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
413 return;
414
415 /*
416 * For the RT2421 chipsets we need to write an invalid
417 * reference clock rate to activate auto_tune.
418 * After that we set the value back to the correct channel.
419 */
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200420 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700421 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200422 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700423
424 msleep(1);
425
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200426 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
427 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
428 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700429
430 msleep(1);
431
432 /*
433 * Switch off tuning bits.
434 */
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200435 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
436 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700437
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200438 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
439 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700440
441 /*
442 * Clear false CRC during channel switch.
443 */
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200444 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700445}
446
447static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
448{
449 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
450}
451
452static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
Ivo van Doornaddc81b2007-10-13 16:26:23 +0200453 struct antenna_setup *ant)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700454{
455 u8 r1;
456 u8 r4;
457
Ivo van Doorna4fe07d2008-03-09 22:45:21 +0100458 /*
459 * We should never come here because rt2x00lib is supposed
460 * to catch this and send us the correct antenna explicitely.
461 */
462 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
463 ant->tx == ANTENNA_SW_DIVERSITY);
464
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700465 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
466 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
467
468 /*
469 * Configure the TX antenna.
470 */
Ivo van Doornaddc81b2007-10-13 16:26:23 +0200471 switch (ant->tx) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700472 case ANTENNA_HW_DIVERSITY:
473 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
474 break;
475 case ANTENNA_A:
476 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
477 break;
478 case ANTENNA_B:
Ivo van Doorna4fe07d2008-03-09 22:45:21 +0100479 default:
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700480 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
481 break;
482 }
483
484 /*
485 * Configure the RX antenna.
486 */
Ivo van Doornaddc81b2007-10-13 16:26:23 +0200487 switch (ant->rx) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700488 case ANTENNA_HW_DIVERSITY:
489 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
490 break;
491 case ANTENNA_A:
492 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
493 break;
494 case ANTENNA_B:
Ivo van Doorna4fe07d2008-03-09 22:45:21 +0100495 default:
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700496 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
497 break;
498 }
499
500 rt2400pci_bbp_write(rt2x00dev, 4, r4);
501 rt2400pci_bbp_write(rt2x00dev, 1, r1);
502}
503
504static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200505 struct rt2x00lib_conf *libconf)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700506{
507 u32 reg;
508
509 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200510 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700511 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
512
513 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200514 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
515 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700516 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
517
518 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200519 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
520 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700521 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
522
523 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
524 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
525 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
526 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
527
528 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200529 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
530 libconf->conf->beacon_int * 16);
531 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
532 libconf->conf->beacon_int * 16);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700533 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
534}
535
536static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +0100537 struct rt2x00lib_conf *libconf,
538 const unsigned int flags)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700539{
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700540 if (flags & CONFIG_UPDATE_PHYMODE)
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200541 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700542 if (flags & CONFIG_UPDATE_CHANNEL)
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200543 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700544 if (flags & CONFIG_UPDATE_TXPOWER)
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200545 rt2400pci_config_txpower(rt2x00dev,
546 libconf->conf->power_level);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700547 if (flags & CONFIG_UPDATE_ANTENNA)
Ivo van Doornaddc81b2007-10-13 16:26:23 +0200548 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700549 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
Ivo van Doorn5c58ee52007-10-06 13:34:52 +0200550 rt2400pci_config_duration(rt2x00dev, libconf);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700551}
552
553static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn181d6902008-02-05 16:42:23 -0500554 const int cw_min, const int cw_max)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700555{
556 u32 reg;
557
558 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500559 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
560 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700561 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
562}
563
564/*
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700565 * Link tuning
566 */
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200567static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
568 struct link_qual *qual)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700569{
570 u32 reg;
571 u8 bbp;
572
573 /*
574 * Update FCS error count from register.
575 */
576 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200577 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700578
579 /*
580 * Update False CCA count from register.
581 */
582 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200583 qual->false_cca = bbp;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700584}
585
586static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
587{
588 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
589 rt2x00dev->link.vgc_level = 0x08;
590}
591
592static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
593{
594 u8 reg;
595
596 /*
597 * The link tuner should not run longer then 60 seconds,
598 * and should run once every 2 seconds.
599 */
600 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
601 return;
602
603 /*
604 * Base r13 link tuning on the false cca count.
605 */
606 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
607
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200608 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700609 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
610 rt2x00dev->link.vgc_level = reg;
Ivo van Doornebcf26d2007-10-13 16:26:12 +0200611 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700612 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
613 rt2x00dev->link.vgc_level = reg;
614 }
615}
616
617/*
618 * Initialization functions.
619 */
Ivo van Doorn837e7f22008-01-06 23:41:45 +0100620static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn181d6902008-02-05 16:42:23 -0500621 struct queue_entry *entry)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700622{
Ivo van Doorn181d6902008-02-05 16:42:23 -0500623 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700624 u32 word;
625
Ivo van Doorn181d6902008-02-05 16:42:23 -0500626 rt2x00_desc_read(priv_rx->desc, 2, &word);
Ivo van Doorn30b3a232008-02-17 17:33:24 +0100627 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
628 entry->queue->data_size);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500629 rt2x00_desc_write(priv_rx->desc, 2, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700630
Ivo van Doorn181d6902008-02-05 16:42:23 -0500631 rt2x00_desc_read(priv_rx->desc, 1, &word);
Ivo van Doorn30b3a232008-02-17 17:33:24 +0100632 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500633 rt2x00_desc_write(priv_rx->desc, 1, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700634
Ivo van Doorn181d6902008-02-05 16:42:23 -0500635 rt2x00_desc_read(priv_rx->desc, 0, &word);
Ivo van Doorn837e7f22008-01-06 23:41:45 +0100636 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500637 rt2x00_desc_write(priv_rx->desc, 0, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700638}
639
Ivo van Doorn837e7f22008-01-06 23:41:45 +0100640static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
Ivo van Doorn181d6902008-02-05 16:42:23 -0500641 struct queue_entry *entry)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700642{
Ivo van Doorn181d6902008-02-05 16:42:23 -0500643 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700644 u32 word;
645
Ivo van Doorn181d6902008-02-05 16:42:23 -0500646 rt2x00_desc_read(priv_tx->desc, 1, &word);
Ivo van Doorn30b3a232008-02-17 17:33:24 +0100647 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500648 rt2x00_desc_write(priv_tx->desc, 1, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700649
Ivo van Doorn181d6902008-02-05 16:42:23 -0500650 rt2x00_desc_read(priv_tx->desc, 2, &word);
651 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
652 entry->queue->data_size);
653 rt2x00_desc_write(priv_tx->desc, 2, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700654
Ivo van Doorn181d6902008-02-05 16:42:23 -0500655 rt2x00_desc_read(priv_tx->desc, 0, &word);
Ivo van Doorn837e7f22008-01-06 23:41:45 +0100656 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
657 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500658 rt2x00_desc_write(priv_tx->desc, 0, word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700659}
660
Ivo van Doorn181d6902008-02-05 16:42:23 -0500661static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700662{
Ivo van Doorn181d6902008-02-05 16:42:23 -0500663 struct queue_entry_priv_pci_rx *priv_rx;
664 struct queue_entry_priv_pci_tx *priv_tx;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700665 u32 reg;
666
667 /*
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700668 * Initialize registers.
669 */
670 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500671 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
672 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
673 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
674 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700675 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
676
Ivo van Doorn181d6902008-02-05 16:42:23 -0500677 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700678 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
Ivo van Doorn30b3a232008-02-17 17:33:24 +0100679 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
680 priv_tx->desc_dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700681 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
682
Ivo van Doorn181d6902008-02-05 16:42:23 -0500683 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700684 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
Ivo van Doorn30b3a232008-02-17 17:33:24 +0100685 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
686 priv_tx->desc_dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700687 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
688
Ivo van Doorn181d6902008-02-05 16:42:23 -0500689 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700690 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
Ivo van Doorn30b3a232008-02-17 17:33:24 +0100691 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
692 priv_tx->desc_dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700693 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
694
Ivo van Doorn181d6902008-02-05 16:42:23 -0500695 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700696 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
Ivo van Doorn30b3a232008-02-17 17:33:24 +0100697 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
698 priv_tx->desc_dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700699 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
700
701 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
702 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
Ivo van Doorn181d6902008-02-05 16:42:23 -0500703 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700704 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
705
Ivo van Doorn181d6902008-02-05 16:42:23 -0500706 priv_rx = rt2x00dev->rx->entries[0].priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700707 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
Ivo van Doorndac37d72008-03-09 22:48:46 +0100708 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700709 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
710
711 return 0;
712}
713
714static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
715{
716 u32 reg;
717
718 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
719 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
720 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
721 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
722
723 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
724 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
725 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
726 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
727 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
728
729 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
730 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
731 (rt2x00dev->rx->data_size / 128));
732 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
733
734 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
735
736 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
737 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
738 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
739 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
740 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
741 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
742
743 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
744 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
745 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
746 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
747 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
748 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
749 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
750 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
751
752 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
753
754 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
755 return -EBUSY;
756
757 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
758 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
759
760 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
761 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
762 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
763
764 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
765 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
766 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
767 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
768 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
769 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
770
771 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
772 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
773 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
774 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
775 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
776
777 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
778 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
779 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
780 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
781
782 /*
783 * We must clear the FCS and FIFO error count.
784 * These registers are cleared on read,
785 * so we may pass a useless variable to store the value.
786 */
787 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
788 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
789
790 return 0;
791}
792
793static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
794{
795 unsigned int i;
796 u16 eeprom;
797 u8 reg_id;
798 u8 value;
799
800 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
801 rt2400pci_bbp_read(rt2x00dev, 0, &value);
802 if ((value != 0xff) && (value != 0x00))
803 goto continue_csr_init;
804 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
805 udelay(REGISTER_BUSY_DELAY);
806 }
807
808 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
809 return -EACCES;
810
811continue_csr_init:
812 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
813 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
814 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
815 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
816 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
817 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
818 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
819 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
820 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
821 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
822 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
823 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
824 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
825 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
826
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700827 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
828 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
829
830 if (eeprom != 0xffff && eeprom != 0x0000) {
831 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
832 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700833 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
834 }
835 }
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700836
837 return 0;
838}
839
840/*
841 * Device state switch handlers.
842 */
843static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
844 enum dev_state state)
845{
846 u32 reg;
847
848 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
849 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
850 state == STATE_RADIO_RX_OFF);
851 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
852}
853
854static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
855 enum dev_state state)
856{
857 int mask = (state == STATE_RADIO_IRQ_OFF);
858 u32 reg;
859
860 /*
861 * When interrupts are being enabled, the interrupt registers
862 * should clear the register to assure a clean state.
863 */
864 if (state == STATE_RADIO_IRQ_ON) {
865 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
866 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
867 }
868
869 /*
870 * Only toggle the interrupts bits we are going to use.
871 * Non-checked interrupt bits are disabled by default.
872 */
873 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
874 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
875 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
876 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
877 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
878 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
879 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
880}
881
882static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
883{
884 /*
885 * Initialize all registers.
886 */
Ivo van Doorn181d6902008-02-05 16:42:23 -0500887 if (rt2400pci_init_queues(rt2x00dev) ||
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700888 rt2400pci_init_registers(rt2x00dev) ||
889 rt2400pci_init_bbp(rt2x00dev)) {
890 ERROR(rt2x00dev, "Register initialization failed.\n");
891 return -EIO;
892 }
893
894 /*
895 * Enable interrupts.
896 */
897 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
898
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700899 return 0;
900}
901
902static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
903{
904 u32 reg;
905
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700906 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
907
908 /*
909 * Disable synchronisation.
910 */
911 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
912
913 /*
914 * Cancel RX and TX.
915 */
916 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
917 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
918 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
919
920 /*
921 * Disable interrupts.
922 */
923 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
924}
925
926static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
927 enum dev_state state)
928{
929 u32 reg;
930 unsigned int i;
931 char put_to_sleep;
932 char bbp_state;
933 char rf_state;
934
935 put_to_sleep = (state != STATE_AWAKE);
936
937 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
938 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
939 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
940 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
941 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
942 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
943
944 /*
945 * Device is not guaranteed to be in the requested state yet.
946 * We must wait until the register indicates that the
947 * device has entered the correct state.
948 */
949 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
950 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
951 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
952 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
953 if (bbp_state == state && rf_state == state)
954 return 0;
955 msleep(10);
956 }
957
958 NOTICE(rt2x00dev, "Device failed to enter state %d, "
959 "current device state: bbp %d and rf %d.\n",
960 state, bbp_state, rf_state);
961
962 return -EBUSY;
963}
964
965static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
966 enum dev_state state)
967{
968 int retval = 0;
969
970 switch (state) {
971 case STATE_RADIO_ON:
972 retval = rt2400pci_enable_radio(rt2x00dev);
973 break;
974 case STATE_RADIO_OFF:
975 rt2400pci_disable_radio(rt2x00dev);
976 break;
977 case STATE_RADIO_RX_ON:
Ivo van Doorn61667d82008-02-25 23:15:05 +0100978 case STATE_RADIO_RX_ON_LINK:
979 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
980 break;
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700981 case STATE_RADIO_RX_OFF:
Ivo van Doorn61667d82008-02-25 23:15:05 +0100982 case STATE_RADIO_RX_OFF_LINK:
983 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
Ivo van Doorn95ea3622007-09-25 17:57:13 -0700984 break;
985 case STATE_DEEP_SLEEP:
986 case STATE_SLEEP:
987 case STATE_STANDBY:
988 case STATE_AWAKE:
989 retval = rt2400pci_set_state(rt2x00dev, state);
990 break;
991 default:
992 retval = -ENOTSUPP;
993 break;
994 }
995
996 return retval;
997}
998
999/*
1000 * TX descriptor initialization
1001 */
1002static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
Ivo van Doorndd3193e2008-01-06 23:41:10 +01001003 struct sk_buff *skb,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001004 struct txentry_desc *txdesc,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001005 struct ieee80211_tx_control *control)
1006{
Ivo van Doorn181d6902008-02-05 16:42:23 -05001007 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
Ivo van Doorndd3193e2008-01-06 23:41:10 +01001008 __le32 *txd = skbdesc->desc;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001009 u32 word;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001010
1011 /*
1012 * Start writing the descriptor words.
1013 */
1014 rt2x00_desc_read(txd, 2, &word);
Ivo van Doorndd3193e2008-01-06 23:41:10 +01001015 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001016 rt2x00_desc_write(txd, 2, word);
1017
1018 rt2x00_desc_read(txd, 3, &word);
Ivo van Doorn181d6902008-02-05 16:42:23 -05001019 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
Ivo van Doorn49da2602007-11-27 21:47:56 +01001020 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1021 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
Ivo van Doorn181d6902008-02-05 16:42:23 -05001022 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
Ivo van Doorn49da2602007-11-27 21:47:56 +01001023 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1024 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001025 rt2x00_desc_write(txd, 3, word);
1026
1027 rt2x00_desc_read(txd, 4, &word);
Ivo van Doorn181d6902008-02-05 16:42:23 -05001028 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
Ivo van Doorn49da2602007-11-27 21:47:56 +01001029 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1030 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
Ivo van Doorn181d6902008-02-05 16:42:23 -05001031 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
Ivo van Doorn49da2602007-11-27 21:47:56 +01001032 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1033 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001034 rt2x00_desc_write(txd, 4, word);
1035
1036 rt2x00_desc_read(txd, 0, &word);
1037 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1038 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1039 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001040 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001041 rt2x00_set_field32(&word, TXD_W0_ACK,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001042 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001043 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001044 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001045 rt2x00_set_field32(&word, TXD_W0_RTS,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001046 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1047 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001048 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1049 !!(control->flags &
1050 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1051 rt2x00_desc_write(txd, 0, word);
1052}
1053
1054/*
1055 * TX data initialization
1056 */
1057static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
Ivo van Doorne58c6ac2008-04-21 19:00:47 +02001058 const enum data_queue_qid queue)
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001059{
1060 u32 reg;
1061
Ivo van Doorne58c6ac2008-04-21 19:00:47 +02001062 if (queue == QID_BEACON) {
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001063 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1064 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
Ivo van Doorn8af244c2008-03-09 22:42:59 +01001065 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1066 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001067 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1068 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1069 }
1070 return;
1071 }
1072
1073 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
Ivo van Doorne58c6ac2008-04-21 19:00:47 +02001074 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1075 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1076 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001077 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1078}
1079
1080/*
1081 * RX control handlers
1082 */
Ivo van Doorn181d6902008-02-05 16:42:23 -05001083static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1084 struct rxdone_entry_desc *rxdesc)
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001085{
Ivo van Doorn181d6902008-02-05 16:42:23 -05001086 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001087 u32 word0;
1088 u32 word2;
Ivo van Doorn89993892008-03-09 22:49:04 +01001089 u32 word3;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001090
Ivo van Doorn181d6902008-02-05 16:42:23 -05001091 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1092 rt2x00_desc_read(priv_rx->desc, 2, &word2);
Ivo van Doorn89993892008-03-09 22:49:04 +01001093 rt2x00_desc_read(priv_rx->desc, 3, &word3);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001094
Ivo van Doorn181d6902008-02-05 16:42:23 -05001095 rxdesc->flags = 0;
Johannes Berg4150c572007-09-17 01:29:23 -04001096 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
Ivo van Doorn181d6902008-02-05 16:42:23 -05001097 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
Johannes Berg4150c572007-09-17 01:29:23 -04001098 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
Ivo van Doorn181d6902008-02-05 16:42:23 -05001099 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001100
1101 /*
1102 * Obtain the status about this packet.
Ivo van Doorn8ed09852008-03-10 00:30:44 +01001103 * The signal is the PLCP value, and needs to be stripped
1104 * of the preamble bit (0x08).
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001105 */
Ivo van Doorn8ed09852008-03-10 00:30:44 +01001106 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
Ivo van Doorn89993892008-03-09 22:49:04 +01001107 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
Ivo van Doorn181d6902008-02-05 16:42:23 -05001108 entry->queue->rt2x00dev->rssi_offset;
Ivo van Doorn181d6902008-02-05 16:42:23 -05001109 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
Ivo van Doorn19d30e02008-03-15 21:38:07 +01001110
1111 rxdesc->dev_flags = RXDONE_SIGNAL_PLCP;
1112 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1113 rxdesc->dev_flags |= RXDONE_MY_BSS;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001114}
1115
1116/*
1117 * Interrupt functions.
1118 */
Ivo van Doorn181d6902008-02-05 16:42:23 -05001119static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
Ivo van Doorne58c6ac2008-04-21 19:00:47 +02001120 const enum data_queue_qid queue_idx)
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001121{
Ivo van Doorn181d6902008-02-05 16:42:23 -05001122 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1123 struct queue_entry_priv_pci_tx *priv_tx;
1124 struct queue_entry *entry;
1125 struct txdone_entry_desc txdesc;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001126 u32 word;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001127
Ivo van Doorn181d6902008-02-05 16:42:23 -05001128 while (!rt2x00queue_empty(queue)) {
1129 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1130 priv_tx = entry->priv_data;
1131 rt2x00_desc_read(priv_tx->desc, 0, &word);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001132
1133 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1134 !rt2x00_get_field32(word, TXD_W0_VALID))
1135 break;
1136
1137 /*
1138 * Obtain the status about this packet.
1139 */
Ivo van Doornfb55f4d2008-05-10 13:42:06 +02001140 txdesc.flags = 0;
1141 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1142 case 0: /* Success */
1143 case 1: /* Success with retry */
1144 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1145 break;
1146 case 2: /* Failure, excessive retries */
1147 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1148 /* Don't break, this is a failed frame! */
1149 default: /* Failure */
1150 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1151 }
Ivo van Doorn181d6902008-02-05 16:42:23 -05001152 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001153
Ivo van Doorn181d6902008-02-05 16:42:23 -05001154 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001155 }
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001156}
1157
1158static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1159{
1160 struct rt2x00_dev *rt2x00dev = dev_instance;
1161 u32 reg;
1162
1163 /*
1164 * Get the interrupt sources & saved to local variable.
1165 * Write register value back to clear pending interrupts.
1166 */
1167 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1168 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1169
1170 if (!reg)
1171 return IRQ_NONE;
1172
1173 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1174 return IRQ_HANDLED;
1175
1176 /*
1177 * Handle interrupts, walk through all bits
1178 * and run the tasks, the bits are checked in order of
1179 * priority.
1180 */
1181
1182 /*
1183 * 1 - Beacon timer expired interrupt.
1184 */
1185 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1186 rt2x00lib_beacondone(rt2x00dev);
1187
1188 /*
1189 * 2 - Rx ring done interrupt.
1190 */
1191 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1192 rt2x00pci_rxdone(rt2x00dev);
1193
1194 /*
1195 * 3 - Atim ring transmit done interrupt.
1196 */
1197 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
Ivo van Doorne58c6ac2008-04-21 19:00:47 +02001198 rt2400pci_txdone(rt2x00dev, QID_ATIM);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001199
1200 /*
1201 * 4 - Priority ring transmit done interrupt.
1202 */
1203 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
Ivo van Doorne58c6ac2008-04-21 19:00:47 +02001204 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001205
1206 /*
1207 * 5 - Tx ring transmit done interrupt.
1208 */
1209 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
Ivo van Doorne58c6ac2008-04-21 19:00:47 +02001210 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001211
1212 return IRQ_HANDLED;
1213}
1214
1215/*
1216 * Device probe functions.
1217 */
1218static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1219{
1220 struct eeprom_93cx6 eeprom;
1221 u32 reg;
1222 u16 word;
1223 u8 *mac;
1224
1225 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1226
1227 eeprom.data = rt2x00dev;
1228 eeprom.register_read = rt2400pci_eepromregister_read;
1229 eeprom.register_write = rt2400pci_eepromregister_write;
1230 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1231 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1232 eeprom.reg_data_in = 0;
1233 eeprom.reg_data_out = 0;
1234 eeprom.reg_data_clock = 0;
1235 eeprom.reg_chip_select = 0;
1236
1237 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1238 EEPROM_SIZE / sizeof(u16));
1239
1240 /*
1241 * Start validation of the data that has been read.
1242 */
1243 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1244 if (!is_valid_ether_addr(mac)) {
Joe Perches0795af52007-10-03 17:59:30 -07001245 DECLARE_MAC_BUF(macbuf);
1246
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001247 random_ether_addr(mac);
Joe Perches0795af52007-10-03 17:59:30 -07001248 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001249 }
1250
1251 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1252 if (word == 0xffff) {
1253 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1254 return -EINVAL;
1255 }
1256
1257 return 0;
1258}
1259
1260static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1261{
1262 u32 reg;
1263 u16 value;
1264 u16 eeprom;
1265
1266 /*
1267 * Read EEPROM word for configuration.
1268 */
1269 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1270
1271 /*
1272 * Identify RF chipset.
1273 */
1274 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1275 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1276 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1277
1278 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1279 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1280 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1281 return -ENODEV;
1282 }
1283
1284 /*
1285 * Identify default antenna configuration.
1286 */
Ivo van Doornaddc81b2007-10-13 16:26:23 +02001287 rt2x00dev->default_ant.tx =
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001288 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
Ivo van Doornaddc81b2007-10-13 16:26:23 +02001289 rt2x00dev->default_ant.rx =
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001290 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1291
1292 /*
Ivo van Doornaddc81b2007-10-13 16:26:23 +02001293 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1294 * I am not 100% sure about this, but the legacy drivers do not
1295 * indicate antenna swapping in software is required when
1296 * diversity is enabled.
1297 */
1298 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1299 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1300 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1301 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1302
1303 /*
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001304 * Store led mode, for correct led behaviour.
1305 */
Ivo van Doorna9450b72008-02-03 15:53:40 +01001306#ifdef CONFIG_RT2400PCI_LEDS
1307 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1308
Ivo van Doorna2e1d522008-03-31 15:53:44 +02001309 rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
1310 rt2x00dev->led_radio.type = LED_TYPE_RADIO;
1311 rt2x00dev->led_radio.led_dev.brightness_set =
1312 rt2400pci_brightness_set;
1313 rt2x00dev->led_radio.led_dev.blink_set =
1314 rt2400pci_blink_set;
1315 rt2x00dev->led_radio.flags = LED_INITIALIZED;
1316
1317 if (value == LED_MODE_TXRX_ACTIVITY) {
1318 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
Ivo van Doorn61c2b682008-04-21 19:01:09 +02001319 rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY;
Ivo van Doorna2e1d522008-03-31 15:53:44 +02001320 rt2x00dev->led_qual.led_dev.brightness_set =
1321 rt2400pci_brightness_set;
1322 rt2x00dev->led_qual.led_dev.blink_set =
1323 rt2400pci_blink_set;
1324 rt2x00dev->led_qual.flags = LED_INITIALIZED;
Ivo van Doorna9450b72008-02-03 15:53:40 +01001325 }
1326#endif /* CONFIG_RT2400PCI_LEDS */
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001327
1328 /*
1329 * Detect if this device has an hardware controlled radio.
1330 */
Ivo van Doorn81873e92007-10-06 14:14:06 +02001331#ifdef CONFIG_RT2400PCI_RFKILL
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001332 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
Ivo van Doorn066cb632007-09-25 20:55:39 +02001333 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
Ivo van Doorn81873e92007-10-06 14:14:06 +02001334#endif /* CONFIG_RT2400PCI_RFKILL */
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001335
1336 /*
1337 * Check if the BBP tuning should be enabled.
1338 */
1339 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1340 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1341
1342 return 0;
1343}
1344
1345/*
1346 * RF value list for RF2420 & RF2421
1347 * Supports: 2.4 GHz
1348 */
1349static const struct rf_channel rf_vals_bg[] = {
1350 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1351 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1352 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1353 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1354 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1355 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1356 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1357 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1358 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1359 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1360 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1361 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1362 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1363 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1364};
1365
1366static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1367{
1368 struct hw_mode_spec *spec = &rt2x00dev->spec;
1369 u8 *txpower;
1370 unsigned int i;
1371
1372 /*
1373 * Initialize all hw fields.
1374 */
Bruno Randolf566bfe52008-05-08 19:15:40 +02001375 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1376 IEEE80211_HW_SIGNAL_DBM;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001377 rt2x00dev->hw->extra_tx_headroom = 0;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001378 rt2x00dev->hw->queues = 2;
1379
1380 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1381 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1382 rt2x00_eeprom_addr(rt2x00dev,
1383 EEPROM_MAC_ADDR_0));
1384
1385 /*
1386 * Convert tx_power array in eeprom.
1387 */
1388 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1389 for (i = 0; i < 14; i++)
1390 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1391
1392 /*
1393 * Initialize hw_mode information.
1394 */
Ivo van Doorn31562e82008-02-17 17:35:05 +01001395 spec->supported_bands = SUPPORT_BAND_2GHZ;
1396 spec->supported_rates = SUPPORT_RATE_CCK;
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001397 spec->tx_power_a = NULL;
1398 spec->tx_power_bg = txpower;
1399 spec->tx_power_default = DEFAULT_TXPOWER;
1400
1401 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1402 spec->channels = rf_vals_bg;
1403}
1404
1405static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1406{
1407 int retval;
1408
1409 /*
1410 * Allocate eeprom data.
1411 */
1412 retval = rt2400pci_validate_eeprom(rt2x00dev);
1413 if (retval)
1414 return retval;
1415
1416 retval = rt2400pci_init_eeprom(rt2x00dev);
1417 if (retval)
1418 return retval;
1419
1420 /*
1421 * Initialize hw specifications.
1422 */
1423 rt2400pci_probe_hw_mode(rt2x00dev);
1424
1425 /*
Ivo van Doorn181d6902008-02-05 16:42:23 -05001426 * This device requires the atim queue
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001427 */
Ivo van Doorn181d6902008-02-05 16:42:23 -05001428 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001429
1430 /*
1431 * Set the rssi offset.
1432 */
1433 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1434
1435 return 0;
1436}
1437
1438/*
1439 * IEEE80211 stack callback functions.
1440 */
1441static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1442 u32 short_retry, u32 long_retry)
1443{
1444 struct rt2x00_dev *rt2x00dev = hw->priv;
1445 u32 reg;
1446
1447 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1448 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1449 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1450 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1451
1452 return 0;
1453}
1454
Johannes Berge100bb62008-04-30 18:51:21 +02001455static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001456 const struct ieee80211_tx_queue_params *params)
1457{
1458 struct rt2x00_dev *rt2x00dev = hw->priv;
1459
1460 /*
1461 * We don't support variating cw_min and cw_max variables
1462 * per queue. So by default we only configure the TX queue,
1463 * and ignore all other configurations.
1464 */
Johannes Berge100bb62008-04-30 18:51:21 +02001465 if (queue != 0)
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001466 return -EINVAL;
1467
1468 if (rt2x00mac_conf_tx(hw, queue, params))
1469 return -EINVAL;
1470
1471 /*
1472 * Write configuration to register.
1473 */
Ivo van Doorn181d6902008-02-05 16:42:23 -05001474 rt2400pci_config_cw(rt2x00dev,
1475 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001476
1477 return 0;
1478}
1479
1480static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1481{
1482 struct rt2x00_dev *rt2x00dev = hw->priv;
1483 u64 tsf;
1484 u32 reg;
1485
1486 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1487 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1488 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1489 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1490
1491 return tsf;
1492}
1493
Ivo van Doorn5957da42008-02-03 15:54:57 +01001494static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1495 struct ieee80211_tx_control *control)
1496{
1497 struct rt2x00_dev *rt2x00dev = hw->priv;
1498 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1499 struct queue_entry_priv_pci_tx *priv_tx;
1500 struct skb_frame_desc *skbdesc;
Ivo van Doorn8af244c2008-03-09 22:42:59 +01001501 u32 reg;
Ivo van Doorn5957da42008-02-03 15:54:57 +01001502
1503 if (unlikely(!intf->beacon))
1504 return -ENOBUFS;
Ivo van Doorn5957da42008-02-03 15:54:57 +01001505 priv_tx = intf->beacon->priv_data;
1506
1507 /*
1508 * Fill in skb descriptor
1509 */
1510 skbdesc = get_skb_frame_desc(skb);
1511 memset(skbdesc, 0, sizeof(*skbdesc));
Ivo van Doornbaf26a72008-02-17 17:32:08 +01001512 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
Ivo van Doorn5957da42008-02-03 15:54:57 +01001513 skbdesc->data = skb->data;
1514 skbdesc->data_len = skb->len;
1515 skbdesc->desc = priv_tx->desc;
1516 skbdesc->desc_len = intf->beacon->queue->desc_size;
1517 skbdesc->entry = intf->beacon;
1518
1519 /*
Ivo van Doorn8af244c2008-03-09 22:42:59 +01001520 * Disable beaconing while we are reloading the beacon data,
1521 * otherwise we might be sending out invalid data.
1522 */
1523 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1524 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1525 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1526 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1527 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1528
1529 /*
Ivo van Doorn5957da42008-02-03 15:54:57 +01001530 * Enable beacon generation.
1531 * Write entire beacon with descriptor to register,
1532 * and kick the beacon generator.
1533 */
Ivo van Doorne58c6ac2008-04-21 19:00:47 +02001534 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
Ivo van Doorn5957da42008-02-03 15:54:57 +01001535 memcpy(priv_tx->data, skb->data, skb->len);
Ivo van Doorne58c6ac2008-04-21 19:00:47 +02001536 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
Ivo van Doorn5957da42008-02-03 15:54:57 +01001537
1538 return 0;
1539}
1540
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001541static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1542{
1543 struct rt2x00_dev *rt2x00dev = hw->priv;
1544 u32 reg;
1545
1546 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1547 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1548}
1549
1550static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1551 .tx = rt2x00mac_tx,
Johannes Berg4150c572007-09-17 01:29:23 -04001552 .start = rt2x00mac_start,
1553 .stop = rt2x00mac_stop,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001554 .add_interface = rt2x00mac_add_interface,
1555 .remove_interface = rt2x00mac_remove_interface,
1556 .config = rt2x00mac_config,
1557 .config_interface = rt2x00mac_config_interface,
Ivo van Doorn3a643d22008-03-25 14:13:18 +01001558 .configure_filter = rt2x00mac_configure_filter,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001559 .get_stats = rt2x00mac_get_stats,
1560 .set_retry_limit = rt2400pci_set_retry_limit,
Johannes Berg471b3ef2007-12-28 14:32:58 +01001561 .bss_info_changed = rt2x00mac_bss_info_changed,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001562 .conf_tx = rt2400pci_conf_tx,
1563 .get_tx_stats = rt2x00mac_get_tx_stats,
1564 .get_tsf = rt2400pci_get_tsf,
Ivo van Doorn5957da42008-02-03 15:54:57 +01001565 .beacon_update = rt2400pci_beacon_update,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001566 .tx_last_beacon = rt2400pci_tx_last_beacon,
1567};
1568
1569static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1570 .irq_handler = rt2400pci_interrupt,
1571 .probe_hw = rt2400pci_probe_hw,
1572 .initialize = rt2x00pci_initialize,
1573 .uninitialize = rt2x00pci_uninitialize,
Ivo van Doorn837e7f22008-01-06 23:41:45 +01001574 .init_rxentry = rt2400pci_init_rxentry,
1575 .init_txentry = rt2400pci_init_txentry,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001576 .set_device_state = rt2400pci_set_device_state,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001577 .rfkill_poll = rt2400pci_rfkill_poll,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001578 .link_stats = rt2400pci_link_stats,
1579 .reset_tuner = rt2400pci_reset_tuner,
1580 .link_tuner = rt2400pci_link_tuner,
1581 .write_tx_desc = rt2400pci_write_tx_desc,
1582 .write_tx_data = rt2x00pci_write_tx_data,
1583 .kick_tx_queue = rt2400pci_kick_tx_queue,
1584 .fill_rxdone = rt2400pci_fill_rxdone,
Ivo van Doorn3a643d22008-03-25 14:13:18 +01001585 .config_filter = rt2400pci_config_filter,
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01001586 .config_intf = rt2400pci_config_intf,
Ivo van Doorn72810372008-03-09 22:46:18 +01001587 .config_erp = rt2400pci_config_erp,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001588 .config = rt2400pci_config,
1589};
1590
Ivo van Doorn181d6902008-02-05 16:42:23 -05001591static const struct data_queue_desc rt2400pci_queue_rx = {
1592 .entry_num = RX_ENTRIES,
1593 .data_size = DATA_FRAME_SIZE,
1594 .desc_size = RXD_DESC_SIZE,
1595 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1596};
1597
1598static const struct data_queue_desc rt2400pci_queue_tx = {
1599 .entry_num = TX_ENTRIES,
1600 .data_size = DATA_FRAME_SIZE,
1601 .desc_size = TXD_DESC_SIZE,
1602 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1603};
1604
1605static const struct data_queue_desc rt2400pci_queue_bcn = {
1606 .entry_num = BEACON_ENTRIES,
1607 .data_size = MGMT_FRAME_SIZE,
1608 .desc_size = TXD_DESC_SIZE,
1609 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1610};
1611
1612static const struct data_queue_desc rt2400pci_queue_atim = {
1613 .entry_num = ATIM_ENTRIES,
1614 .data_size = DATA_FRAME_SIZE,
1615 .desc_size = TXD_DESC_SIZE,
1616 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1617};
1618
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001619static const struct rt2x00_ops rt2400pci_ops = {
Ivo van Doorn23601572007-11-27 21:47:34 +01001620 .name = KBUILD_MODNAME,
Ivo van Doorn6bb40dd2008-02-03 15:49:59 +01001621 .max_sta_intf = 1,
1622 .max_ap_intf = 1,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001623 .eeprom_size = EEPROM_SIZE,
1624 .rf_size = RF_SIZE,
Ivo van Doorn181d6902008-02-05 16:42:23 -05001625 .rx = &rt2400pci_queue_rx,
1626 .tx = &rt2400pci_queue_tx,
1627 .bcn = &rt2400pci_queue_bcn,
1628 .atim = &rt2400pci_queue_atim,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001629 .lib = &rt2400pci_rt2x00_ops,
1630 .hw = &rt2400pci_mac80211_ops,
1631#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1632 .debugfs = &rt2400pci_rt2x00debug,
1633#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1634};
1635
1636/*
1637 * RT2400pci module information.
1638 */
1639static struct pci_device_id rt2400pci_device_table[] = {
1640 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1641 { 0, }
1642};
1643
1644MODULE_AUTHOR(DRV_PROJECT);
1645MODULE_VERSION(DRV_VERSION);
1646MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1647MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1648MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1649MODULE_LICENSE("GPL");
1650
1651static struct pci_driver rt2400pci_driver = {
Ivo van Doorn23601572007-11-27 21:47:34 +01001652 .name = KBUILD_MODNAME,
Ivo van Doorn95ea3622007-09-25 17:57:13 -07001653 .id_table = rt2400pci_device_table,
1654 .probe = rt2x00pci_probe,
1655 .remove = __devexit_p(rt2x00pci_remove),
1656 .suspend = rt2x00pci_suspend,
1657 .resume = rt2x00pci_resume,
1658};
1659
1660static int __init rt2400pci_init(void)
1661{
1662 return pci_register_driver(&rt2400pci_driver);
1663}
1664
1665static void __exit rt2400pci_exit(void)
1666{
1667 pci_unregister_driver(&rt2400pci_driver);
1668}
1669
1670module_init(rt2400pci_init);
1671module_exit(rt2400pci_exit);