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gerrit-public.fairphone.software / fp2-dev / platform / dalvik / 160c5e674ff581736dcae27d2998cd294eaa294a / . / vm / compiler / codegen / armv5te / Armv5teLIR.h
blob: c1dbf33dbb7600f37527f7902425ac1629b2ba42 [file] [log] [blame]
Ben Chengba4fc8b2009-06-01 13:00:29 -0700[diff] [blame]1/*
2 * Copyright (C) 2009 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "Dalvik.h"
18#include "compiler/CompilerInternals.h"
19
20#ifndef _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_H
21#define _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_H
22
23/*
24 * r0, r1, r2, r3, and r7 are always scratch
25 * r4PC is scratch if used solely in the compiled land. Otherwise it holds the
26 * Dalvik PC.
27 * rFP holds the current frame pointer
28 * rGLUE holds &InterpState
29 */
30typedef enum NativeRegisterPool {
31 r0 = 0,
32 r1 = 1,
33 r2 = 2,
34 r3 = 3,
35 r4PC = 4,
36 rFP = 5,
37 rGLUE = 6,
38 r7 = 7,
Bill Buzbee6e963e12009-06-17 16:56:19 -0700[diff] [blame]39 r8 = 8,
40 r9 = 9,
41 r10 = 10,
42 r11 = 11,
43 r12 = 12,
44 r13 = 13,
45 rlr = 14,
46 rpc = 15
Ben Chengba4fc8b2009-06-01 13:00:29 -0700[diff] [blame]47} NativeRegisterPool;
48
Bill Buzbee6e963e12009-06-17 16:56:19 -0700[diff] [blame]49/* Mask to convert high reg to low for Thumb */
50#define THUMB_REG_MASK 0x7
51
Ben Chengba4fc8b2009-06-01 13:00:29 -0700[diff] [blame]52/* Thumb condition encodings */
53typedef enum Armv5teConditionCode {
54 ARM_COND_EQ = 0x0, /* 0000 */
55 ARM_COND_NE = 0x1, /* 0001 */
56 ARM_COND_LT = 0xb, /* 1011 */
57 ARM_COND_GE = 0xa, /* 1010 */
58 ARM_COND_GT = 0xc, /* 1100 */
59 ARM_COND_LE = 0xd, /* 1101 */
60 ARM_COND_CS = 0x2, /* 0010 */
61 ARM_COND_MI = 0x4, /* 0100 */
62} Armv5teConditionCode;
63
64#define isPseudoOpCode(opCode) ((int)(opCode) < 0)
65
66/*
67 * The following enum defines the list of supported Thumb instructions by the
68 * assembler. Their corresponding snippet positions will be defined in
69 * Assemble.c.
70 */
71typedef enum Armv5teOpCode {
Ben Cheng38329f52009-07-07 14:19:20 -0700[diff] [blame]72 ARMV5TE_PSEUDO_TARGET_LABEL = -11,
73 ARMV5TE_PSEUDO_CHAINING_CELL_HOT = -10,
74 ARMV5TE_PSEUDO_CHAINING_CELL_INVOKE_PREDICTED = -9,
75 ARMV5TE_PSEUDO_CHAINING_CELL_INVOKE_SINGLETON = -8,
Ben Cheng1efc9c52009-06-08 18:25:27 -0700[diff] [blame]76 ARMV5TE_PSEUDO_CHAINING_CELL_NORMAL = -7,
Ben Chengba4fc8b2009-06-01 13:00:29 -0700[diff] [blame]77 ARMV5TE_PSEUDO_DALVIK_BYTECODE_BOUNDARY = -6,
78 ARMV5TE_PSEUDO_ALIGN4 = -5,
79 ARMV5TE_PSEUDO_PC_RECONSTRUCTION_CELL = -4,
80 ARMV5TE_PSEUDO_PC_RECONSTRUCTION_BLOCK_LABEL = -3,
81 ARMV5TE_PSEUDO_EH_BLOCK_LABEL = -2,
82 ARMV5TE_PSEUDO_NORMAL_BLOCK_LABEL = -1,
83 /************************************************************************/
84 ARMV5TE_16BIT_DATA, /* DATA [0] rd[15..0] */
85 ARMV5TE_ADC, /* adc [0100000101] rm[5..3] rd[2..0] */
86 ARMV5TE_ADD_RRI3, /* add(1) [0001110] imm_3[8..6] rn[5..3] rd[2..0]*/
87 ARMV5TE_ADD_RI8, /* add(2) [00110] rd[10..8] imm_8[7..0] */
88 ARMV5TE_ADD_RRR, /* add(3) [0001100] rm[8..6] rn[5..3] rd[2..0] */
89 ARMV5TE_ADD_RR_LH, /* add(4) [01000100] H12[01] rm[5..3] rd[2..0] */
90 ARMV5TE_ADD_RR_HL, /* add(4) [01001000] H12[10] rm[5..3] rd[2..0] */
91 ARMV5TE_ADD_RR_HH, /* add(4) [01001100] H12[11] rm[5..3] rd[2..0] */
92 ARMV5TE_ADD_PC_REL, /* add(5) [10100] rd[10..8] imm_8[7..0] */
93 ARMV5TE_ADD_SP_REL, /* add(6) [10101] rd[10..8] imm_8[7..0] */
94 ARMV5TE_ADD_SPI7, /* add(7) [101100000] imm_7[6..0] */
95 ARMV5TE_AND_RR, /* and [0100000000] rm[5..3] rd[2..0] */
96 ARMV5TE_ASR, /* asr(1) [00010] imm_5[10..6] rm[5..3] rd[2..0] */
97 ARMV5TE_ASRV, /* asr(2) [0100000100] rs[5..3] rd[2..0] */
98 ARMV5TE_B_COND, /* b(1) [1101] cond[11..8] offset_8[7..0] */
99 ARMV5TE_B_UNCOND, /* b(2) [11100] offset_11[10..0] */
100 ARMV5TE_BIC, /* bic [0100001110] rm[5..3] rd[2..0] */
101 ARMV5TE_BKPT, /* bkpt [10111110] imm_8[7..0] */
102 ARMV5TE_BLX_1, /* blx(1) [111] H[10] offset_11[10..0] */
103 ARMV5TE_BLX_2, /* blx(1) [111] H[01] offset_11[10..0] */
104 ARMV5TE_BL_1, /* blx(1) [111] H[10] offset_11[10..0] */
105 ARMV5TE_BL_2, /* blx(1) [111] H[11] offset_11[10..0] */
106 ARMV5TE_BLX_R, /* blx(2) [010001111] H2[6..6] rm[5..3] SBZ[000] */
107 ARMV5TE_BX, /* bx [010001110] H2[6..6] rm[5..3] SBZ[000] */
108 ARMV5TE_CMN, /* cmn [0100001011] rm[5..3] rd[2..0] */
109 ARMV5TE_CMP_RI8, /* cmp(1) [00101] rn[10..8] imm_8[7..0] */
110 ARMV5TE_CMP_RR, /* cmp(2) [0100001010] rm[5..3] rd[2..0] */
111 ARMV5TE_CMP_LH, /* cmp(3) [01000101] H12[01] rm[5..3] rd[2..0] */
112 ARMV5TE_CMP_HL, /* cmp(3) [01000110] H12[10] rm[5..3] rd[2..0] */
113 ARMV5TE_CMP_HH, /* cmp(3) [01000111] H12[11] rm[5..3] rd[2..0] */
114 ARMV5TE_EOR, /* eor [0100000001] rm[5..3] rd[2..0] */
115 ARMV5TE_LDMIA, /* ldmia [11001] rn[10..8] reglist [7..0] */
116 ARMV5TE_LDR_RRI5, /* ldr(1) [01101] imm_5[10..6] rn[5..3] rd[2..0] */
117 ARMV5TE_LDR_RRR, /* ldr(2) [0101100] rm[8..6] rn[5..3] rd[2..0] */
118 ARMV5TE_LDR_PC_REL, /* ldr(3) [01001] rd[10..8] imm_8[7..0] */
119 ARMV5TE_LDR_SP_REL, /* ldr(4) [10011] rd[10..8] imm_8[7..0] */
120 ARMV5TE_LDRB_RRI5, /* ldrb(1) [01111] imm_5[10..6] rn[5..3] rd[2..0] */
121 ARMV5TE_LDRB_RRR, /* ldrb(2) [0101110] rm[8..6] rn[5..3] rd[2..0] */
122 ARMV5TE_LDRH_RRI5, /* ldrh(1) [10001] imm_5[10..6] rn[5..3] rd[2..0] */
123 ARMV5TE_LDRH_RRR, /* ldrh(2) [0101101] rm[8..6] rn[5..3] rd[2..0] */
124 ARMV5TE_LDRSB_RRR, /* ldrsb [0101011] rm[8..6] rn[5..3] rd[2..0] */
125 ARMV5TE_LDRSH_RRR, /* ldrsh [0101111] rm[8..6] rn[5..3] rd[2..0] */
126 ARMV5TE_LSL, /* lsl(1) [00000] imm_5[10..6] rm[5..3] rd[2..0] */
127 ARMV5TE_LSLV, /* lsl(2) [0100000010] rs[5..3] rd[2..0] */
128 ARMV5TE_LSR, /* lsr(1) [00001] imm_5[10..6] rm[5..3] rd[2..0] */
129 ARMV5TE_LSRV, /* lsr(2) [0100000011] rs[5..3] rd[2..0] */
130 ARMV5TE_MOV_IMM, /* mov(1) [00100] rd[10..8] imm_8[7..0] */
131 ARMV5TE_MOV_RR, /* mov(2) [0001110000] rn[5..3] rd[2..0] */
Ben Cheng38329f52009-07-07 14:19:20 -0700[diff] [blame]132 ARMV5TE_MOV_RR_H2H, /* mov(3) [01000111] H12[11] rm[5..3] rd[2..0] */
133 ARMV5TE_MOV_RR_H2L, /* mov(3) [01000110] H12[01] rm[5..3] rd[2..0] */
134 ARMV5TE_MOV_RR_L2H, /* mov(3) [01000101] H12[10] rm[5..3] rd[2..0] */
Ben Chengba4fc8b2009-06-01 13:00:29 -0700[diff] [blame]135 ARMV5TE_MUL, /* mul [0100001101] rm[5..3] rd[2..0] */
136 ARMV5TE_MVN, /* mvn [0100001111] rm[5..3] rd[2..0] */
137 ARMV5TE_NEG, /* neg [0100001001] rm[5..3] rd[2..0] */
138 ARMV5TE_ORR, /* orr [0100001100] rm[5..3] rd[2..0] */
139 ARMV5TE_POP, /* pop [1011110] r[8..8] rl[7..0] */
140 ARMV5TE_PUSH, /* push [1011010] r[8..8] rl[7..0] */
141 ARMV5TE_ROR, /* ror [0100000111] rs[5..3] rd[2..0] */
142 ARMV5TE_SBC, /* sbc [0100000110] rm[5..3] rd[2..0] */
143 ARMV5TE_STMIA, /* stmia [11000] rn[10..8] reglist [7.. 0] */
144 ARMV5TE_STR_RRI5, /* str(1) [01100] imm_5[10..6] rn[5..3] rd[2..0] */
145 ARMV5TE_STR_RRR, /* str(2) [0101000] rm[8..6] rn[5..3] rd[2..0] */
146 ARMV5TE_STR_SP_REL, /* str(3) [10010] rd[10..8] imm_8[7..0] */
147 ARMV5TE_STRB_RRI5, /* strb(1) [01110] imm_5[10..6] rn[5..3] rd[2..0] */
148 ARMV5TE_STRB_RRR, /* strb(2) [0101010] rm[8..6] rn[5..3] rd[2..0] */
149 ARMV5TE_STRH_RRI5, /* strh(1) [10000] imm_5[10..6] rn[5..3] rd[2..0] */
150 ARMV5TE_STRH_RRR, /* strh(2) [0101001] rm[8..6] rn[5..3] rd[2..0] */
151 ARMV5TE_SUB_RRI3, /* sub(1) [0001111] imm_3[8..6] rn[5..3] rd[2..0]*/
152 ARMV5TE_SUB_RI8, /* sub(2) [00111] rd[10..8] imm_8[7..0] */
153 ARMV5TE_SUB_RRR, /* sub(3) [0001101] rm[8..6] rn[5..3] rd[2..0] */
154 ARMV5TE_SUB_SPI7, /* sub(4) [101100001] imm_7[6..0] */
155 ARMV5TE_SWI, /* swi [11011111] imm_8[7..0] */
156 ARMV5TE_TST, /* tst [0100001000] rm[5..3] rn[2..0] */
157 ARMV5TE_LAST,
158} Armv5teOpCode;
159
Ben Chenge9695e52009-06-16 16:11:47 -0700[diff] [blame]160/* Bit flags describing the behavior of each native opcode */
161typedef enum Armv5teOpFeatureFlags {
162 IS_BRANCH = 1 << 1,
163 CLOBBER_DEST = 1 << 2,
164 CLOBBER_SRC1 = 1 << 3,
165 NO_OPERAND = 1 << 4,
166 IS_UNARY_OP = 1 << 5,
167 IS_BINARY_OP = 1 << 6,
168 IS_TERTIARY_OP = 1 << 7,
169} Armv5teOpFeatureFlags;
170
171/* Struct used to define the snippet positions for each Thumb opcode */
Ben Chengba4fc8b2009-06-01 13:00:29 -0700[diff] [blame]172typedef struct Armv5teEncodingMap {
173 short skeleton;
174 struct {
175 int end;
176 int start;
177 } fieldLoc[3];
178 Armv5teOpCode opCode;
Ben Chenge9695e52009-06-16 16:11:47 -0700[diff] [blame]179 int flags;
Ben Chengba4fc8b2009-06-01 13:00:29 -0700[diff] [blame]180 char *name;
181 char* fmt;
182} Armv5teEncodingMap;
183
184extern Armv5teEncodingMap EncodingMap[ARMV5TE_LAST];
185
186/*
187 * Each instance of this struct holds a pseudo or real LIR instruction:
188 * - pesudo ones (eg labels and marks) and will be discarded by the assembler.
189 * - real ones will e assembled into Thumb instructions.
190 */
191typedef struct Armv5teLIR {
192 LIR generic;
193 Armv5teOpCode opCode;
Ben Chenge9695e52009-06-16 16:11:47 -0700[diff] [blame]194 int operands[3]; // [0..2] = [dest, src1, src2]
195 bool isNop; // LIR is optimized away
196 int age; // default is 0, set lazily by the optimizer
Ben Chengba4fc8b2009-06-01 13:00:29 -0700[diff] [blame]197} Armv5teLIR;
198
Ben Cheng38329f52009-07-07 14:19:20 -0700[diff] [blame]199/* Chain cell for predicted method invocation */
200typedef struct PredictedChainingCell {
201 u4 branch; /* Branch to chained destination */
202 const ClassObject *clazz; /* key #1 for prediction */
203 const Method *method; /* key #2 to lookup native PC from dalvik PC */
204 u4 counter; /* counter to patch the chaining cell */
205} PredictedChainingCell;
206
207/* Init values when a predicted chain is initially assembled */
208#define PREDICTED_CHAIN_BX_PAIR_INIT 0
209#define PREDICTED_CHAIN_CLAZZ_INIT 0
210#define PREDICTED_CHAIN_METHOD_INIT 0
211#define PREDICTED_CHAIN_COUNTER_INIT 0
212
213/* Used when the callee is not compiled yet */
214#define PREDICTED_CHAIN_COUNTER_DELAY 16
215
216/* Rechain after this many mis-predictions have happened */
217#define PREDICTED_CHAIN_COUNTER_RECHAIN 1024
218
219/* Used if the resolved callee is a native method */
220#define PREDICTED_CHAIN_COUNTER_AVOID 0x7fffffff
221
Ben Chengba4fc8b2009-06-01 13:00:29 -0700[diff] [blame]222/* Utility macros to traverse the LIR/Armv5teLIR list */
223#define NEXT_LIR(lir) ((Armv5teLIR *) lir->generic.next)
224#define PREV_LIR(lir) ((Armv5teLIR *) lir->generic.prev)
225
226#define NEXT_LIR_LVALUE(lir) (lir)->generic.next
227#define PREV_LIR_LVALUE(lir) (lir)->generic.prev
228
Ben Cheng1efc9c52009-06-08 18:25:27 -0700[diff] [blame]229#define CHAIN_CELL_OFFSET_TAG 0xcdab
230
Bill Buzbeed45ba372009-06-15 17:00:57 -0700[diff] [blame]231/* Create the TemplateOpcode enum */
232#define JIT_TEMPLATE(X) TEMPLATE_##X,
233typedef enum {
234#include "../../template/armv5te/TemplateOpList.h"
235/*
236 * For example,
237 * TEMPLATE_CMP_LONG,
238 * TEMPLATE_RETURN,
239 * ...
240 */
241 TEMPLATE_LAST_MARK,
242} TemplateOpCode;
243#undef JIT_TEMPLATE
244
Ben Chengba4fc8b2009-06-01 13:00:29 -0700[diff] [blame]245#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_H */