Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1 | /* radeon_state.c -- State support for Radeon -*- linux-c -*- |
| 2 | * |
| 3 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 21 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 22 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 23 | * DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | * Authors: |
David Dawes | 0e5b8d7 | 2001-03-19 17:45:52 +0000 | [diff] [blame] | 26 | * Gareth Hughes <gareth@valinux.com> |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 27 | * Kevin E. Martin <martin@valinux.com> |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 28 | */ |
| 29 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 30 | #include "drmP.h" |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 31 | #include "drm.h" |
Michel Daenzer | 5e1b8ed | 2002-10-29 13:49:26 +0000 | [diff] [blame] | 32 | #include "drm_sarea.h" |
Jens Owen | 3903e5a | 2002-04-09 21:54:56 +0000 | [diff] [blame] | 33 | #include "radeon_drm.h" |
| 34 | #include "radeon_drv.h" |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 35 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 36 | /* ================================================================ |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 37 | * Helper functions for client state checking and fixup |
| 38 | */ |
| 39 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 40 | static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * |
| 41 | dev_priv, |
| 42 | drm_file_t * filp_priv, |
| 43 | u32 * offset) |
| 44 | { |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 45 | u32 off = *offset; |
Dave Airlie | d4dbf45 | 2004-08-24 11:15:53 +0000 | [diff] [blame] | 46 | struct drm_radeon_driver_file_fields *radeon_priv; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 47 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 48 | if (off >= dev_priv->fb_location && |
| 49 | off < (dev_priv->gart_vm_start + dev_priv->gart_size)) |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 50 | return 0; |
| 51 | |
Dave Airlie | d4dbf45 | 2004-08-24 11:15:53 +0000 | [diff] [blame] | 52 | radeon_priv = filp_priv->driver_priv; |
| 53 | |
| 54 | off += radeon_priv->radeon_fb_delta; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 55 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 56 | DRM_DEBUG("offset fixed up to 0x%x\n", off); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 57 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 58 | if (off < dev_priv->fb_location || |
| 59 | off >= (dev_priv->gart_vm_start + dev_priv->gart_size)) |
| 60 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 61 | |
| 62 | *offset = off; |
| 63 | |
| 64 | return 0; |
| 65 | } |
| 66 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 67 | static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * |
| 68 | dev_priv, |
| 69 | drm_file_t * filp_priv, |
| 70 | int id, u32 __user * data) |
| 71 | { |
| 72 | switch (id) { |
Michel Daenzer | 0dea4de | 2004-01-10 20:59:16 +0000 | [diff] [blame] | 73 | |
| 74 | case RADEON_EMIT_PP_MISC: |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 75 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
| 76 | &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 77 | DRM_ERROR("Invalid depth buffer offset\n"); |
| 78 | return DRM_ERR(EINVAL); |
Michel Daenzer | 0dea4de | 2004-01-10 20:59:16 +0000 | [diff] [blame] | 79 | } |
| 80 | break; |
| 81 | |
| 82 | case RADEON_EMIT_PP_CNTL: |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 83 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
| 84 | &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 85 | DRM_ERROR("Invalid colour buffer offset\n"); |
| 86 | return DRM_ERR(EINVAL); |
Michel Daenzer | 0dea4de | 2004-01-10 20:59:16 +0000 | [diff] [blame] | 87 | } |
| 88 | break; |
| 89 | |
| 90 | case R200_EMIT_PP_TXOFFSET_0: |
| 91 | case R200_EMIT_PP_TXOFFSET_1: |
| 92 | case R200_EMIT_PP_TXOFFSET_2: |
| 93 | case R200_EMIT_PP_TXOFFSET_3: |
| 94 | case R200_EMIT_PP_TXOFFSET_4: |
| 95 | case R200_EMIT_PP_TXOFFSET_5: |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 96 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
| 97 | &data[0])) { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 98 | DRM_ERROR("Invalid R200 texture offset\n"); |
| 99 | return DRM_ERR(EINVAL); |
Michel Daenzer | 0dea4de | 2004-01-10 20:59:16 +0000 | [diff] [blame] | 100 | } |
| 101 | break; |
| 102 | |
| 103 | case RADEON_EMIT_PP_TXFILTER_0: |
| 104 | case RADEON_EMIT_PP_TXFILTER_1: |
| 105 | case RADEON_EMIT_PP_TXFILTER_2: |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 106 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
| 107 | &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 108 | DRM_ERROR("Invalid R100 texture offset\n"); |
| 109 | return DRM_ERR(EINVAL); |
Michel Daenzer | 0dea4de | 2004-01-10 20:59:16 +0000 | [diff] [blame] | 110 | } |
| 111 | break; |
| 112 | |
| 113 | case R200_EMIT_PP_CUBIC_OFFSETS_0: |
| 114 | case R200_EMIT_PP_CUBIC_OFFSETS_1: |
| 115 | case R200_EMIT_PP_CUBIC_OFFSETS_2: |
| 116 | case R200_EMIT_PP_CUBIC_OFFSETS_3: |
| 117 | case R200_EMIT_PP_CUBIC_OFFSETS_4: |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 118 | case R200_EMIT_PP_CUBIC_OFFSETS_5:{ |
| 119 | int i; |
| 120 | for (i = 0; i < 5; i++) { |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 121 | if (radeon_check_and_fixup_offset(dev_priv, |
| 122 | filp_priv, |
| 123 | &data[i])) { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 124 | DRM_ERROR |
| 125 | ("Invalid R200 cubic texture offset\n"); |
| 126 | return DRM_ERR(EINVAL); |
| 127 | } |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 128 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 129 | break; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 130 | } |
Michel Daenzer | 0dea4de | 2004-01-10 20:59:16 +0000 | [diff] [blame] | 131 | |
Roland Scheidegger | 732cdc5 | 2005-02-10 19:22:43 +0000 | [diff] [blame] | 132 | case RADEON_EMIT_PP_CUBIC_OFFSETS_T0: |
| 133 | case RADEON_EMIT_PP_CUBIC_OFFSETS_T1: |
| 134 | case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{ |
| 135 | int i; |
| 136 | for (i = 0; i < 5; i++) { |
| 137 | if (radeon_check_and_fixup_offset(dev_priv, |
| 138 | filp_priv, |
| 139 | &data[i])) { |
| 140 | DRM_ERROR |
| 141 | ("Invalid R100 cubic texture offset\n"); |
| 142 | return DRM_ERR(EINVAL); |
| 143 | } |
| 144 | } |
| 145 | } |
| 146 | break; |
| 147 | |
Michel Daenzer | 0dea4de | 2004-01-10 20:59:16 +0000 | [diff] [blame] | 148 | case RADEON_EMIT_RB3D_COLORPITCH: |
| 149 | case RADEON_EMIT_RE_LINE_PATTERN: |
| 150 | case RADEON_EMIT_SE_LINE_WIDTH: |
| 151 | case RADEON_EMIT_PP_LUM_MATRIX: |
| 152 | case RADEON_EMIT_PP_ROT_MATRIX_0: |
| 153 | case RADEON_EMIT_RB3D_STENCILREFMASK: |
| 154 | case RADEON_EMIT_SE_VPORT_XSCALE: |
| 155 | case RADEON_EMIT_SE_CNTL: |
| 156 | case RADEON_EMIT_SE_CNTL_STATUS: |
| 157 | case RADEON_EMIT_RE_MISC: |
| 158 | case RADEON_EMIT_PP_BORDER_COLOR_0: |
| 159 | case RADEON_EMIT_PP_BORDER_COLOR_1: |
| 160 | case RADEON_EMIT_PP_BORDER_COLOR_2: |
| 161 | case RADEON_EMIT_SE_ZBIAS_FACTOR: |
| 162 | case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT: |
| 163 | case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED: |
| 164 | case R200_EMIT_PP_TXCBLEND_0: |
| 165 | case R200_EMIT_PP_TXCBLEND_1: |
| 166 | case R200_EMIT_PP_TXCBLEND_2: |
| 167 | case R200_EMIT_PP_TXCBLEND_3: |
| 168 | case R200_EMIT_PP_TXCBLEND_4: |
| 169 | case R200_EMIT_PP_TXCBLEND_5: |
| 170 | case R200_EMIT_PP_TXCBLEND_6: |
| 171 | case R200_EMIT_PP_TXCBLEND_7: |
| 172 | case R200_EMIT_TCL_LIGHT_MODEL_CTL_0: |
| 173 | case R200_EMIT_TFACTOR_0: |
| 174 | case R200_EMIT_VTX_FMT_0: |
| 175 | case R200_EMIT_VAP_CTL: |
| 176 | case R200_EMIT_MATRIX_SELECT_0: |
| 177 | case R200_EMIT_TEX_PROC_CTL_2: |
| 178 | case R200_EMIT_TCL_UCP_VERT_BLEND_CTL: |
| 179 | case R200_EMIT_PP_TXFILTER_0: |
| 180 | case R200_EMIT_PP_TXFILTER_1: |
| 181 | case R200_EMIT_PP_TXFILTER_2: |
| 182 | case R200_EMIT_PP_TXFILTER_3: |
| 183 | case R200_EMIT_PP_TXFILTER_4: |
| 184 | case R200_EMIT_PP_TXFILTER_5: |
| 185 | case R200_EMIT_VTE_CNTL: |
| 186 | case R200_EMIT_OUTPUT_VTX_COMP_SEL: |
| 187 | case R200_EMIT_PP_TAM_DEBUG3: |
| 188 | case R200_EMIT_PP_CNTL_X: |
| 189 | case R200_EMIT_RB3D_DEPTHXY_OFFSET: |
| 190 | case R200_EMIT_RE_AUX_SCISSOR_CNTL: |
| 191 | case R200_EMIT_RE_SCISSOR_TL_0: |
| 192 | case R200_EMIT_RE_SCISSOR_TL_1: |
| 193 | case R200_EMIT_RE_SCISSOR_TL_2: |
| 194 | case R200_EMIT_SE_VAP_CNTL_STATUS: |
| 195 | case R200_EMIT_SE_VTX_STATE_CNTL: |
| 196 | case R200_EMIT_RE_POINTSIZE: |
| 197 | case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0: |
| 198 | case R200_EMIT_PP_CUBIC_FACES_0: |
| 199 | case R200_EMIT_PP_CUBIC_FACES_1: |
| 200 | case R200_EMIT_PP_CUBIC_FACES_2: |
| 201 | case R200_EMIT_PP_CUBIC_FACES_3: |
| 202 | case R200_EMIT_PP_CUBIC_FACES_4: |
| 203 | case R200_EMIT_PP_CUBIC_FACES_5: |
| 204 | case RADEON_EMIT_PP_TEX_SIZE_0: |
| 205 | case RADEON_EMIT_PP_TEX_SIZE_1: |
| 206 | case RADEON_EMIT_PP_TEX_SIZE_2: |
Roland Scheidegger | 43c244e | 2004-05-18 23:30:46 +0000 | [diff] [blame] | 207 | case R200_EMIT_RB3D_BLENDCOLOR: |
Roland Scheidegger | c4a87c6 | 2004-12-08 16:43:00 +0000 | [diff] [blame] | 208 | case R200_EMIT_TCL_POINT_SPRITE_CNTL: |
Roland Scheidegger | 732cdc5 | 2005-02-10 19:22:43 +0000 | [diff] [blame] | 209 | case RADEON_EMIT_PP_CUBIC_FACES_0: |
| 210 | case RADEON_EMIT_PP_CUBIC_FACES_1: |
| 211 | case RADEON_EMIT_PP_CUBIC_FACES_2: |
Roland Scheidegger | 3456392 | 2005-03-15 22:12:30 +0000 | [diff] [blame] | 212 | case R200_EMIT_PP_TRI_PERF_CNTL: |
Michel Daenzer | 0dea4de | 2004-01-10 20:59:16 +0000 | [diff] [blame] | 213 | /* These packets don't contain memory offsets */ |
| 214 | break; |
| 215 | |
| 216 | default: |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 217 | DRM_ERROR("Unknown state packet ID %d\n", id); |
| 218 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 219 | } |
| 220 | |
| 221 | return 0; |
| 222 | } |
| 223 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 224 | static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * |
| 225 | dev_priv, |
| 226 | drm_file_t * filp_priv, |
| 227 | drm_radeon_cmd_buffer_t * |
| 228 | cmdbuf, |
| 229 | unsigned int *cmdsz) |
| 230 | { |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 231 | u32 *cmd = (u32 *) cmdbuf->buf; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 232 | |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 233 | *cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 234 | |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 235 | if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 236 | DRM_ERROR("Not a type 3 packet\n"); |
| 237 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 238 | } |
| 239 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 240 | if (4 * *cmdsz > cmdbuf->bufsz) { |
| 241 | DRM_ERROR("Packet size larger than size of data provided\n"); |
| 242 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 243 | } |
| 244 | |
| 245 | /* Check client state and fix it up if necessary */ |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 246 | if (cmd[0] & 0x8000) { /* MSB of opcode: next DWORD GUI_CNTL */ |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 247 | u32 offset; |
| 248 | |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 249 | if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 250 | | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 251 | offset = cmd[2] << 10; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 252 | if (radeon_check_and_fixup_offset |
| 253 | (dev_priv, filp_priv, &offset)) { |
| 254 | DRM_ERROR("Invalid first packet offset\n"); |
| 255 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 256 | } |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 257 | cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 258 | } |
| 259 | |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 260 | if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) && |
| 261 | (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { |
| 262 | offset = cmd[3] << 10; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 263 | if (radeon_check_and_fixup_offset |
| 264 | (dev_priv, filp_priv, &offset)) { |
| 265 | DRM_ERROR("Invalid second packet offset\n"); |
| 266 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 267 | } |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 268 | cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 269 | } |
| 270 | } |
| 271 | |
| 272 | return 0; |
| 273 | } |
| 274 | |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 275 | /* ================================================================ |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 276 | * CP hardware state programming functions |
| 277 | */ |
| 278 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 279 | static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv, |
| 280 | drm_clip_rect_t * box) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 281 | { |
| 282 | RING_LOCALS; |
| 283 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 284 | DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n", |
| 285 | box->x1, box->y1, box->x2, box->y2); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 286 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 287 | BEGIN_RING(4); |
| 288 | OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); |
| 289 | OUT_RING((box->y1 << 16) | box->x1); |
| 290 | OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); |
| 291 | OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 292 | ADVANCE_RING(); |
| 293 | } |
| 294 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 295 | /* Emit 1.1 state |
| 296 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 297 | static int radeon_emit_state(drm_radeon_private_t * dev_priv, |
| 298 | drm_file_t * filp_priv, |
| 299 | drm_radeon_context_regs_t * ctx, |
| 300 | drm_radeon_texture_regs_t * tex, |
| 301 | unsigned int dirty) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 302 | { |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 303 | RING_LOCALS; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 304 | DRM_DEBUG("dirty=0x%08x\n", dirty); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 305 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 306 | if (dirty & RADEON_UPLOAD_CONTEXT) { |
| 307 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
| 308 | &ctx->rb3d_depthoffset)) { |
| 309 | DRM_ERROR("Invalid depth buffer offset\n"); |
| 310 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 311 | } |
| 312 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 313 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
| 314 | &ctx->rb3d_coloroffset)) { |
| 315 | DRM_ERROR("Invalid depth buffer offset\n"); |
| 316 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 317 | } |
| 318 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 319 | BEGIN_RING(14); |
| 320 | OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); |
| 321 | OUT_RING(ctx->pp_misc); |
| 322 | OUT_RING(ctx->pp_fog_color); |
| 323 | OUT_RING(ctx->re_solid_color); |
| 324 | OUT_RING(ctx->rb3d_blendcntl); |
| 325 | OUT_RING(ctx->rb3d_depthoffset); |
| 326 | OUT_RING(ctx->rb3d_depthpitch); |
| 327 | OUT_RING(ctx->rb3d_zstencilcntl); |
| 328 | OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2)); |
| 329 | OUT_RING(ctx->pp_cntl); |
| 330 | OUT_RING(ctx->rb3d_cntl); |
| 331 | OUT_RING(ctx->rb3d_coloroffset); |
| 332 | OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); |
| 333 | OUT_RING(ctx->rb3d_colorpitch); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 334 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 335 | } |
| 336 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 337 | if (dirty & RADEON_UPLOAD_VERTFMT) { |
| 338 | BEGIN_RING(2); |
| 339 | OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0)); |
| 340 | OUT_RING(ctx->se_coord_fmt); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 341 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 342 | } |
| 343 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 344 | if (dirty & RADEON_UPLOAD_LINE) { |
| 345 | BEGIN_RING(5); |
| 346 | OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1)); |
| 347 | OUT_RING(ctx->re_line_pattern); |
| 348 | OUT_RING(ctx->re_line_state); |
| 349 | OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0)); |
| 350 | OUT_RING(ctx->se_line_width); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 351 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 352 | } |
| 353 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 354 | if (dirty & RADEON_UPLOAD_BUMPMAP) { |
| 355 | BEGIN_RING(5); |
| 356 | OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0)); |
| 357 | OUT_RING(ctx->pp_lum_matrix); |
| 358 | OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1)); |
| 359 | OUT_RING(ctx->pp_rot_matrix_0); |
| 360 | OUT_RING(ctx->pp_rot_matrix_1); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 361 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 362 | } |
| 363 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 364 | if (dirty & RADEON_UPLOAD_MASKS) { |
| 365 | BEGIN_RING(4); |
| 366 | OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2)); |
| 367 | OUT_RING(ctx->rb3d_stencilrefmask); |
| 368 | OUT_RING(ctx->rb3d_ropcntl); |
| 369 | OUT_RING(ctx->rb3d_planemask); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 370 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 371 | } |
| 372 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 373 | if (dirty & RADEON_UPLOAD_VIEWPORT) { |
| 374 | BEGIN_RING(7); |
| 375 | OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5)); |
| 376 | OUT_RING(ctx->se_vport_xscale); |
| 377 | OUT_RING(ctx->se_vport_xoffset); |
| 378 | OUT_RING(ctx->se_vport_yscale); |
| 379 | OUT_RING(ctx->se_vport_yoffset); |
| 380 | OUT_RING(ctx->se_vport_zscale); |
| 381 | OUT_RING(ctx->se_vport_zoffset); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 382 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 383 | } |
| 384 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 385 | if (dirty & RADEON_UPLOAD_SETUP) { |
| 386 | BEGIN_RING(4); |
| 387 | OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0)); |
| 388 | OUT_RING(ctx->se_cntl); |
| 389 | OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0)); |
| 390 | OUT_RING(ctx->se_cntl_status); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 391 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 392 | } |
| 393 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 394 | if (dirty & RADEON_UPLOAD_MISC) { |
| 395 | BEGIN_RING(2); |
| 396 | OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0)); |
| 397 | OUT_RING(ctx->re_misc); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 398 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 399 | } |
| 400 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 401 | if (dirty & RADEON_UPLOAD_TEX0) { |
| 402 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
| 403 | &tex[0].pp_txoffset)) { |
| 404 | DRM_ERROR("Invalid texture offset for unit 0\n"); |
| 405 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 406 | } |
| 407 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 408 | BEGIN_RING(9); |
| 409 | OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5)); |
| 410 | OUT_RING(tex[0].pp_txfilter); |
| 411 | OUT_RING(tex[0].pp_txformat); |
| 412 | OUT_RING(tex[0].pp_txoffset); |
| 413 | OUT_RING(tex[0].pp_txcblend); |
| 414 | OUT_RING(tex[0].pp_txablend); |
| 415 | OUT_RING(tex[0].pp_tfactor); |
| 416 | OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0)); |
| 417 | OUT_RING(tex[0].pp_border_color); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 418 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 419 | } |
| 420 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 421 | if (dirty & RADEON_UPLOAD_TEX1) { |
| 422 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
| 423 | &tex[1].pp_txoffset)) { |
| 424 | DRM_ERROR("Invalid texture offset for unit 1\n"); |
| 425 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 426 | } |
| 427 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 428 | BEGIN_RING(9); |
| 429 | OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5)); |
| 430 | OUT_RING(tex[1].pp_txfilter); |
| 431 | OUT_RING(tex[1].pp_txformat); |
| 432 | OUT_RING(tex[1].pp_txoffset); |
| 433 | OUT_RING(tex[1].pp_txcblend); |
| 434 | OUT_RING(tex[1].pp_txablend); |
| 435 | OUT_RING(tex[1].pp_tfactor); |
| 436 | OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0)); |
| 437 | OUT_RING(tex[1].pp_border_color); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 438 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 439 | } |
| 440 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 441 | if (dirty & RADEON_UPLOAD_TEX2) { |
| 442 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, |
| 443 | &tex[2].pp_txoffset)) { |
| 444 | DRM_ERROR("Invalid texture offset for unit 2\n"); |
| 445 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 446 | } |
| 447 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 448 | BEGIN_RING(9); |
| 449 | OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5)); |
| 450 | OUT_RING(tex[2].pp_txfilter); |
| 451 | OUT_RING(tex[2].pp_txformat); |
| 452 | OUT_RING(tex[2].pp_txoffset); |
| 453 | OUT_RING(tex[2].pp_txcblend); |
| 454 | OUT_RING(tex[2].pp_txablend); |
| 455 | OUT_RING(tex[2].pp_tfactor); |
| 456 | OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0)); |
| 457 | OUT_RING(tex[2].pp_border_color); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 458 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 459 | } |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 460 | |
| 461 | return 0; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 462 | } |
| 463 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 464 | /* Emit 1.2 state |
| 465 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 466 | static int radeon_emit_state2(drm_radeon_private_t * dev_priv, |
| 467 | drm_file_t * filp_priv, |
| 468 | drm_radeon_state_t * state) |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 469 | { |
| 470 | RING_LOCALS; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 471 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 472 | if (state->dirty & RADEON_UPLOAD_ZBIAS) { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 473 | BEGIN_RING(3); |
| 474 | OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1)); |
| 475 | OUT_RING(state->context2.se_zbias_factor); |
| 476 | OUT_RING(state->context2.se_zbias_constant); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 477 | ADVANCE_RING(); |
| 478 | } |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 479 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 480 | return radeon_emit_state(dev_priv, filp_priv, &state->context, |
| 481 | state->tex, state->dirty); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 482 | } |
| 483 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 484 | /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in |
| 485 | * 1.3 cmdbuffers allow all previous state to be updated as well as |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 486 | * the tcl scalar and vector areas. |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 487 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 488 | static struct { |
| 489 | int start; |
| 490 | int len; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 491 | const char *name; |
| 492 | } packet[RADEON_MAX_STATE_PACKETS] = { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 493 | { |
| 494 | RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, { |
| 495 | RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, { |
| 496 | RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, { |
| 497 | RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, { |
| 498 | RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, { |
| 499 | RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, { |
| 500 | RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, { |
| 501 | RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, { |
| 502 | RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, { |
| 503 | RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, { |
| 504 | RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, { |
| 505 | RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, { |
| 506 | RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, { |
| 507 | RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, { |
| 508 | RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, { |
| 509 | RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, { |
| 510 | RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, { |
| 511 | RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, { |
| 512 | RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, { |
| 513 | RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, { |
| 514 | RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, |
| 515 | "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, { |
| 516 | R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, { |
| 517 | R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, { |
| 518 | R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, { |
| 519 | R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, { |
| 520 | R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, { |
| 521 | R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, { |
| 522 | R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, { |
| 523 | R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, { |
| 524 | R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, |
| 525 | { |
| 526 | R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, { |
| 527 | R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, { |
| 528 | R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, { |
| 529 | R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, { |
| 530 | R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, { |
| 531 | R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, |
| 532 | { |
| 533 | R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, { |
| 534 | R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, { |
| 535 | R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, { |
| 536 | R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, { |
| 537 | R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, { |
| 538 | R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, { |
| 539 | R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, { |
| 540 | R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, { |
| 541 | R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, { |
| 542 | R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, { |
| 543 | R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, { |
| 544 | R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, { |
| 545 | R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, { |
| 546 | R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, |
| 547 | { |
| 548 | R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, { |
| 549 | R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, { |
| 550 | R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, { |
| 551 | R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, { |
| 552 | R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, { |
| 553 | R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, { |
| 554 | R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, { |
| 555 | R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, { |
| 556 | R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, { |
| 557 | R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, { |
| 558 | R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, |
| 559 | "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, { |
| 560 | R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ |
| 561 | { |
| 562 | R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ |
| 563 | { |
| 564 | R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, { |
| 565 | R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, { |
| 566 | R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, { |
| 567 | R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, { |
| 568 | R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, { |
| 569 | R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, { |
| 570 | R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, { |
| 571 | R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, { |
| 572 | R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, { |
| 573 | R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, { |
| 574 | RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, { |
| 575 | RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, { |
| 576 | RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, { |
Roland Scheidegger | c4a87c6 | 2004-12-08 16:43:00 +0000 | [diff] [blame] | 577 | R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, { |
| 578 | R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, |
Roland Scheidegger | 732cdc5 | 2005-02-10 19:22:43 +0000 | [diff] [blame] | 579 | { |
| 580 | RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, { |
| 581 | RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, { |
| 582 | RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, { |
| 583 | RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, { |
| 584 | RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, { |
Roland Scheidegger | 3456392 | 2005-03-15 22:12:30 +0000 | [diff] [blame] | 585 | RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, { |
| 586 | R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, |
Roland Scheidegger | c4a87c6 | 2004-12-08 16:43:00 +0000 | [diff] [blame] | 587 | }; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 588 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 589 | /* ================================================================ |
| 590 | * Performance monitoring functions |
| 591 | */ |
| 592 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 593 | static void radeon_clear_box(drm_radeon_private_t * dev_priv, |
| 594 | int x, int y, int w, int h, int r, int g, int b) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 595 | { |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 596 | u32 color; |
| 597 | RING_LOCALS; |
| 598 | |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 599 | x += dev_priv->sarea_priv->boxes[0].x1; |
| 600 | y += dev_priv->sarea_priv->boxes[0].y1; |
| 601 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 602 | switch (dev_priv->color_fmt) { |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 603 | case RADEON_COLOR_FORMAT_RGB565: |
| 604 | color = (((r & 0xf8) << 8) | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 605 | ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 606 | break; |
| 607 | case RADEON_COLOR_FORMAT_ARGB8888: |
| 608 | default: |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 609 | color = (((0xff) << 24) | (r << 16) | (g << 8) | b); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 610 | break; |
| 611 | } |
| 612 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 613 | BEGIN_RING(4); |
| 614 | RADEON_WAIT_UNTIL_3D_IDLE(); |
| 615 | OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); |
| 616 | OUT_RING(0xffffffff); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 617 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 618 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 619 | BEGIN_RING(6); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 620 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 621 | OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); |
| 622 | OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| 623 | RADEON_GMC_BRUSH_SOLID_COLOR | |
| 624 | (dev_priv->color_fmt << 8) | |
| 625 | RADEON_GMC_SRC_DATATYPE_COLOR | |
| 626 | RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 627 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 628 | if (dev_priv->page_flipping && dev_priv->current_page == 1) { |
| 629 | OUT_RING(dev_priv->front_pitch_offset); |
| 630 | } else { |
| 631 | OUT_RING(dev_priv->back_pitch_offset); |
| 632 | } |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 633 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 634 | OUT_RING(color); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 635 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 636 | OUT_RING((x << 16) | y); |
| 637 | OUT_RING((w << 16) | h); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 638 | |
| 639 | ADVANCE_RING(); |
| 640 | } |
| 641 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 642 | static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 643 | { |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 644 | /* Collapse various things into a wait flag -- trying to |
| 645 | * guess if userspase slept -- better just to have them tell us. |
| 646 | */ |
| 647 | if (dev_priv->stats.last_frame_reads > 1 || |
| 648 | dev_priv->stats.last_clear_reads > dev_priv->stats.clears) { |
| 649 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 650 | } |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 651 | |
| 652 | if (dev_priv->stats.freelist_loops) { |
| 653 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; |
| 654 | } |
| 655 | |
| 656 | /* Purple box for page flipping |
| 657 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 658 | if (dev_priv->stats.boxes & RADEON_BOX_FLIP) |
| 659 | radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 660 | |
| 661 | /* Red box if we have to wait for idle at any point |
| 662 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 663 | if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE) |
| 664 | radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 665 | |
| 666 | /* Blue box: lost context? |
| 667 | */ |
| 668 | |
| 669 | /* Yellow box for texture swaps |
| 670 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 671 | if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD) |
| 672 | radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 673 | |
| 674 | /* Green box if hardware never idles (as far as we can tell) |
| 675 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 676 | if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) |
| 677 | radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 678 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 679 | /* Draw bars indicating number of buffers allocated |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 680 | * (not a great measure, easily confused) |
| 681 | */ |
| 682 | if (dev_priv->stats.requested_bufs) { |
| 683 | if (dev_priv->stats.requested_bufs > 100) |
| 684 | dev_priv->stats.requested_bufs = 100; |
| 685 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 686 | radeon_clear_box(dev_priv, 4, 16, |
| 687 | dev_priv->stats.requested_bufs, 4, |
| 688 | 196, 128, 128); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 689 | } |
| 690 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 691 | memset(&dev_priv->stats, 0, sizeof(dev_priv->stats)); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 692 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 693 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 694 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 695 | /* ================================================================ |
| 696 | * CP command dispatch functions |
| 697 | */ |
| 698 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 699 | static void radeon_cp_dispatch_clear(drm_device_t * dev, |
| 700 | drm_radeon_clear_t * clear, |
| 701 | drm_radeon_clear_rect_t * depth_boxes) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 702 | { |
| 703 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 704 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 705 | drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 706 | int nbox = sarea_priv->nbox; |
| 707 | drm_clip_rect_t *pbox = sarea_priv->boxes; |
| 708 | unsigned int flags = clear->flags; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 709 | u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 710 | int i; |
| 711 | RING_LOCALS; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 712 | DRM_DEBUG("flags = 0x%x\n", flags); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 713 | |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 714 | dev_priv->stats.clears++; |
| 715 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 716 | if (dev_priv->page_flipping && dev_priv->current_page == 1) { |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 717 | unsigned int tmp = flags; |
| 718 | |
| 719 | flags &= ~(RADEON_FRONT | RADEON_BACK); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 720 | if (tmp & RADEON_FRONT) |
| 721 | flags |= RADEON_BACK; |
| 722 | if (tmp & RADEON_BACK) |
| 723 | flags |= RADEON_FRONT; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 724 | } |
| 725 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 726 | if (flags & (RADEON_FRONT | RADEON_BACK)) { |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 727 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 728 | BEGIN_RING(4); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 729 | |
| 730 | /* Ensure the 3D stream is idle before doing a |
| 731 | * 2D fill to clear the front or back buffer. |
| 732 | */ |
| 733 | RADEON_WAIT_UNTIL_3D_IDLE(); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 734 | |
| 735 | OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); |
| 736 | OUT_RING(clear->color_mask); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 737 | |
| 738 | ADVANCE_RING(); |
| 739 | |
| 740 | /* Make sure we restore the 3D state next time. |
| 741 | */ |
| 742 | dev_priv->sarea_priv->ctx_owner = 0; |
| 743 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 744 | for (i = 0; i < nbox; i++) { |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 745 | int x = pbox[i].x1; |
| 746 | int y = pbox[i].y1; |
| 747 | int w = pbox[i].x2 - x; |
| 748 | int h = pbox[i].y2 - y; |
| 749 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 750 | DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n", |
| 751 | x, y, w, h, flags); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 752 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 753 | if (flags & RADEON_FRONT) { |
| 754 | BEGIN_RING(6); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 755 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 756 | OUT_RING(CP_PACKET3 |
| 757 | (RADEON_CNTL_PAINT_MULTI, 4)); |
| 758 | OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| 759 | RADEON_GMC_BRUSH_SOLID_COLOR | |
| 760 | (dev_priv-> |
| 761 | color_fmt << 8) | |
| 762 | RADEON_GMC_SRC_DATATYPE_COLOR | |
| 763 | RADEON_ROP3_P | |
| 764 | RADEON_GMC_CLR_CMP_CNTL_DIS); |
| 765 | |
| 766 | OUT_RING(dev_priv->front_pitch_offset); |
| 767 | OUT_RING(clear->clear_color); |
| 768 | |
| 769 | OUT_RING((x << 16) | y); |
| 770 | OUT_RING((w << 16) | h); |
| 771 | |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 772 | ADVANCE_RING(); |
| 773 | } |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 774 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 775 | if (flags & RADEON_BACK) { |
| 776 | BEGIN_RING(6); |
| 777 | |
| 778 | OUT_RING(CP_PACKET3 |
| 779 | (RADEON_CNTL_PAINT_MULTI, 4)); |
| 780 | OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| 781 | RADEON_GMC_BRUSH_SOLID_COLOR | |
| 782 | (dev_priv-> |
| 783 | color_fmt << 8) | |
| 784 | RADEON_GMC_SRC_DATATYPE_COLOR | |
| 785 | RADEON_ROP3_P | |
| 786 | RADEON_GMC_CLR_CMP_CNTL_DIS); |
| 787 | |
| 788 | OUT_RING(dev_priv->back_pitch_offset); |
| 789 | OUT_RING(clear->clear_color); |
| 790 | |
| 791 | OUT_RING((x << 16) | y); |
| 792 | OUT_RING((w << 16) | h); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 793 | |
| 794 | ADVANCE_RING(); |
| 795 | } |
| 796 | } |
| 797 | } |
| 798 | |
Roland Scheidegger | c4a87c6 | 2004-12-08 16:43:00 +0000 | [diff] [blame] | 799 | /* hyper z clear */ |
| 800 | /* no docs available, based on reverse engeneering by Stephane Marchesin */ |
| 801 | if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) && (flags & RADEON_CLEAR_FASTZ)) { |
| 802 | |
| 803 | int i; |
| 804 | int depthpixperline = dev_priv->depth_fmt==RADEON_DEPTH_FORMAT_16BIT_INT_Z? |
| 805 | (dev_priv->depth_pitch / 2): (dev_priv->depth_pitch / 4); |
| 806 | |
| 807 | u32 clearmask; |
| 808 | |
| 809 | u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth | |
| 810 | ((clear->depth_mask & 0xff) << 24); |
| 811 | |
| 812 | |
| 813 | /* Make sure we restore the 3D state next time. |
| 814 | * we haven't touched any "normal" state - still need this? |
| 815 | */ |
| 816 | dev_priv->sarea_priv->ctx_owner = 0; |
| 817 | |
| 818 | if ((dev_priv->flags & CHIP_HAS_HIERZ) && (flags & RADEON_USE_HIERZ)) { |
| 819 | /* FIXME : reverse engineer that for Rx00 cards */ |
| 820 | /* FIXME : the mask supposedly contains low-res z values. So can't set |
| 821 | just to the max (0xff? or actually 0x3fff?), need to take z clear |
| 822 | value into account? */ |
| 823 | /* pattern seems to work for r100, though get slight |
| 824 | rendering errors with glxgears. If hierz is not enabled for r100, |
| 825 | only 4 bits which indicate clear (15,16,31,32, all zero) matter, the |
| 826 | other ones are ignored, and the same clear mask can be used. That's |
| 827 | very different behaviour than R200 which needs different clear mask |
| 828 | and different number of tiles to clear if hierz is enabled or not !?! |
| 829 | */ |
| 830 | clearmask = (0xff<<22)|(0xff<<6)| 0x003f003f; |
| 831 | } |
| 832 | else { |
| 833 | /* clear mask : chooses the clearing pattern. |
| 834 | rv250: could be used to clear only parts of macrotiles |
| 835 | (but that would get really complicated...)? |
| 836 | bit 0 and 1 (either or both of them ?!?!) are used to |
| 837 | not clear tile (or maybe one of the bits indicates if the tile is |
| 838 | compressed or not), bit 2 and 3 to not clear tile 1,...,. |
| 839 | Pattern is as follows: |
| 840 | | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29| |
| 841 | bits ------------------------------------------------- |
| 842 | | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31| |
| 843 | rv100: clearmask covers 2x8 4x1 tiles, but one clear still |
| 844 | covers 256 pixels ?!? |
| 845 | */ |
| 846 | clearmask = 0x0; |
| 847 | } |
| 848 | |
| 849 | BEGIN_RING( 8 ); |
| 850 | RADEON_WAIT_UNTIL_2D_IDLE(); |
| 851 | OUT_RING_REG( RADEON_RB3D_DEPTHCLEARVALUE, |
| 852 | tempRB3D_DEPTHCLEARVALUE); |
| 853 | /* what offset is this exactly ? */ |
| 854 | OUT_RING_REG( RADEON_RB3D_ZMASKOFFSET, 0 ); |
| 855 | /* need ctlstat, otherwise get some strange black flickering */ |
| 856 | OUT_RING_REG( RADEON_RB3D_ZCACHE_CTLSTAT, RADEON_RB3D_ZC_FLUSH_ALL ); |
| 857 | ADVANCE_RING(); |
| 858 | |
| 859 | for (i = 0; i < nbox; i++) { |
| 860 | int tileoffset, nrtilesx, nrtilesy, j; |
| 861 | /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */ |
| 862 | if ((dev_priv->flags&CHIP_HAS_HIERZ) && !(dev_priv->microcode_version==UCODE_R200)) { |
| 863 | /* FIXME : figure this out for r200 (when hierz is enabled). Or |
| 864 | maybe r200 actually doesn't need to put the low-res z value into |
| 865 | the tile cache like r100, but just needs to clear the hi-level z-buffer? |
| 866 | Works for R100, both with hierz and without. |
| 867 | R100 seems to operate on 2x1 8x8 tiles, but... |
| 868 | odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially |
| 869 | problematic with resolutions which are not 64 pix aligned? */ |
| 870 | tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 6; |
| 871 | nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4; |
| 872 | nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); |
| 873 | for (j = 0; j <= nrtilesy; j++) { |
| 874 | BEGIN_RING( 4 ); |
| 875 | OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); |
| 876 | /* first tile */ |
| 877 | OUT_RING( tileoffset * 8 ); |
| 878 | /* the number of tiles to clear */ |
| 879 | OUT_RING( nrtilesx + 4 ); |
| 880 | /* clear mask : chooses the clearing pattern. */ |
| 881 | OUT_RING( clearmask ); |
| 882 | ADVANCE_RING(); |
| 883 | tileoffset += depthpixperline >> 6; |
| 884 | } |
| 885 | } |
| 886 | else if (dev_priv->microcode_version==UCODE_R200) { |
| 887 | /* works for rv250. */ |
| 888 | /* find first macro tile (8x2 4x4 z-pixels on rv250) */ |
| 889 | tileoffset = ((pbox[i].y1 >> 3) * depthpixperline + pbox[i].x1) >> 5; |
| 890 | nrtilesx = (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5); |
| 891 | nrtilesy = (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); |
| 892 | for (j = 0; j <= nrtilesy; j++) { |
| 893 | BEGIN_RING( 4 ); |
| 894 | OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); |
| 895 | /* first tile */ |
| 896 | /* judging by the first tile offset needed, could possibly |
| 897 | directly address/clear 4x4 tiles instead of 8x2 * 4x4 |
| 898 | macro tiles, though would still need clear mask for |
| 899 | right/bottom if truely 4x4 granularity is desired ? */ |
| 900 | OUT_RING( tileoffset * 16 ); |
| 901 | /* the number of tiles to clear */ |
| 902 | OUT_RING( nrtilesx + 1 ); |
| 903 | /* clear mask : chooses the clearing pattern. */ |
| 904 | OUT_RING( clearmask ); |
| 905 | ADVANCE_RING(); |
| 906 | tileoffset += depthpixperline >> 5; |
| 907 | } |
| 908 | } |
| 909 | else { /* rv 100 */ |
| 910 | /* rv100 might not need 64 pix alignment, who knows */ |
| 911 | /* offsets are, hmm, weird */ |
| 912 | tileoffset = ((pbox[i].y1 >> 4) * depthpixperline + pbox[i].x1) >> 6; |
| 913 | nrtilesx = ((pbox[i].x2 & ~63) - (pbox[i].x1 & ~63)) >> 4; |
| 914 | nrtilesy = (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4); |
| 915 | for (j = 0; j <= nrtilesy; j++) { |
| 916 | BEGIN_RING( 4 ); |
| 917 | OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_ZMASK, 2 ) ); |
| 918 | OUT_RING( tileoffset * 128 ); |
| 919 | /* the number of tiles to clear */ |
| 920 | OUT_RING( nrtilesx + 4 ); |
| 921 | /* clear mask : chooses the clearing pattern. */ |
| 922 | OUT_RING( clearmask ); |
| 923 | ADVANCE_RING(); |
| 924 | tileoffset += depthpixperline >> 6; |
| 925 | } |
| 926 | } |
| 927 | } |
| 928 | |
| 929 | /* TODO don't always clear all hi-level z tiles */ |
| 930 | if ((dev_priv->flags & CHIP_HAS_HIERZ) && (dev_priv->microcode_version==UCODE_R200) |
| 931 | && (flags & RADEON_USE_HIERZ)) |
| 932 | /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */ |
| 933 | /* FIXME : the mask supposedly contains low-res z values. So can't set |
| 934 | just to the max (0xff? or actually 0x3fff?), need to take z clear |
| 935 | value into account? */ |
| 936 | { |
| 937 | BEGIN_RING( 4 ); |
| 938 | OUT_RING( CP_PACKET3( RADEON_3D_CLEAR_HIZ, 2 ) ); |
| 939 | OUT_RING( 0x0 ); /* First tile */ |
| 940 | OUT_RING( 0x3cc0 ); |
| 941 | OUT_RING( (0xff<<22)|(0xff<<6)| 0x003f003f); |
| 942 | ADVANCE_RING(); |
| 943 | } |
| 944 | } |
| 945 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 946 | /* We have to clear the depth and/or stencil buffers by |
| 947 | * rendering a quad into just those buffers. Thus, we have to |
| 948 | * make sure the 3D engine is configured correctly. |
| 949 | */ |
Roland Scheidegger | c4a87c6 | 2004-12-08 16:43:00 +0000 | [diff] [blame] | 950 | else if ((dev_priv->microcode_version == UCODE_R200) && |
| 951 | (flags & (RADEON_DEPTH | RADEON_STENCIL))) { |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 952 | |
| 953 | int tempPP_CNTL; |
| 954 | int tempRE_CNTL; |
| 955 | int tempRB3D_CNTL; |
| 956 | int tempRB3D_ZSTENCILCNTL; |
| 957 | int tempRB3D_STENCILREFMASK; |
| 958 | int tempRB3D_PLANEMASK; |
| 959 | int tempSE_CNTL; |
| 960 | int tempSE_VTE_CNTL; |
| 961 | int tempSE_VTX_FMT_0; |
| 962 | int tempSE_VTX_FMT_1; |
| 963 | int tempSE_VAP_CNTL; |
| 964 | int tempRE_AUX_SCISSOR_CNTL; |
| 965 | |
| 966 | tempPP_CNTL = 0; |
| 967 | tempRE_CNTL = 0; |
| 968 | |
| 969 | tempRB3D_CNTL = depth_clear->rb3d_cntl; |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 970 | |
| 971 | tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; |
| 972 | tempRB3D_STENCILREFMASK = 0x0; |
| 973 | |
| 974 | tempSE_CNTL = depth_clear->se_cntl; |
| 975 | |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 976 | /* Disable TCL */ |
| 977 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 978 | tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */ |
| 979 | (0x9 << |
| 980 | SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT)); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 981 | |
| 982 | tempRB3D_PLANEMASK = 0x0; |
| 983 | |
| 984 | tempRE_AUX_SCISSOR_CNTL = 0x0; |
| 985 | |
| 986 | tempSE_VTE_CNTL = |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 987 | SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK; |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 988 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 989 | /* Vertex format (X, Y, Z, W) */ |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 990 | tempSE_VTX_FMT_0 = |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 991 | SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK | |
| 992 | SE_VTX_FMT_0__VTX_W0_PRESENT_MASK; |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 993 | tempSE_VTX_FMT_1 = 0x0; |
| 994 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 995 | /* |
| 996 | * Depth buffer specific enables |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 997 | */ |
| 998 | if (flags & RADEON_DEPTH) { |
| 999 | /* Enable depth buffer */ |
| 1000 | tempRB3D_CNTL |= RADEON_Z_ENABLE; |
| 1001 | } else { |
| 1002 | /* Disable depth buffer */ |
| 1003 | tempRB3D_CNTL &= ~RADEON_Z_ENABLE; |
| 1004 | } |
| 1005 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1006 | /* |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1007 | * Stencil buffer specific enables |
| 1008 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1009 | if (flags & RADEON_STENCIL) { |
| 1010 | tempRB3D_CNTL |= RADEON_STENCIL_ENABLE; |
| 1011 | tempRB3D_STENCILREFMASK = clear->depth_mask; |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1012 | } else { |
| 1013 | tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE; |
| 1014 | tempRB3D_STENCILREFMASK = 0x00000000; |
| 1015 | } |
| 1016 | |
Roland Scheidegger | c4a87c6 | 2004-12-08 16:43:00 +0000 | [diff] [blame] | 1017 | if (flags & RADEON_USE_COMP_ZBUF) { |
| 1018 | tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | |
| 1019 | RADEON_Z_DECOMPRESSION_ENABLE; |
| 1020 | } |
| 1021 | if (flags & RADEON_USE_HIERZ) { |
| 1022 | tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; |
| 1023 | } |
| 1024 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1025 | BEGIN_RING(26); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1026 | RADEON_WAIT_UNTIL_2D_IDLE(); |
| 1027 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1028 | OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL); |
| 1029 | OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL); |
| 1030 | OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL); |
| 1031 | OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL); |
| 1032 | OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, |
| 1033 | tempRB3D_STENCILREFMASK); |
| 1034 | OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK); |
| 1035 | OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL); |
| 1036 | OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL); |
| 1037 | OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0); |
| 1038 | OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1); |
| 1039 | OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL); |
| 1040 | OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1041 | ADVANCE_RING(); |
| 1042 | |
| 1043 | /* Make sure we restore the 3D state next time. |
| 1044 | */ |
| 1045 | dev_priv->sarea_priv->ctx_owner = 0; |
| 1046 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1047 | for (i = 0; i < nbox; i++) { |
| 1048 | |
| 1049 | /* Funny that this should be required -- |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1050 | * sets top-left? |
| 1051 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1052 | radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1053 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1054 | BEGIN_RING(14); |
| 1055 | OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12)); |
| 1056 | OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | |
| 1057 | RADEON_PRIM_WALK_RING | |
| 1058 | (3 << RADEON_NUM_VERTICES_SHIFT))); |
| 1059 | OUT_RING(depth_boxes[i].ui[CLEAR_X1]); |
| 1060 | OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); |
| 1061 | OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); |
| 1062 | OUT_RING(0x3f800000); |
| 1063 | OUT_RING(depth_boxes[i].ui[CLEAR_X1]); |
| 1064 | OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); |
| 1065 | OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); |
| 1066 | OUT_RING(0x3f800000); |
| 1067 | OUT_RING(depth_boxes[i].ui[CLEAR_X2]); |
| 1068 | OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); |
| 1069 | OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); |
| 1070 | OUT_RING(0x3f800000); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1071 | ADVANCE_RING(); |
| 1072 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1073 | } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) { |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1074 | |
Roland Scheidegger | c4a87c6 | 2004-12-08 16:43:00 +0000 | [diff] [blame] | 1075 | int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; |
| 1076 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1077 | rb3d_cntl = depth_clear->rb3d_cntl; |
| 1078 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1079 | if (flags & RADEON_DEPTH) { |
| 1080 | rb3d_cntl |= RADEON_Z_ENABLE; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1081 | } else { |
| 1082 | rb3d_cntl &= ~RADEON_Z_ENABLE; |
| 1083 | } |
| 1084 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1085 | if (flags & RADEON_STENCIL) { |
| 1086 | rb3d_cntl |= RADEON_STENCIL_ENABLE; |
| 1087 | rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */ |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1088 | } else { |
| 1089 | rb3d_cntl &= ~RADEON_STENCIL_ENABLE; |
| 1090 | rb3d_stencilrefmask = 0x00000000; |
| 1091 | } |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1092 | |
Roland Scheidegger | c4a87c6 | 2004-12-08 16:43:00 +0000 | [diff] [blame] | 1093 | if (flags & RADEON_USE_COMP_ZBUF) { |
| 1094 | tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | |
| 1095 | RADEON_Z_DECOMPRESSION_ENABLE; |
| 1096 | } |
| 1097 | if (flags & RADEON_USE_HIERZ) { |
| 1098 | tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; |
| 1099 | } |
| 1100 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1101 | BEGIN_RING(13); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1102 | RADEON_WAIT_UNTIL_2D_IDLE(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1103 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1104 | OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1)); |
| 1105 | OUT_RING(0x00000000); |
| 1106 | OUT_RING(rb3d_cntl); |
| 1107 | |
Roland Scheidegger | c4a87c6 | 2004-12-08 16:43:00 +0000 | [diff] [blame] | 1108 | OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1109 | OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask); |
| 1110 | OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000); |
| 1111 | OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1112 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1113 | |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1114 | /* Make sure we restore the 3D state next time. |
| 1115 | */ |
| 1116 | dev_priv->sarea_priv->ctx_owner = 0; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1117 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1118 | for (i = 0; i < nbox; i++) { |
| 1119 | |
| 1120 | /* Funny that this should be required -- |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1121 | * sets top-left? |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1122 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1123 | radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1124 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1125 | BEGIN_RING(15); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1126 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1127 | OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13)); |
| 1128 | OUT_RING(RADEON_VTX_Z_PRESENT | |
| 1129 | RADEON_VTX_PKCOLOR_PRESENT); |
| 1130 | OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | |
| 1131 | RADEON_PRIM_WALK_RING | |
| 1132 | RADEON_MAOS_ENABLE | |
| 1133 | RADEON_VTX_FMT_RADEON_MODE | |
| 1134 | (3 << RADEON_NUM_VERTICES_SHIFT))); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1135 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1136 | OUT_RING(depth_boxes[i].ui[CLEAR_X1]); |
| 1137 | OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); |
| 1138 | OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); |
| 1139 | OUT_RING(0x0); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1140 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1141 | OUT_RING(depth_boxes[i].ui[CLEAR_X1]); |
| 1142 | OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); |
| 1143 | OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); |
| 1144 | OUT_RING(0x0); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1145 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1146 | OUT_RING(depth_boxes[i].ui[CLEAR_X2]); |
| 1147 | OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); |
| 1148 | OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); |
| 1149 | OUT_RING(0x0); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1150 | |
| 1151 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1152 | } |
| 1153 | } |
| 1154 | |
| 1155 | /* Increment the clear counter. The client-side 3D driver must |
| 1156 | * wait on this value before performing the clear ioctl. We |
| 1157 | * need this because the card's so damned fast... |
| 1158 | */ |
| 1159 | dev_priv->sarea_priv->last_clear++; |
| 1160 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1161 | BEGIN_RING(4); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1162 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1163 | RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1164 | RADEON_WAIT_UNTIL_IDLE(); |
| 1165 | |
| 1166 | ADVANCE_RING(); |
| 1167 | } |
| 1168 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1169 | static void radeon_cp_dispatch_swap(drm_device_t * dev) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1170 | { |
| 1171 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1172 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
| 1173 | int nbox = sarea_priv->nbox; |
| 1174 | drm_clip_rect_t *pbox = sarea_priv->boxes; |
| 1175 | int i; |
| 1176 | RING_LOCALS; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1177 | DRM_DEBUG("\n"); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1178 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1179 | /* Do some trivial performance monitoring... |
| 1180 | */ |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1181 | if (dev_priv->do_boxes) |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1182 | radeon_cp_performance_boxes(dev_priv); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1183 | |
| 1184 | /* Wait for the 3D stream to idle before dispatching the bitblt. |
| 1185 | * This will prevent data corruption between the two streams. |
| 1186 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1187 | BEGIN_RING(2); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1188 | |
| 1189 | RADEON_WAIT_UNTIL_3D_IDLE(); |
| 1190 | |
| 1191 | ADVANCE_RING(); |
| 1192 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1193 | for (i = 0; i < nbox; i++) { |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1194 | int x = pbox[i].x1; |
| 1195 | int y = pbox[i].y1; |
| 1196 | int w = pbox[i].x2 - x; |
| 1197 | int h = pbox[i].y2 - y; |
| 1198 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1199 | DRM_DEBUG("dispatch swap %d,%d-%d,%d\n", x, y, w, h); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1200 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1201 | BEGIN_RING(7); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1202 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1203 | OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5)); |
| 1204 | OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
| 1205 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| 1206 | RADEON_GMC_BRUSH_NONE | |
| 1207 | (dev_priv->color_fmt << 8) | |
| 1208 | RADEON_GMC_SRC_DATATYPE_COLOR | |
| 1209 | RADEON_ROP3_S | |
| 1210 | RADEON_DP_SRC_SOURCE_MEMORY | |
| 1211 | RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); |
| 1212 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1213 | /* Make this work even if front & back are flipped: |
| 1214 | */ |
| 1215 | if (dev_priv->current_page == 0) { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1216 | OUT_RING(dev_priv->back_pitch_offset); |
| 1217 | OUT_RING(dev_priv->front_pitch_offset); |
| 1218 | } else { |
| 1219 | OUT_RING(dev_priv->front_pitch_offset); |
| 1220 | OUT_RING(dev_priv->back_pitch_offset); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1221 | } |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1222 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1223 | OUT_RING((x << 16) | y); |
| 1224 | OUT_RING((x << 16) | y); |
| 1225 | OUT_RING((w << 16) | h); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1226 | |
| 1227 | ADVANCE_RING(); |
| 1228 | } |
| 1229 | |
| 1230 | /* Increment the frame counter. The client-side 3D driver must |
| 1231 | * throttle the framerate by waiting for this value before |
| 1232 | * performing the swapbuffer ioctl. |
| 1233 | */ |
| 1234 | dev_priv->sarea_priv->last_frame++; |
| 1235 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1236 | BEGIN_RING(4); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1237 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1238 | RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1239 | RADEON_WAIT_UNTIL_2D_IDLE(); |
| 1240 | |
| 1241 | ADVANCE_RING(); |
| 1242 | } |
| 1243 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1244 | static void radeon_cp_dispatch_flip(drm_device_t * dev) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1245 | { |
| 1246 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1247 | drm_sarea_t *sarea = (drm_sarea_t *) dev_priv->sarea->handle; |
Michel Daenzer | 5e1b8ed | 2002-10-29 13:49:26 +0000 | [diff] [blame] | 1248 | int offset = (dev_priv->current_page == 1) |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1249 | ? dev_priv->front_offset : dev_priv->back_offset; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1250 | RING_LOCALS; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1251 | DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", |
| 1252 | __FUNCTION__, |
| 1253 | dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1254 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1255 | /* Do some trivial performance monitoring... |
| 1256 | */ |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1257 | if (dev_priv->do_boxes) { |
| 1258 | dev_priv->stats.boxes |= RADEON_BOX_FLIP; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1259 | radeon_cp_performance_boxes(dev_priv); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1260 | } |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1261 | |
Michel Daenzer | 5e1b8ed | 2002-10-29 13:49:26 +0000 | [diff] [blame] | 1262 | /* Update the frame offsets for both CRTCs |
| 1263 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1264 | BEGIN_RING(6); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1265 | |
| 1266 | RADEON_WAIT_UNTIL_3D_IDLE(); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1267 | OUT_RING_REG(RADEON_CRTC_OFFSET, |
| 1268 | ((sarea->frame.y * dev_priv->front_pitch + |
| 1269 | sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7) |
| 1270 | + offset); |
| 1271 | OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base |
| 1272 | + offset); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1273 | |
| 1274 | ADVANCE_RING(); |
| 1275 | |
| 1276 | /* Increment the frame counter. The client-side 3D driver must |
| 1277 | * throttle the framerate by waiting for this value before |
| 1278 | * performing the swapbuffer ioctl. |
| 1279 | */ |
| 1280 | dev_priv->sarea_priv->last_frame++; |
Michel Daenzer | 5e1b8ed | 2002-10-29 13:49:26 +0000 | [diff] [blame] | 1281 | dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1282 | 1 - dev_priv->current_page; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1283 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1284 | BEGIN_RING(2); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1285 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1286 | RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1287 | |
| 1288 | ADVANCE_RING(); |
| 1289 | } |
| 1290 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1291 | static int bad_prim_vertex_nr(int primitive, int nr) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1292 | { |
| 1293 | switch (primitive & RADEON_PRIM_TYPE_MASK) { |
| 1294 | case RADEON_PRIM_TYPE_NONE: |
| 1295 | case RADEON_PRIM_TYPE_POINT: |
| 1296 | return nr < 1; |
| 1297 | case RADEON_PRIM_TYPE_LINE: |
| 1298 | return (nr & 1) || nr == 0; |
| 1299 | case RADEON_PRIM_TYPE_LINE_STRIP: |
| 1300 | return nr < 2; |
| 1301 | case RADEON_PRIM_TYPE_TRI_LIST: |
| 1302 | case RADEON_PRIM_TYPE_3VRT_POINT_LIST: |
| 1303 | case RADEON_PRIM_TYPE_3VRT_LINE_LIST: |
| 1304 | case RADEON_PRIM_TYPE_RECT_LIST: |
| 1305 | return nr % 3 || nr == 0; |
| 1306 | case RADEON_PRIM_TYPE_TRI_FAN: |
| 1307 | case RADEON_PRIM_TYPE_TRI_STRIP: |
| 1308 | return nr < 3; |
| 1309 | default: |
| 1310 | return 1; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1311 | } |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1312 | } |
| 1313 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1314 | typedef struct { |
| 1315 | unsigned int start; |
| 1316 | unsigned int finish; |
| 1317 | unsigned int prim; |
| 1318 | unsigned int numverts; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1319 | unsigned int offset; |
| 1320 | unsigned int vc_format; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1321 | } drm_radeon_tcl_prim_t; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1322 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1323 | static void radeon_cp_dispatch_vertex(drm_device_t * dev, |
| 1324 | drm_buf_t * buf, |
| 1325 | drm_radeon_tcl_prim_t * prim) |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1326 | { |
| 1327 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Keith Whitwell | 9e7d617 | 2003-06-16 10:40:52 +0000 | [diff] [blame] | 1328 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
Michel Daenzer | 062751a | 2003-08-26 15:44:01 +0000 | [diff] [blame] | 1329 | int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1330 | int numverts = (int)prim->numverts; |
Keith Whitwell | 9e7d617 | 2003-06-16 10:40:52 +0000 | [diff] [blame] | 1331 | int nbox = sarea_priv->nbox; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1332 | int i = 0; |
| 1333 | RING_LOCALS; |
| 1334 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1335 | DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n", |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1336 | prim->prim, |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1337 | prim->vc_format, prim->start, prim->finish, prim->numverts); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1338 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1339 | if (bad_prim_vertex_nr(prim->prim, prim->numverts)) { |
| 1340 | DRM_ERROR("bad prim %x numverts %d\n", |
| 1341 | prim->prim, prim->numverts); |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 1342 | return; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1343 | } |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1344 | |
| 1345 | do { |
| 1346 | /* Emit the next cliprect */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1347 | if (i < nbox) { |
| 1348 | radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1349 | } |
| 1350 | |
| 1351 | /* Emit the vertex buffer rendering commands */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1352 | BEGIN_RING(5); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1353 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1354 | OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3)); |
| 1355 | OUT_RING(offset); |
| 1356 | OUT_RING(numverts); |
| 1357 | OUT_RING(prim->vc_format); |
| 1358 | OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST | |
| 1359 | RADEON_COLOR_ORDER_RGBA | |
| 1360 | RADEON_VTX_FMT_RADEON_MODE | |
| 1361 | (numverts << RADEON_NUM_VERTICES_SHIFT)); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1362 | |
| 1363 | ADVANCE_RING(); |
| 1364 | |
| 1365 | i++; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1366 | } while (i < nbox); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1367 | } |
| 1368 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1369 | static void radeon_cp_discard_buffer(drm_device_t * dev, drm_buf_t * buf) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1370 | { |
| 1371 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1372 | drm_radeon_buf_priv_t *buf_priv = buf->dev_private; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1373 | RING_LOCALS; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1374 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1375 | buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1376 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1377 | /* Emit the vertex buffer age */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1378 | BEGIN_RING(2); |
| 1379 | RADEON_DISPATCH_AGE(buf_priv->age); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1380 | ADVANCE_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1381 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1382 | buf->pending = 1; |
| 1383 | buf->used = 0; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1384 | } |
| 1385 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1386 | static void radeon_cp_dispatch_indirect(drm_device_t * dev, |
| 1387 | drm_buf_t * buf, int start, int end) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1388 | { |
| 1389 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1390 | RING_LOCALS; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1391 | DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1392 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1393 | if (start != end) { |
Michel Daenzer | 062751a | 2003-08-26 15:44:01 +0000 | [diff] [blame] | 1394 | int offset = (dev_priv->gart_buffers_offset |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1395 | + buf->offset + start); |
| 1396 | int dwords = (end - start + 3) / sizeof(u32); |
| 1397 | |
| 1398 | /* Indirect buffer data must be an even number of |
| 1399 | * dwords, so if we've been given an odd number we must |
| 1400 | * pad the data with a Type-2 CP packet. |
| 1401 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1402 | if (dwords & 1) { |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1403 | u32 *data = (u32 *) |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1404 | ((char *)dev->agp_buffer_map->handle |
| 1405 | + buf->offset + start); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1406 | data[dwords++] = RADEON_CP_PACKET2; |
| 1407 | } |
| 1408 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1409 | /* Fire off the indirect buffer */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1410 | BEGIN_RING(3); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1411 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1412 | OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1)); |
| 1413 | OUT_RING(offset); |
| 1414 | OUT_RING(dwords); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1415 | |
| 1416 | ADVANCE_RING(); |
| 1417 | } |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1418 | } |
| 1419 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1420 | static void radeon_cp_dispatch_indices(drm_device_t * dev, |
| 1421 | drm_buf_t * elt_buf, |
| 1422 | drm_radeon_tcl_prim_t * prim) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1423 | { |
| 1424 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Keith Whitwell | 9e7d617 | 2003-06-16 10:40:52 +0000 | [diff] [blame] | 1425 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
Michel Daenzer | 062751a | 2003-08-26 15:44:01 +0000 | [diff] [blame] | 1426 | int offset = dev_priv->gart_buffers_offset + prim->offset; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1427 | u32 *data; |
| 1428 | int dwords; |
| 1429 | int i = 0; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 1430 | int start = prim->start + RADEON_INDEX_PRIM_OFFSET; |
| 1431 | int count = (prim->finish - start) / sizeof(u16); |
Keith Whitwell | 9e7d617 | 2003-06-16 10:40:52 +0000 | [diff] [blame] | 1432 | int nbox = sarea_priv->nbox; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1433 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1434 | DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n", |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1435 | prim->prim, |
| 1436 | prim->vc_format, |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1437 | prim->start, prim->finish, prim->offset, prim->numverts); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1438 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1439 | if (bad_prim_vertex_nr(prim->prim, count)) { |
| 1440 | DRM_ERROR("bad prim %x count %d\n", prim->prim, count); |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 1441 | return; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1442 | } |
| 1443 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1444 | if (start >= prim->finish || (prim->start & 0x7)) { |
| 1445 | DRM_ERROR("buffer prim %d\n", prim->prim); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1446 | return; |
| 1447 | } |
| 1448 | |
| 1449 | dwords = (prim->finish - prim->start + 3) / sizeof(u32); |
| 1450 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1451 | data = (u32 *) ((char *)dev->agp_buffer_map->handle + |
| 1452 | elt_buf->offset + prim->start); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1453 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1454 | data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1455 | data[1] = offset; |
| 1456 | data[2] = prim->numverts; |
| 1457 | data[3] = prim->vc_format; |
| 1458 | data[4] = (prim->prim | |
| 1459 | RADEON_PRIM_WALK_IND | |
| 1460 | RADEON_COLOR_ORDER_RGBA | |
| 1461 | RADEON_VTX_FMT_RADEON_MODE | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1462 | (count << RADEON_NUM_VERTICES_SHIFT)); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1463 | |
| 1464 | do { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1465 | if (i < nbox) |
| 1466 | radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1467 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1468 | radeon_cp_dispatch_indirect(dev, elt_buf, |
| 1469 | prim->start, prim->finish); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1470 | |
| 1471 | i++; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1472 | } while (i < nbox); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1473 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1474 | } |
| 1475 | |
Eric Anholt | ab59dd2 | 2005-07-20 21:17:47 +0000 | [diff] [blame] | 1476 | #define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1477 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1478 | static int radeon_cp_dispatch_texture(DRMFILE filp, |
| 1479 | drm_device_t * dev, |
| 1480 | drm_radeon_texture_t * tex, |
| 1481 | drm_radeon_tex_image_t * image) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1482 | { |
| 1483 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 1484 | drm_file_t *filp_priv; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1485 | drm_buf_t *buf; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1486 | u32 format; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1487 | u32 *buffer; |
Dave Airlie | 02df04d | 2004-07-25 08:47:38 +0000 | [diff] [blame] | 1488 | const u8 __user *data; |
Eric Anholt | ab59dd2 | 2005-07-20 21:17:47 +0000 | [diff] [blame] | 1489 | int size, dwords, tex_width, blit_width, spitch; |
Michel Daenzer | fac2ed4 | 2003-02-06 18:20:00 +0000 | [diff] [blame] | 1490 | u32 height; |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1491 | int i; |
Roland Scheidegger | 732cdc5 | 2005-02-10 19:22:43 +0000 | [diff] [blame] | 1492 | u32 texpitch, microtile; |
Eric Anholt | ab59dd2 | 2005-07-20 21:17:47 +0000 | [diff] [blame] | 1493 | u32 offset; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1494 | RING_LOCALS; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1495 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1496 | DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 1497 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1498 | if (radeon_check_and_fixup_offset(dev_priv, filp_priv, &tex->offset)) { |
| 1499 | DRM_ERROR("Invalid destination offset\n"); |
| 1500 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 1501 | } |
| 1502 | |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 1503 | dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD; |
| 1504 | |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1505 | /* Flush the pixel cache. This ensures no pixel data gets mixed |
| 1506 | * up with the texture data from the host data blit, otherwise |
| 1507 | * part of the texture image may be corrupted. |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1508 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1509 | BEGIN_RING(4); |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1510 | RADEON_FLUSH_CACHE(); |
| 1511 | RADEON_WAIT_UNTIL_IDLE(); |
| 1512 | ADVANCE_RING(); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1513 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1514 | /* The compiler won't optimize away a division by a variable, |
| 1515 | * even if the only legal values are powers of two. Thus, we'll |
| 1516 | * use a shift instead. |
| 1517 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1518 | switch (tex->format) { |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1519 | case RADEON_TXFORMAT_ARGB8888: |
| 1520 | case RADEON_TXFORMAT_RGBA8888: |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1521 | format = RADEON_COLOR_FORMAT_ARGB8888; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1522 | tex_width = tex->width * 4; |
| 1523 | blit_width = image->width * 4; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1524 | break; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1525 | case RADEON_TXFORMAT_AI88: |
| 1526 | case RADEON_TXFORMAT_ARGB1555: |
| 1527 | case RADEON_TXFORMAT_RGB565: |
| 1528 | case RADEON_TXFORMAT_ARGB4444: |
Keith Whitwell | f1c8fe9 | 2002-09-23 17:26:43 +0000 | [diff] [blame] | 1529 | case RADEON_TXFORMAT_VYUY422: |
| 1530 | case RADEON_TXFORMAT_YVYU422: |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1531 | format = RADEON_COLOR_FORMAT_RGB565; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1532 | tex_width = tex->width * 2; |
| 1533 | blit_width = image->width * 2; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1534 | break; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1535 | case RADEON_TXFORMAT_I8: |
| 1536 | case RADEON_TXFORMAT_RGB332: |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1537 | format = RADEON_COLOR_FORMAT_CI8; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1538 | tex_width = tex->width * 1; |
| 1539 | blit_width = image->width * 1; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1540 | break; |
| 1541 | default: |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1542 | DRM_ERROR("invalid texture format %d\n", tex->format); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1543 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1544 | } |
Eric Anholt | ab59dd2 | 2005-07-20 21:17:47 +0000 | [diff] [blame] | 1545 | spitch = blit_width >> 6; |
| 1546 | if (spitch == 0 && image->height > 1) |
| 1547 | return DRM_ERR(EINVAL); |
| 1548 | |
Roland Scheidegger | 732cdc5 | 2005-02-10 19:22:43 +0000 | [diff] [blame] | 1549 | texpitch = tex->pitch; |
| 1550 | if ((texpitch << 22) & RADEON_DST_TILE_MICRO) { |
| 1551 | microtile = 1; |
| 1552 | if (tex_width < 64) { |
| 1553 | texpitch &= ~(RADEON_DST_TILE_MICRO >> 22); |
| 1554 | /* we got tiled coordinates, untile them */ |
| 1555 | image->x *= 2; |
| 1556 | } |
| 1557 | } |
| 1558 | else microtile = 0; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1559 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1560 | DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1561 | |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1562 | do { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1563 | DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n", |
| 1564 | tex->offset >> 10, tex->pitch, tex->format, |
| 1565 | image->x, image->y, image->width, image->height); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1566 | |
Michel Daenzer | fac2ed4 | 2003-02-06 18:20:00 +0000 | [diff] [blame] | 1567 | /* Make a copy of some parameters in case we have to |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1568 | * update them for a multi-pass texture blit. |
| 1569 | */ |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1570 | height = image->height; |
Dave Airlie | 02df04d | 2004-07-25 08:47:38 +0000 | [diff] [blame] | 1571 | data = (const u8 __user *)image->data; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1572 | |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1573 | size = height * blit_width; |
| 1574 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1575 | if (size > RADEON_MAX_TEXTURE_SIZE) { |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1576 | height = RADEON_MAX_TEXTURE_SIZE / blit_width; |
| 1577 | size = height * blit_width; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1578 | } else if (size < 4 && size > 0) { |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1579 | size = 4; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1580 | } else if (size == 0) { |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1581 | return 0; |
| 1582 | } |
| 1583 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1584 | buf = radeon_freelist_get(dev); |
| 1585 | if (0 && !buf) { |
| 1586 | radeon_do_cp_idle(dev_priv); |
| 1587 | buf = radeon_freelist_get(dev); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1588 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1589 | if (!buf) { |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1590 | DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n"); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1591 | if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) |
Dave Airlie | 7809efc | 2004-08-30 09:01:50 +0000 | [diff] [blame] | 1592 | return DRM_ERR(EFAULT); |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1593 | return DRM_ERR(EAGAIN); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1594 | } |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1595 | |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1596 | /* Dispatch the indirect buffer. |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1597 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1598 | buffer = |
| 1599 | (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1600 | dwords = size / 4; |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1601 | |
Roland Scheidegger | 732cdc5 | 2005-02-10 19:22:43 +0000 | [diff] [blame] | 1602 | if (microtile) { |
| 1603 | /* texture micro tiling in use, minimum texture width is thus 16 bytes. |
| 1604 | however, we cannot use blitter directly for texture width < 64 bytes, |
| 1605 | since minimum tex pitch is 64 bytes and we need this to match |
| 1606 | the texture width, otherwise the blitter will tile it wrong. |
| 1607 | Thus, tiling manually in this case. Additionally, need to special |
| 1608 | case tex height = 1, since our actual image will have height 2 |
| 1609 | and we need to ensure we don't read beyond the texture size |
| 1610 | from user space. */ |
| 1611 | if (tex->height == 1) { |
| 1612 | if (tex_width >= 64 || tex_width <= 16) { |
| 1613 | if (DRM_COPY_FROM_USER(buffer, data, |
| 1614 | tex_width * sizeof(u32))) { |
| 1615 | DRM_ERROR("EFAULT on pad, %d bytes\n", |
| 1616 | tex_width); |
| 1617 | return DRM_ERR(EFAULT); |
| 1618 | } |
| 1619 | } else if (tex_width == 32) { |
| 1620 | if (DRM_COPY_FROM_USER(buffer, data, 16)) { |
| 1621 | DRM_ERROR("EFAULT on pad, %d bytes\n", |
| 1622 | tex_width); |
| 1623 | return DRM_ERR(EFAULT); |
| 1624 | } |
| 1625 | if (DRM_COPY_FROM_USER(buffer + 8, data + 16, 16)) { |
| 1626 | DRM_ERROR("EFAULT on pad, %d bytes\n", |
| 1627 | tex_width); |
| 1628 | return DRM_ERR(EFAULT); |
| 1629 | } |
| 1630 | } |
| 1631 | } else if (tex_width >= 64 || tex_width == 16) { |
| 1632 | if (DRM_COPY_FROM_USER(buffer, data, |
| 1633 | dwords * sizeof(u32))) { |
| 1634 | DRM_ERROR("EFAULT on data, %d dwords\n", |
| 1635 | dwords); |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1636 | return DRM_ERR(EFAULT); |
| 1637 | } |
Roland Scheidegger | 732cdc5 | 2005-02-10 19:22:43 +0000 | [diff] [blame] | 1638 | } else if (tex_width < 16) { |
| 1639 | for (i = 0; i < tex->height; i++) { |
| 1640 | if (DRM_COPY_FROM_USER(buffer, data, tex_width)) { |
| 1641 | DRM_ERROR("EFAULT on pad, %d bytes\n", |
| 1642 | tex_width); |
| 1643 | return DRM_ERR(EFAULT); |
| 1644 | } |
| 1645 | buffer += 4; |
| 1646 | data += tex_width; |
| 1647 | } |
| 1648 | } else if (tex_width == 32) { |
| 1649 | /* TODO: make sure this works when not fitting in one buffer |
| 1650 | (i.e. 32bytes x 2048...) */ |
| 1651 | for (i = 0; i < tex->height; i += 2) { |
| 1652 | if (DRM_COPY_FROM_USER(buffer, data, 16)) { |
| 1653 | DRM_ERROR("EFAULT on pad, %d bytes\n", |
| 1654 | tex_width); |
| 1655 | return DRM_ERR(EFAULT); |
| 1656 | } |
| 1657 | data += 16; |
| 1658 | if (DRM_COPY_FROM_USER(buffer + 8, data, 16)) { |
| 1659 | DRM_ERROR("EFAULT on pad, %d bytes\n", |
| 1660 | tex_width); |
| 1661 | return DRM_ERR(EFAULT); |
| 1662 | } |
| 1663 | data += 16; |
| 1664 | if (DRM_COPY_FROM_USER(buffer + 4, data, 16)) { |
| 1665 | DRM_ERROR("EFAULT on pad, %d bytes\n", |
| 1666 | tex_width); |
| 1667 | return DRM_ERR(EFAULT); |
| 1668 | } |
| 1669 | data += 16; |
| 1670 | if (DRM_COPY_FROM_USER(buffer + 12, data, 16)) { |
| 1671 | DRM_ERROR("EFAULT on pad, %d bytes\n", |
| 1672 | tex_width); |
| 1673 | return DRM_ERR(EFAULT); |
| 1674 | } |
| 1675 | data += 16; |
| 1676 | buffer += 16; |
| 1677 | } |
| 1678 | } |
| 1679 | } |
| 1680 | else { |
| 1681 | if (tex_width >= 32) { |
| 1682 | /* Texture image width is larger than the minimum, so we |
| 1683 | * can upload it directly. |
| 1684 | */ |
| 1685 | if (DRM_COPY_FROM_USER(buffer, data, |
| 1686 | dwords * sizeof(u32))) { |
| 1687 | DRM_ERROR("EFAULT on data, %d dwords\n", |
| 1688 | dwords); |
| 1689 | return DRM_ERR(EFAULT); |
| 1690 | } |
| 1691 | } else { |
| 1692 | /* Texture image width is less than the minimum, so we |
| 1693 | * need to pad out each image scanline to the minimum |
| 1694 | * width. |
| 1695 | */ |
| 1696 | for (i = 0; i < tex->height; i++) { |
| 1697 | if (DRM_COPY_FROM_USER(buffer, data, tex_width)) { |
| 1698 | DRM_ERROR("EFAULT on pad, %d bytes\n", |
| 1699 | tex_width); |
| 1700 | return DRM_ERR(EFAULT); |
| 1701 | } |
| 1702 | buffer += 8; |
| 1703 | data += tex_width; |
| 1704 | } |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1705 | } |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1706 | } |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1707 | |
Keith Whitwell | 1728bc6 | 2003-03-28 14:27:37 +0000 | [diff] [blame] | 1708 | buf->filp = filp; |
Eric Anholt | ab59dd2 | 2005-07-20 21:17:47 +0000 | [diff] [blame] | 1709 | buf->used = size; |
| 1710 | offset = dev_priv->gart_buffers_offset + buf->offset; |
| 1711 | BEGIN_RING(9); |
| 1712 | OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5)); |
| 1713 | OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
| 1714 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| 1715 | RADEON_GMC_BRUSH_NONE | |
| 1716 | (format << 8) | |
| 1717 | RADEON_GMC_SRC_DATATYPE_COLOR | |
| 1718 | RADEON_ROP3_S | |
| 1719 | RADEON_DP_SRC_SOURCE_MEMORY | |
| 1720 | RADEON_GMC_CLR_CMP_CNTL_DIS | |
| 1721 | RADEON_GMC_WR_MSK_DIS ); |
| 1722 | OUT_RING((spitch << 22) | (offset >> 10)); |
| 1723 | OUT_RING((texpitch << 22) | (tex->offset >> 10)); |
| 1724 | OUT_RING(0); |
| 1725 | OUT_RING((image->x << 16) | image->y); |
| 1726 | OUT_RING((image->width << 16) | height); |
| 1727 | RADEON_WAIT_UNTIL_2D_IDLE(); |
| 1728 | ADVANCE_RING(); |
| 1729 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1730 | radeon_cp_discard_buffer(dev, buf); |
David Dawes | 0e5b8d7 | 2001-03-19 17:45:52 +0000 | [diff] [blame] | 1731 | |
Michel Daenzer | fac2ed4 | 2003-02-06 18:20:00 +0000 | [diff] [blame] | 1732 | /* Update the input parameters for next time */ |
| 1733 | image->y += height; |
| 1734 | image->height -= height; |
Dave Airlie | 02df04d | 2004-07-25 08:47:38 +0000 | [diff] [blame] | 1735 | image->data = (const u8 __user *)image->data + size; |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1736 | } while (image->height > 0); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1737 | |
| 1738 | /* Flush the pixel cache after the blit completes. This ensures |
| 1739 | * the texture data is written out to memory before rendering |
| 1740 | * continues. |
| 1741 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1742 | BEGIN_RING(4); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1743 | RADEON_FLUSH_CACHE(); |
| 1744 | RADEON_WAIT_UNTIL_2D_IDLE(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1745 | ADVANCE_RING(); |
Keith Whitwell | b03fa55 | 2002-12-06 12:22:43 +0000 | [diff] [blame] | 1746 | return 0; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1747 | } |
| 1748 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1749 | static void radeon_cp_dispatch_stipple(drm_device_t * dev, u32 * stipple) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1750 | { |
| 1751 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1752 | int i; |
| 1753 | RING_LOCALS; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1754 | DRM_DEBUG("\n"); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1755 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1756 | BEGIN_RING(35); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1757 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1758 | OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0)); |
| 1759 | OUT_RING(0x00000000); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1760 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1761 | OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31)); |
| 1762 | for (i = 0; i < 32; i++) { |
| 1763 | OUT_RING(stipple[i]); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1764 | } |
| 1765 | |
| 1766 | ADVANCE_RING(); |
| 1767 | } |
| 1768 | |
Roland Scheidegger | 43c3223 | 2005-01-26 17:48:59 +0000 | [diff] [blame] | 1769 | static void radeon_apply_surface_regs(int surf_index, drm_radeon_private_t *dev_priv) |
| 1770 | { |
| 1771 | if (!dev_priv->mmio) |
| 1772 | return; |
| 1773 | |
| 1774 | radeon_do_cp_idle(dev_priv); |
| 1775 | |
| 1776 | RADEON_WRITE(RADEON_SURFACE0_INFO + 16*surf_index, |
| 1777 | dev_priv->surfaces[surf_index].flags); |
| 1778 | RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16*surf_index, |
| 1779 | dev_priv->surfaces[surf_index].lower); |
| 1780 | RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16*surf_index, |
| 1781 | dev_priv->surfaces[surf_index].upper); |
| 1782 | } |
| 1783 | |
| 1784 | /* Allocates a virtual surface |
| 1785 | * doesn't always allocate a real surface, will stretch an existing |
| 1786 | * surface when possible. |
| 1787 | * |
| 1788 | * Note that refcount can be at most 2, since during a free refcount=3 |
| 1789 | * might mean we have to allocate a new surface which might not always |
| 1790 | * be available. |
| 1791 | * For example : we allocate three contigous surfaces ABC. If B is |
| 1792 | * freed, we suddenly need two surfaces to store A and C, which might |
| 1793 | * not always be available. |
| 1794 | */ |
| 1795 | static int alloc_surface(drm_radeon_surface_alloc_t* new, drm_radeon_private_t *dev_priv, DRMFILE filp) |
| 1796 | { |
| 1797 | struct radeon_virt_surface *s; |
| 1798 | int i; |
| 1799 | int virt_surface_index; |
| 1800 | uint32_t new_upper, new_lower; |
| 1801 | |
| 1802 | new_lower = new->address; |
| 1803 | new_upper = new_lower + new->size - 1; |
| 1804 | |
| 1805 | /* sanity check */ |
| 1806 | if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) || |
| 1807 | ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) != RADEON_SURF_ADDRESS_FIXED_MASK) || |
| 1808 | ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0)) |
| 1809 | return -1; |
| 1810 | |
| 1811 | /* make sure there is no overlap with existing surfaces */ |
| 1812 | for (i = 0; i < RADEON_MAX_SURFACES; i++) { |
| 1813 | if ((dev_priv->surfaces[i].refcount != 0) && |
| 1814 | (( (new_lower >= dev_priv->surfaces[i].lower) && |
| 1815 | (new_lower < dev_priv->surfaces[i].upper) ) || |
| 1816 | ( (new_lower < dev_priv->surfaces[i].lower) && |
| 1817 | (new_upper > dev_priv->surfaces[i].lower) )) ){ |
| 1818 | return -1;} |
| 1819 | } |
| 1820 | |
| 1821 | /* find a virtual surface */ |
| 1822 | for (i = 0; i < 2*RADEON_MAX_SURFACES; i++) |
| 1823 | if (dev_priv->virt_surfaces[i].filp == 0) |
| 1824 | break; |
| 1825 | if (i == 2*RADEON_MAX_SURFACES) { |
| 1826 | return -1;} |
| 1827 | virt_surface_index = i; |
| 1828 | |
| 1829 | /* try to reuse an existing surface */ |
| 1830 | for (i = 0; i < RADEON_MAX_SURFACES; i++) { |
| 1831 | /* extend before */ |
| 1832 | if ((dev_priv->surfaces[i].refcount == 1) && |
| 1833 | (new->flags == dev_priv->surfaces[i].flags) && |
| 1834 | (new_upper + 1 == dev_priv->surfaces[i].lower)) { |
| 1835 | s = &(dev_priv->virt_surfaces[virt_surface_index]); |
| 1836 | s->surface_index = i; |
| 1837 | s->lower = new_lower; |
| 1838 | s->upper = new_upper; |
| 1839 | s->flags = new->flags; |
| 1840 | s->filp = filp; |
| 1841 | dev_priv->surfaces[i].refcount++; |
| 1842 | dev_priv->surfaces[i].lower = s->lower; |
| 1843 | radeon_apply_surface_regs(s->surface_index, dev_priv); |
| 1844 | return virt_surface_index; |
| 1845 | } |
| 1846 | |
| 1847 | /* extend after */ |
| 1848 | if ((dev_priv->surfaces[i].refcount == 1) && |
| 1849 | (new->flags == dev_priv->surfaces[i].flags) && |
| 1850 | (new_lower == dev_priv->surfaces[i].upper + 1)) { |
| 1851 | s = &(dev_priv->virt_surfaces[virt_surface_index]); |
| 1852 | s->surface_index = i; |
| 1853 | s->lower = new_lower; |
| 1854 | s->upper = new_upper; |
| 1855 | s->flags = new->flags; |
| 1856 | s->filp = filp; |
| 1857 | dev_priv->surfaces[i].refcount++; |
| 1858 | dev_priv->surfaces[i].upper = s->upper; |
| 1859 | radeon_apply_surface_regs(s->surface_index, dev_priv); |
| 1860 | return virt_surface_index; |
| 1861 | } |
| 1862 | } |
| 1863 | |
| 1864 | /* okay, we need a new one */ |
| 1865 | for (i = 0; i < RADEON_MAX_SURFACES; i++) { |
| 1866 | if (dev_priv->surfaces[i].refcount == 0) { |
| 1867 | s = &(dev_priv->virt_surfaces[virt_surface_index]); |
| 1868 | s->surface_index = i; |
| 1869 | s->lower = new_lower; |
| 1870 | s->upper = new_upper; |
| 1871 | s->flags = new->flags; |
| 1872 | s->filp = filp; |
| 1873 | dev_priv->surfaces[i].refcount = 1; |
| 1874 | dev_priv->surfaces[i].lower = s->lower; |
| 1875 | dev_priv->surfaces[i].upper = s->upper; |
| 1876 | dev_priv->surfaces[i].flags = s->flags; |
| 1877 | radeon_apply_surface_regs(s->surface_index, dev_priv); |
| 1878 | return virt_surface_index; |
| 1879 | } |
| 1880 | } |
| 1881 | |
| 1882 | /* we didn't find anything */ |
| 1883 | return -1; |
| 1884 | } |
| 1885 | |
| 1886 | static int free_surface(DRMFILE filp, drm_radeon_private_t *dev_priv, int lower) |
| 1887 | { |
| 1888 | struct radeon_virt_surface *s; |
| 1889 | int i; |
| 1890 | /* find the virtual surface */ |
| 1891 | for(i = 0; i < 2*RADEON_MAX_SURFACES; i++) { |
| 1892 | s = &(dev_priv->virt_surfaces[i]); |
| 1893 | if (s->filp) { |
| 1894 | if ((lower == s->lower) && (filp == s->filp)) { |
| 1895 | if (dev_priv->surfaces[s->surface_index].lower == s->lower) |
| 1896 | dev_priv->surfaces[s->surface_index].lower = s->upper; |
| 1897 | |
| 1898 | if (dev_priv->surfaces[s->surface_index].upper == s->upper) |
| 1899 | dev_priv->surfaces[s->surface_index].upper = s->lower; |
| 1900 | |
| 1901 | dev_priv->surfaces[s->surface_index].refcount--; |
| 1902 | if (dev_priv->surfaces[s->surface_index].refcount == 0) |
| 1903 | dev_priv->surfaces[s->surface_index].flags = 0; |
| 1904 | s->filp = 0; |
| 1905 | radeon_apply_surface_regs(s->surface_index, dev_priv); |
| 1906 | return 0; |
| 1907 | } |
| 1908 | } |
| 1909 | } |
| 1910 | return 1; |
| 1911 | } |
| 1912 | |
| 1913 | static void radeon_surfaces_release(DRMFILE filp, drm_radeon_private_t *dev_priv) |
| 1914 | { |
| 1915 | int i; |
| 1916 | for( i = 0; i < 2*RADEON_MAX_SURFACES; i++) |
| 1917 | { |
| 1918 | if (dev_priv->virt_surfaces[i].filp == filp) |
| 1919 | free_surface(filp, dev_priv, dev_priv->virt_surfaces[i].lower); |
| 1920 | } |
| 1921 | } |
| 1922 | |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1923 | /* ================================================================ |
| 1924 | * IOCTL functions |
| 1925 | */ |
| 1926 | |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 1927 | static int radeon_surface_alloc(DRM_IOCTL_ARGS) |
Roland Scheidegger | 43c3223 | 2005-01-26 17:48:59 +0000 | [diff] [blame] | 1928 | { |
| 1929 | DRM_DEVICE; |
| 1930 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1931 | drm_radeon_surface_alloc_t alloc; |
| 1932 | |
| 1933 | if (!dev_priv) { |
| 1934 | DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); |
| 1935 | return DRM_ERR(EINVAL); |
| 1936 | } |
| 1937 | |
| 1938 | DRM_COPY_FROM_USER_IOCTL(alloc, (drm_radeon_surface_alloc_t __user *)data, |
| 1939 | sizeof(alloc)); |
| 1940 | |
| 1941 | if (alloc_surface(&alloc, dev_priv, filp) == -1) |
| 1942 | return DRM_ERR(EINVAL); |
| 1943 | else |
| 1944 | return 0; |
| 1945 | } |
| 1946 | |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 1947 | static int radeon_surface_free(DRM_IOCTL_ARGS) |
Roland Scheidegger | 43c3223 | 2005-01-26 17:48:59 +0000 | [diff] [blame] | 1948 | { |
| 1949 | DRM_DEVICE; |
| 1950 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1951 | drm_radeon_surface_free_t memfree; |
| 1952 | |
| 1953 | if (!dev_priv) { |
| 1954 | DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ ); |
| 1955 | return DRM_ERR(EINVAL); |
| 1956 | } |
| 1957 | |
Eric Anholt | ed31275 | 2005-02-03 01:05:34 +0000 | [diff] [blame] | 1958 | DRM_COPY_FROM_USER_IOCTL(memfree, (drm_radeon_surface_free_t __user *)data, |
Roland Scheidegger | 43c3223 | 2005-01-26 17:48:59 +0000 | [diff] [blame] | 1959 | sizeof(memfree) ); |
| 1960 | |
| 1961 | if (free_surface(filp, dev_priv, memfree.address)) |
| 1962 | return DRM_ERR(EINVAL); |
| 1963 | else |
| 1964 | return 0; |
| 1965 | } |
| 1966 | |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 1967 | static int radeon_cp_clear(DRM_IOCTL_ARGS) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1968 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1969 | DRM_DEVICE; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1970 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 1971 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
| 1972 | drm_radeon_clear_t clear; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1973 | drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1974 | DRM_DEBUG("\n"); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1975 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1976 | LOCK_TEST_WITH_RETURN(dev, filp); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1977 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1978 | DRM_COPY_FROM_USER_IOCTL(clear, (drm_radeon_clear_t __user *) data, |
| 1979 | sizeof(clear)); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1980 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1981 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1982 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1983 | if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1984 | sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; |
| 1985 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1986 | if (DRM_COPY_FROM_USER(&depth_boxes, clear.depth_boxes, |
| 1987 | sarea_priv->nbox * sizeof(depth_boxes[0]))) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 1988 | return DRM_ERR(EFAULT); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 1989 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1990 | radeon_cp_dispatch_clear(dev, &clear, depth_boxes); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 1991 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1992 | COMMIT_RING(); |
| 1993 | return 0; |
| 1994 | } |
| 1995 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1996 | /* Not sure why this isn't set all the time: |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 1997 | */ |
| 1998 | static int radeon_do_init_pageflip(drm_device_t * dev) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 1999 | { |
| 2000 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Keith Whitwell | 24025ca | 2002-07-04 12:03:15 +0000 | [diff] [blame] | 2001 | RING_LOCALS; |
| 2002 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2003 | DRM_DEBUG("\n"); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2004 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2005 | BEGIN_RING(6); |
Keith Whitwell | 24025ca | 2002-07-04 12:03:15 +0000 | [diff] [blame] | 2006 | RADEON_WAIT_UNTIL_3D_IDLE(); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2007 | OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0)); |
| 2008 | OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) | |
| 2009 | RADEON_CRTC_OFFSET_FLIP_CNTL); |
| 2010 | OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0)); |
| 2011 | OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) | |
| 2012 | RADEON_CRTC_OFFSET_FLIP_CNTL); |
Keith Whitwell | 24025ca | 2002-07-04 12:03:15 +0000 | [diff] [blame] | 2013 | ADVANCE_RING(); |
| 2014 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2015 | dev_priv->page_flipping = 1; |
| 2016 | dev_priv->current_page = 0; |
Keith Whitwell | bb91bc0 | 2002-06-27 17:56:39 +0000 | [diff] [blame] | 2017 | dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2018 | |
| 2019 | return 0; |
| 2020 | } |
| 2021 | |
Jon Smirl | fa6b1d1 | 2004-09-27 19:51:38 +0000 | [diff] [blame] | 2022 | /* Called whenever a client dies, from drm_release. |
Keith Whitwell | f1c8fe9 | 2002-09-23 17:26:43 +0000 | [diff] [blame] | 2023 | * NOTE: Lock isn't necessarily held when this is called! |
| 2024 | */ |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 2025 | static int radeon_do_cleanup_pageflip(drm_device_t * dev) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2026 | { |
| 2027 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2028 | DRM_DEBUG("\n"); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2029 | |
Keith Whitwell | 24025ca | 2002-07-04 12:03:15 +0000 | [diff] [blame] | 2030 | if (dev_priv->current_page != 0) |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2031 | radeon_cp_dispatch_flip(dev); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2032 | |
| 2033 | dev_priv->page_flipping = 0; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2034 | return 0; |
| 2035 | } |
| 2036 | |
| 2037 | /* Swapping and flipping are different operations, need different ioctls. |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2038 | * They can & should be intermixed to support multiple 3d windows. |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2039 | */ |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 2040 | static int radeon_cp_flip(DRM_IOCTL_ARGS) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2041 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2042 | DRM_DEVICE; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2043 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2044 | DRM_DEBUG("\n"); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2045 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2046 | LOCK_TEST_WITH_RETURN(dev, filp); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2047 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2048 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2049 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2050 | if (!dev_priv->page_flipping) |
| 2051 | radeon_do_init_pageflip(dev); |
| 2052 | |
| 2053 | radeon_cp_dispatch_flip(dev); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2054 | |
| 2055 | COMMIT_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2056 | return 0; |
| 2057 | } |
| 2058 | |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 2059 | static int radeon_cp_swap(DRM_IOCTL_ARGS) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2060 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2061 | DRM_DEVICE; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2062 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 2063 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2064 | DRM_DEBUG("\n"); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2065 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2066 | LOCK_TEST_WITH_RETURN(dev, filp); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 2067 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2068 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
Gareth Hughes | 4d2a445 | 2001-01-24 15:34:46 +0000 | [diff] [blame] | 2069 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2070 | if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2071 | sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; |
| 2072 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2073 | radeon_cp_dispatch_swap(dev); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2074 | dev_priv->sarea_priv->ctx_owner = 0; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2075 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2076 | COMMIT_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2077 | return 0; |
| 2078 | } |
| 2079 | |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 2080 | static int radeon_cp_vertex(DRM_IOCTL_ARGS) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2081 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2082 | DRM_DEVICE; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2083 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2084 | drm_file_t *filp_priv; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2085 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2086 | drm_device_dma_t *dma = dev->dma; |
| 2087 | drm_buf_t *buf; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2088 | drm_radeon_vertex_t vertex; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2089 | drm_radeon_tcl_prim_t prim; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2090 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2091 | LOCK_TEST_WITH_RETURN(dev, filp); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 2092 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2093 | if (!dev_priv) { |
| 2094 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2095 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2096 | } |
| 2097 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2098 | DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2099 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2100 | DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex_t __user *) data, |
| 2101 | sizeof(vertex)); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2102 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2103 | DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", |
| 2104 | DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2105 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2106 | if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { |
| 2107 | DRM_ERROR("buffer index %d (of %d max)\n", |
| 2108 | vertex.idx, dma->buf_count - 1); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2109 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2110 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2111 | if (vertex.prim < 0 || vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { |
| 2112 | DRM_ERROR("buffer prim %d\n", vertex.prim); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2113 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2114 | } |
| 2115 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2116 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
| 2117 | VB_AGE_TEST_WITH_RETURN(dev_priv); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2118 | |
| 2119 | buf = dma->buflist[vertex.idx]; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2120 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2121 | if (buf->filp != filp) { |
| 2122 | DRM_ERROR("process %d using buffer owned by %p\n", |
| 2123 | DRM_CURRENTPID, buf->filp); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2124 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2125 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2126 | if (buf->pending) { |
| 2127 | DRM_ERROR("sending pending buffer %d\n", vertex.idx); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2128 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2129 | } |
| 2130 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2131 | /* Build up a prim_t record: |
| 2132 | */ |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 2133 | if (vertex.count) { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2134 | buf->used = vertex.count; /* not used? */ |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2135 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2136 | if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { |
| 2137 | if (radeon_emit_state(dev_priv, filp_priv, |
| 2138 | &sarea_priv->context_state, |
| 2139 | sarea_priv->tex_state, |
| 2140 | sarea_priv->dirty)) { |
| 2141 | DRM_ERROR("radeon_emit_state failed\n"); |
| 2142 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2143 | } |
| 2144 | |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 2145 | sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | |
| 2146 | RADEON_UPLOAD_TEX1IMAGES | |
| 2147 | RADEON_UPLOAD_TEX2IMAGES | |
| 2148 | RADEON_REQUIRE_QUIESCENCE); |
| 2149 | } |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2150 | |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 2151 | prim.start = 0; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2152 | prim.finish = vertex.count; /* unused */ |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 2153 | prim.prim = vertex.prim; |
Keith Whitwell | baef086 | 2002-03-08 16:03:37 +0000 | [diff] [blame] | 2154 | prim.numverts = vertex.count; |
| 2155 | prim.vc_format = dev_priv->sarea_priv->vc_format; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2156 | |
| 2157 | radeon_cp_dispatch_vertex(dev, buf, &prim); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2158 | } |
| 2159 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2160 | if (vertex.discard) { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2161 | radeon_cp_discard_buffer(dev, buf); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2162 | } |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2163 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2164 | COMMIT_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2165 | return 0; |
| 2166 | } |
| 2167 | |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 2168 | static int radeon_cp_indices(DRM_IOCTL_ARGS) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2169 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2170 | DRM_DEVICE; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2171 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2172 | drm_file_t *filp_priv; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2173 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2174 | drm_device_dma_t *dma = dev->dma; |
| 2175 | drm_buf_t *buf; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2176 | drm_radeon_indices_t elts; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2177 | drm_radeon_tcl_prim_t prim; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2178 | int count; |
| 2179 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2180 | LOCK_TEST_WITH_RETURN(dev, filp); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 2181 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2182 | if (!dev_priv) { |
| 2183 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2184 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2185 | } |
| 2186 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2187 | DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2188 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2189 | DRM_COPY_FROM_USER_IOCTL(elts, (drm_radeon_indices_t __user *) data, |
| 2190 | sizeof(elts)); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2191 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2192 | DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n", |
| 2193 | DRM_CURRENTPID, elts.idx, elts.start, elts.end, elts.discard); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2194 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2195 | if (elts.idx < 0 || elts.idx >= dma->buf_count) { |
| 2196 | DRM_ERROR("buffer index %d (of %d max)\n", |
| 2197 | elts.idx, dma->buf_count - 1); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2198 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2199 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2200 | if (elts.prim < 0 || elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { |
| 2201 | DRM_ERROR("buffer prim %d\n", elts.prim); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2202 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2203 | } |
| 2204 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2205 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
| 2206 | VB_AGE_TEST_WITH_RETURN(dev_priv); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2207 | |
| 2208 | buf = dma->buflist[elts.idx]; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2209 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2210 | if (buf->filp != filp) { |
| 2211 | DRM_ERROR("process %d using buffer owned by %p\n", |
| 2212 | DRM_CURRENTPID, buf->filp); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2213 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2214 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2215 | if (buf->pending) { |
| 2216 | DRM_ERROR("sending pending buffer %d\n", elts.idx); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2217 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2218 | } |
| 2219 | |
| 2220 | count = (elts.end - elts.start) / sizeof(u16); |
| 2221 | elts.start -= RADEON_INDEX_PRIM_OFFSET; |
| 2222 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2223 | if (elts.start & 0x7) { |
| 2224 | DRM_ERROR("misaligned buffer 0x%x\n", elts.start); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2225 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2226 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2227 | if (elts.start < buf->used) { |
| 2228 | DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2229 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2230 | } |
| 2231 | |
| 2232 | buf->used = elts.end; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2233 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2234 | if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { |
| 2235 | if (radeon_emit_state(dev_priv, filp_priv, |
| 2236 | &sarea_priv->context_state, |
| 2237 | sarea_priv->tex_state, |
| 2238 | sarea_priv->dirty)) { |
| 2239 | DRM_ERROR("radeon_emit_state failed\n"); |
| 2240 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2241 | } |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2242 | |
| 2243 | sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | |
| 2244 | RADEON_UPLOAD_TEX1IMAGES | |
| 2245 | RADEON_UPLOAD_TEX2IMAGES | |
| 2246 | RADEON_REQUIRE_QUIESCENCE); |
| 2247 | } |
| 2248 | |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2249 | /* Build up a prim_t record: |
| 2250 | */ |
| 2251 | prim.start = elts.start; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2252 | prim.finish = elts.end; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2253 | prim.prim = elts.prim; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2254 | prim.offset = 0; /* offset from start of dma buffers */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2255 | prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2256 | prim.vc_format = dev_priv->sarea_priv->vc_format; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2257 | |
| 2258 | radeon_cp_dispatch_indices(dev, buf, &prim); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2259 | if (elts.discard) { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2260 | radeon_cp_discard_buffer(dev, buf); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2261 | } |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2262 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2263 | COMMIT_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2264 | return 0; |
| 2265 | } |
| 2266 | |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 2267 | static int radeon_cp_texture(DRM_IOCTL_ARGS) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2268 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2269 | DRM_DEVICE; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2270 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 2271 | drm_radeon_texture_t tex; |
| 2272 | drm_radeon_tex_image_t image; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2273 | int ret; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2274 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2275 | LOCK_TEST_WITH_RETURN(dev, filp); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2276 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2277 | DRM_COPY_FROM_USER_IOCTL(tex, (drm_radeon_texture_t __user *) data, |
| 2278 | sizeof(tex)); |
Gareth Hughes | 3a74d3a | 2001-03-06 04:37:37 +0000 | [diff] [blame] | 2279 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2280 | if (tex.image == NULL) { |
| 2281 | DRM_ERROR("null texture image!\n"); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2282 | return DRM_ERR(EINVAL); |
David Dawes | 0e5b8d7 | 2001-03-19 17:45:52 +0000 | [diff] [blame] | 2283 | } |
| 2284 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2285 | if (DRM_COPY_FROM_USER(&image, |
| 2286 | (drm_radeon_tex_image_t __user *) tex.image, |
| 2287 | sizeof(image))) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2288 | return DRM_ERR(EFAULT); |
David Dawes | 0e5b8d7 | 2001-03-19 17:45:52 +0000 | [diff] [blame] | 2289 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2290 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
| 2291 | VB_AGE_TEST_WITH_RETURN(dev_priv); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 2292 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2293 | ret = radeon_cp_dispatch_texture(filp, dev, &tex, &image); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2294 | |
| 2295 | COMMIT_RING(); |
| 2296 | return ret; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2297 | } |
| 2298 | |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 2299 | static int radeon_cp_stipple(DRM_IOCTL_ARGS) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2300 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2301 | DRM_DEVICE; |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 2302 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2303 | drm_radeon_stipple_t stipple; |
| 2304 | u32 mask[32]; |
| 2305 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2306 | LOCK_TEST_WITH_RETURN(dev, filp); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2307 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2308 | DRM_COPY_FROM_USER_IOCTL(stipple, (drm_radeon_stipple_t __user *) data, |
| 2309 | sizeof(stipple)); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2310 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2311 | if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32))) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2312 | return DRM_ERR(EFAULT); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2313 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2314 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 2315 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2316 | radeon_cp_dispatch_stipple(dev, mask); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2317 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2318 | COMMIT_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2319 | return 0; |
| 2320 | } |
| 2321 | |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 2322 | static int radeon_cp_indirect(DRM_IOCTL_ARGS) |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2323 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2324 | DRM_DEVICE; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2325 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 2326 | drm_device_dma_t *dma = dev->dma; |
| 2327 | drm_buf_t *buf; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2328 | drm_radeon_indirect_t indirect; |
| 2329 | RING_LOCALS; |
| 2330 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2331 | LOCK_TEST_WITH_RETURN(dev, filp); |
Kevin E Martin | 5d6ddbc | 2001-04-05 22:16:12 +0000 | [diff] [blame] | 2332 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2333 | if (!dev_priv) { |
| 2334 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2335 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2336 | } |
| 2337 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2338 | DRM_COPY_FROM_USER_IOCTL(indirect, |
| 2339 | (drm_radeon_indirect_t __user *) data, |
| 2340 | sizeof(indirect)); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2341 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2342 | DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n", |
| 2343 | indirect.idx, indirect.start, indirect.end, indirect.discard); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2344 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2345 | if (indirect.idx < 0 || indirect.idx >= dma->buf_count) { |
| 2346 | DRM_ERROR("buffer index %d (of %d max)\n", |
| 2347 | indirect.idx, dma->buf_count - 1); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2348 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2349 | } |
| 2350 | |
| 2351 | buf = dma->buflist[indirect.idx]; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2352 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2353 | if (buf->filp != filp) { |
| 2354 | DRM_ERROR("process %d using buffer owned by %p\n", |
| 2355 | DRM_CURRENTPID, buf->filp); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2356 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2357 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2358 | if (buf->pending) { |
| 2359 | DRM_ERROR("sending pending buffer %d\n", indirect.idx); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2360 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2361 | } |
| 2362 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2363 | if (indirect.start < buf->used) { |
| 2364 | DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", |
| 2365 | indirect.start, buf->used); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2366 | return DRM_ERR(EINVAL); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2367 | } |
| 2368 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2369 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
| 2370 | VB_AGE_TEST_WITH_RETURN(dev_priv); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2371 | |
| 2372 | buf->used = indirect.end; |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2373 | |
| 2374 | /* Wait for the 3D stream to idle before the indirect buffer |
| 2375 | * containing 2D acceleration commands is processed. |
| 2376 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2377 | BEGIN_RING(2); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2378 | |
| 2379 | RADEON_WAIT_UNTIL_3D_IDLE(); |
| 2380 | |
| 2381 | ADVANCE_RING(); |
| 2382 | |
| 2383 | /* Dispatch the indirect buffer full of commands from the |
| 2384 | * X server. This is insecure and is thus only available to |
| 2385 | * privileged clients. |
| 2386 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2387 | radeon_cp_dispatch_indirect(dev, buf, indirect.start, indirect.end); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2388 | if (indirect.discard) { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2389 | radeon_cp_discard_buffer(dev, buf); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2390 | } |
| 2391 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2392 | COMMIT_RING(); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2393 | return 0; |
| 2394 | } |
| 2395 | |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 2396 | static int radeon_cp_vertex2(DRM_IOCTL_ARGS) |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2397 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2398 | DRM_DEVICE; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2399 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2400 | drm_file_t *filp_priv; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2401 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2402 | drm_device_dma_t *dma = dev->dma; |
| 2403 | drm_buf_t *buf; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2404 | drm_radeon_vertex2_t vertex; |
| 2405 | int i; |
| 2406 | unsigned char laststate; |
| 2407 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2408 | LOCK_TEST_WITH_RETURN(dev, filp); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2409 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2410 | if (!dev_priv) { |
| 2411 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2412 | return DRM_ERR(EINVAL); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2413 | } |
| 2414 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2415 | DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2416 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2417 | DRM_COPY_FROM_USER_IOCTL(vertex, (drm_radeon_vertex2_t __user *) data, |
| 2418 | sizeof(vertex)); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2419 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2420 | DRM_DEBUG("pid=%d index=%d discard=%d\n", |
| 2421 | DRM_CURRENTPID, vertex.idx, vertex.discard); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2422 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2423 | if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { |
| 2424 | DRM_ERROR("buffer index %d (of %d max)\n", |
| 2425 | vertex.idx, dma->buf_count - 1); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2426 | return DRM_ERR(EINVAL); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2427 | } |
| 2428 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2429 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
| 2430 | VB_AGE_TEST_WITH_RETURN(dev_priv); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2431 | |
| 2432 | buf = dma->buflist[vertex.idx]; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2433 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2434 | if (buf->filp != filp) { |
| 2435 | DRM_ERROR("process %d using buffer owned by %p\n", |
| 2436 | DRM_CURRENTPID, buf->filp); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2437 | return DRM_ERR(EINVAL); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2438 | } |
| 2439 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2440 | if (buf->pending) { |
| 2441 | DRM_ERROR("sending pending buffer %d\n", vertex.idx); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2442 | return DRM_ERR(EINVAL); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2443 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2444 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2445 | if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2446 | return DRM_ERR(EINVAL); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2447 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2448 | for (laststate = 0xff, i = 0; i < vertex.nr_prims; i++) { |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2449 | drm_radeon_prim_t prim; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2450 | drm_radeon_tcl_prim_t tclprim; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2451 | |
| 2452 | if (DRM_COPY_FROM_USER(&prim, &vertex.prim[i], sizeof(prim))) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2453 | return DRM_ERR(EFAULT); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2454 | |
| 2455 | if (prim.stateidx != laststate) { |
| 2456 | drm_radeon_state_t state; |
| 2457 | |
| 2458 | if (DRM_COPY_FROM_USER(&state, |
| 2459 | &vertex.state[prim.stateidx], |
| 2460 | sizeof(state))) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2461 | return DRM_ERR(EFAULT); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2462 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2463 | if (radeon_emit_state2(dev_priv, filp_priv, &state)) { |
| 2464 | DRM_ERROR("radeon_emit_state2 failed\n"); |
| 2465 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2466 | } |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2467 | |
| 2468 | laststate = prim.stateidx; |
| 2469 | } |
| 2470 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2471 | tclprim.start = prim.start; |
| 2472 | tclprim.finish = prim.finish; |
| 2473 | tclprim.prim = prim.prim; |
| 2474 | tclprim.vc_format = prim.vc_format; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2475 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2476 | if (prim.prim & RADEON_PRIM_WALK_IND) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2477 | tclprim.offset = prim.numverts * 64; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2478 | tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2479 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2480 | radeon_cp_dispatch_indices(dev, buf, &tclprim); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2481 | } else { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2482 | tclprim.numverts = prim.numverts; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2483 | tclprim.offset = 0; /* not used */ |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2484 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2485 | radeon_cp_dispatch_vertex(dev, buf, &tclprim); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2486 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2487 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2488 | if (sarea_priv->nbox == 1) |
| 2489 | sarea_priv->nbox = 0; |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2490 | } |
| 2491 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2492 | if (vertex.discard) { |
| 2493 | radeon_cp_discard_buffer(dev, buf); |
David Dawes | ab87c5d | 2002-02-14 02:00:26 +0000 | [diff] [blame] | 2494 | } |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2495 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2496 | COMMIT_RING(); |
Kevin E Martin | 0994e63 | 2001-01-05 22:57:55 +0000 | [diff] [blame] | 2497 | return 0; |
| 2498 | } |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2499 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2500 | static int radeon_emit_packets(drm_radeon_private_t * dev_priv, |
| 2501 | drm_file_t * filp_priv, |
| 2502 | drm_radeon_cmd_header_t header, |
| 2503 | drm_radeon_cmd_buffer_t * cmdbuf) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2504 | { |
| 2505 | int id = (int)header.packet.packet_id; |
Brian Paul | ff25e70 | 2002-10-28 19:05:40 +0000 | [diff] [blame] | 2506 | int sz, reg; |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2507 | int *data = (int *)cmdbuf->buf; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2508 | RING_LOCALS; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2509 | |
Brian Paul | ff25e70 | 2002-10-28 19:05:40 +0000 | [diff] [blame] | 2510 | if (id >= RADEON_MAX_STATE_PACKETS) |
| 2511 | return DRM_ERR(EINVAL); |
| 2512 | |
| 2513 | sz = packet[id].len; |
| 2514 | reg = packet[id].start; |
| 2515 | |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2516 | if (sz * sizeof(int) > cmdbuf->bufsz) { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2517 | DRM_ERROR("Packet size provided larger than data provided\n"); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2518 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2519 | } |
| 2520 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2521 | if (radeon_check_and_fixup_packets(dev_priv, filp_priv, id, data)) { |
| 2522 | DRM_ERROR("Packet verification failed\n"); |
| 2523 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2524 | } |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2525 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2526 | BEGIN_RING(sz + 1); |
| 2527 | OUT_RING(CP_PACKET0(reg, (sz - 1))); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2528 | OUT_RING_TABLE(data, sz); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2529 | ADVANCE_RING(); |
| 2530 | |
| 2531 | cmdbuf->buf += sz * sizeof(int); |
| 2532 | cmdbuf->bufsz -= sz * sizeof(int); |
| 2533 | return 0; |
| 2534 | } |
| 2535 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2536 | static __inline__ int radeon_emit_scalars(drm_radeon_private_t * dev_priv, |
| 2537 | drm_radeon_cmd_header_t header, |
| 2538 | drm_radeon_cmd_buffer_t * cmdbuf) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2539 | { |
| 2540 | int sz = header.scalars.count; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2541 | int start = header.scalars.offset; |
| 2542 | int stride = header.scalars.stride; |
| 2543 | RING_LOCALS; |
| 2544 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2545 | BEGIN_RING(3 + sz); |
| 2546 | OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); |
| 2547 | OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); |
| 2548 | OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2549 | OUT_RING_TABLE(cmdbuf->buf, sz); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2550 | ADVANCE_RING(); |
| 2551 | cmdbuf->buf += sz * sizeof(int); |
| 2552 | cmdbuf->bufsz -= sz * sizeof(int); |
| 2553 | return 0; |
| 2554 | } |
| 2555 | |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2556 | /* God this is ugly |
| 2557 | */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2558 | static __inline__ int radeon_emit_scalars2(drm_radeon_private_t * dev_priv, |
| 2559 | drm_radeon_cmd_header_t header, |
| 2560 | drm_radeon_cmd_buffer_t * cmdbuf) |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2561 | { |
| 2562 | int sz = header.scalars.count; |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2563 | int start = ((unsigned int)header.scalars.offset) + 0x100; |
| 2564 | int stride = header.scalars.stride; |
| 2565 | RING_LOCALS; |
| 2566 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2567 | BEGIN_RING(3 + sz); |
| 2568 | OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); |
| 2569 | OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); |
| 2570 | OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2571 | OUT_RING_TABLE(cmdbuf->buf, sz); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2572 | ADVANCE_RING(); |
| 2573 | cmdbuf->buf += sz * sizeof(int); |
| 2574 | cmdbuf->bufsz -= sz * sizeof(int); |
| 2575 | return 0; |
| 2576 | } |
| 2577 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2578 | static __inline__ int radeon_emit_vectors(drm_radeon_private_t * dev_priv, |
| 2579 | drm_radeon_cmd_header_t header, |
| 2580 | drm_radeon_cmd_buffer_t * cmdbuf) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2581 | { |
| 2582 | int sz = header.vectors.count; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2583 | int start = header.vectors.offset; |
| 2584 | int stride = header.vectors.stride; |
| 2585 | RING_LOCALS; |
| 2586 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2587 | BEGIN_RING(3 + sz); |
| 2588 | OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); |
| 2589 | OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); |
| 2590 | OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2591 | OUT_RING_TABLE(cmdbuf->buf, sz); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2592 | ADVANCE_RING(); |
| 2593 | |
| 2594 | cmdbuf->buf += sz * sizeof(int); |
| 2595 | cmdbuf->bufsz -= sz * sizeof(int); |
| 2596 | return 0; |
| 2597 | } |
| 2598 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2599 | static int radeon_emit_packet3(drm_device_t * dev, |
| 2600 | drm_file_t * filp_priv, |
| 2601 | drm_radeon_cmd_buffer_t * cmdbuf) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2602 | { |
| 2603 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2604 | unsigned int cmdsz; |
Dave Airlie | 02df04d | 2004-07-25 08:47:38 +0000 | [diff] [blame] | 2605 | int ret; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2606 | RING_LOCALS; |
| 2607 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2608 | DRM_DEBUG("\n"); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2609 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2610 | if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv, |
| 2611 | cmdbuf, &cmdsz))) { |
| 2612 | DRM_ERROR("Packet verification failed\n"); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2613 | return ret; |
| 2614 | } |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2615 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2616 | BEGIN_RING(cmdsz); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2617 | OUT_RING_TABLE(cmdbuf->buf, cmdsz); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2618 | ADVANCE_RING(); |
| 2619 | |
| 2620 | cmdbuf->buf += cmdsz * 4; |
| 2621 | cmdbuf->bufsz -= cmdsz * 4; |
| 2622 | return 0; |
| 2623 | } |
| 2624 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2625 | static int radeon_emit_packet3_cliprect(drm_device_t * dev, |
| 2626 | drm_file_t * filp_priv, |
| 2627 | drm_radeon_cmd_buffer_t * cmdbuf, |
| 2628 | int orig_nbox) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2629 | { |
| 2630 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 2631 | drm_clip_rect_t box; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2632 | unsigned int cmdsz; |
Dave Airlie | 02df04d | 2004-07-25 08:47:38 +0000 | [diff] [blame] | 2633 | int ret; |
| 2634 | drm_clip_rect_t __user *boxes = cmdbuf->boxes; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2635 | int i = 0; |
| 2636 | RING_LOCALS; |
| 2637 | |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2638 | DRM_DEBUG("\n"); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2639 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2640 | if ((ret = radeon_check_and_fixup_packet3(dev_priv, filp_priv, |
| 2641 | cmdbuf, &cmdsz))) { |
| 2642 | DRM_ERROR("Packet verification failed\n"); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2643 | return ret; |
| 2644 | } |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2645 | |
Keith Whitwell | 33d5713 | 2002-08-12 07:26:00 +0000 | [diff] [blame] | 2646 | if (!orig_nbox) |
| 2647 | goto out; |
| 2648 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2649 | do { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2650 | if (i < cmdbuf->nbox) { |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2651 | if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box))) |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2652 | return DRM_ERR(EFAULT); |
Keith Whitwell | f1c8fe9 | 2002-09-23 17:26:43 +0000 | [diff] [blame] | 2653 | /* FIXME The second and subsequent times round |
| 2654 | * this loop, send a WAIT_UNTIL_3D_IDLE before |
| 2655 | * calling emit_clip_rect(). This fixes a |
| 2656 | * lockup on fast machines when sending |
| 2657 | * several cliprects with a cmdbuf, as when |
| 2658 | * waving a 2D window over a 3D |
| 2659 | * window. Something in the commands from user |
| 2660 | * space seems to hang the card when they're |
| 2661 | * sent several times in a row. That would be |
| 2662 | * the correct place to fix it but this works |
| 2663 | * around it until I can figure that out - Tim |
| 2664 | * Smith */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2665 | if (i) { |
| 2666 | BEGIN_RING(2); |
Tim Smith | 8fa8db1 | 2002-07-17 08:30:36 +0000 | [diff] [blame] | 2667 | RADEON_WAIT_UNTIL_3D_IDLE(); |
| 2668 | ADVANCE_RING(); |
| 2669 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2670 | radeon_emit_clip_rect(dev_priv, &box); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2671 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2672 | |
| 2673 | BEGIN_RING(cmdsz); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2674 | OUT_RING_TABLE(cmdbuf->buf, cmdsz); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2675 | ADVANCE_RING(); |
| 2676 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2677 | } while (++i < cmdbuf->nbox); |
| 2678 | if (cmdbuf->nbox == 1) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2679 | cmdbuf->nbox = 0; |
| 2680 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2681 | out: |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2682 | cmdbuf->buf += cmdsz * 4; |
| 2683 | cmdbuf->bufsz -= cmdsz * 4; |
| 2684 | return 0; |
| 2685 | } |
| 2686 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2687 | static int radeon_emit_wait(drm_device_t * dev, int flags) |
Keith Whitwell | f1c8fe9 | 2002-09-23 17:26:43 +0000 | [diff] [blame] | 2688 | { |
| 2689 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 2690 | RING_LOCALS; |
| 2691 | |
| 2692 | DRM_DEBUG("%s: %x\n", __FUNCTION__, flags); |
| 2693 | switch (flags) { |
| 2694 | case RADEON_WAIT_2D: |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2695 | BEGIN_RING(2); |
| 2696 | RADEON_WAIT_UNTIL_2D_IDLE(); |
Keith Whitwell | f1c8fe9 | 2002-09-23 17:26:43 +0000 | [diff] [blame] | 2697 | ADVANCE_RING(); |
| 2698 | break; |
| 2699 | case RADEON_WAIT_3D: |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2700 | BEGIN_RING(2); |
| 2701 | RADEON_WAIT_UNTIL_3D_IDLE(); |
Keith Whitwell | f1c8fe9 | 2002-09-23 17:26:43 +0000 | [diff] [blame] | 2702 | ADVANCE_RING(); |
| 2703 | break; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2704 | case RADEON_WAIT_2D | RADEON_WAIT_3D: |
| 2705 | BEGIN_RING(2); |
| 2706 | RADEON_WAIT_UNTIL_IDLE(); |
Keith Whitwell | f1c8fe9 | 2002-09-23 17:26:43 +0000 | [diff] [blame] | 2707 | ADVANCE_RING(); |
| 2708 | break; |
| 2709 | default: |
| 2710 | return DRM_ERR(EINVAL); |
| 2711 | } |
| 2712 | |
| 2713 | return 0; |
| 2714 | } |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2715 | |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 2716 | static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2717 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2718 | DRM_DEVICE; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2719 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2720 | drm_file_t *filp_priv; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2721 | drm_device_dma_t *dma = dev->dma; |
Dave Airlie | 8efddd0 | 2004-07-15 13:03:55 +0000 | [diff] [blame] | 2722 | drm_buf_t *buf = NULL; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2723 | int idx; |
| 2724 | drm_radeon_cmd_buffer_t cmdbuf; |
| 2725 | drm_radeon_cmd_header_t header; |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2726 | int orig_nbox, orig_bufsz; |
Eric Anholt | 2f7cd38 | 2005-02-14 03:22:58 +0000 | [diff] [blame] | 2727 | char *kbuf = NULL; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2728 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2729 | LOCK_TEST_WITH_RETURN(dev, filp); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2730 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2731 | if (!dev_priv) { |
| 2732 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2733 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2734 | } |
| 2735 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2736 | DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2737 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2738 | DRM_COPY_FROM_USER_IOCTL(cmdbuf, |
| 2739 | (drm_radeon_cmd_buffer_t __user *) data, |
| 2740 | sizeof(cmdbuf)); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2741 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2742 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
| 2743 | VB_AGE_TEST_WITH_RETURN(dev_priv); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2744 | |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2745 | if (cmdbuf.bufsz > 64 * 1024 || cmdbuf.bufsz < 0) { |
| 2746 | return DRM_ERR(EINVAL); |
| 2747 | } |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2748 | |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2749 | /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid |
| 2750 | * races between checking values and using those values in other code, |
| 2751 | * and simply to avoid a lot of function calls to copy in data. |
| 2752 | */ |
| 2753 | orig_bufsz = cmdbuf.bufsz; |
| 2754 | if (orig_bufsz != 0) { |
| 2755 | kbuf = drm_alloc(cmdbuf.bufsz, DRM_MEM_DRIVER); |
| 2756 | if (kbuf == NULL) |
| 2757 | return DRM_ERR(ENOMEM); |
Eric Anholt | 2f7cd38 | 2005-02-14 03:22:58 +0000 | [diff] [blame] | 2758 | if (DRM_COPY_FROM_USER(kbuf, cmdbuf.buf, cmdbuf.bufsz)) { |
| 2759 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2760 | return DRM_ERR(EFAULT); |
Eric Anholt | 2f7cd38 | 2005-02-14 03:22:58 +0000 | [diff] [blame] | 2761 | } |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2762 | cmdbuf.buf = kbuf; |
| 2763 | } |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2764 | |
Keith Whitwell | 33d5713 | 2002-08-12 07:26:00 +0000 | [diff] [blame] | 2765 | orig_nbox = cmdbuf.nbox; |
Eric Anholt | ab59dd2 | 2005-07-20 21:17:47 +0000 | [diff] [blame] | 2766 | |
| 2767 | if(dev_priv->microcode_version == UCODE_R300) { |
| 2768 | int temp; |
| 2769 | temp=r300_do_cp_cmdbuf(dev, filp, filp_priv, &cmdbuf); |
| 2770 | |
| 2771 | if (orig_bufsz != 0) |
| 2772 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); |
| 2773 | |
| 2774 | return temp; |
| 2775 | } |
| 2776 | |
| 2777 | /* microcode_version != r300 */ |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2778 | while (cmdbuf.bufsz >= sizeof(header)) { |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2779 | header.i = *(int *)cmdbuf.buf; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2780 | cmdbuf.buf += sizeof(header); |
| 2781 | cmdbuf.bufsz -= sizeof(header); |
| 2782 | |
| 2783 | switch (header.header.cmd_type) { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2784 | case RADEON_CMD_PACKET: |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2785 | DRM_DEBUG("RADEON_CMD_PACKET\n"); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2786 | if (radeon_emit_packets |
| 2787 | (dev_priv, filp_priv, header, &cmdbuf)) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2788 | DRM_ERROR("radeon_emit_packets failed\n"); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2789 | goto err; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2790 | } |
| 2791 | break; |
| 2792 | |
| 2793 | case RADEON_CMD_SCALARS: |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2794 | DRM_DEBUG("RADEON_CMD_SCALARS\n"); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2795 | if (radeon_emit_scalars(dev_priv, header, &cmdbuf)) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2796 | DRM_ERROR("radeon_emit_scalars failed\n"); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2797 | goto err; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2798 | } |
| 2799 | break; |
| 2800 | |
| 2801 | case RADEON_CMD_VECTORS: |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2802 | DRM_DEBUG("RADEON_CMD_VECTORS\n"); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2803 | if (radeon_emit_vectors(dev_priv, header, &cmdbuf)) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2804 | DRM_ERROR("radeon_emit_vectors failed\n"); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2805 | goto err; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2806 | } |
| 2807 | break; |
| 2808 | |
| 2809 | case RADEON_CMD_DMA_DISCARD: |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2810 | DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2811 | idx = header.dma.buf_idx; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2812 | if (idx < 0 || idx >= dma->buf_count) { |
| 2813 | DRM_ERROR("buffer index %d (of %d max)\n", |
| 2814 | idx, dma->buf_count - 1); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2815 | goto err; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2816 | } |
| 2817 | |
| 2818 | buf = dma->buflist[idx]; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2819 | if (buf->filp != filp || buf->pending) { |
| 2820 | DRM_ERROR("bad buffer %p %p %d\n", |
| 2821 | buf->filp, filp, buf->pending); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2822 | goto err; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2823 | } |
| 2824 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2825 | radeon_cp_discard_buffer(dev, buf); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2826 | break; |
| 2827 | |
| 2828 | case RADEON_CMD_PACKET3: |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2829 | DRM_DEBUG("RADEON_CMD_PACKET3\n"); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2830 | if (radeon_emit_packet3(dev, filp_priv, &cmdbuf)) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2831 | DRM_ERROR("radeon_emit_packet3 failed\n"); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2832 | goto err; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2833 | } |
| 2834 | break; |
| 2835 | |
| 2836 | case RADEON_CMD_PACKET3_CLIP: |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2837 | DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2838 | if (radeon_emit_packet3_cliprect |
| 2839 | (dev, filp_priv, &cmdbuf, orig_nbox)) { |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2840 | DRM_ERROR("radeon_emit_packet3_clip failed\n"); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2841 | goto err; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2842 | } |
| 2843 | break; |
| 2844 | |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2845 | case RADEON_CMD_SCALARS2: |
| 2846 | DRM_DEBUG("RADEON_CMD_SCALARS2\n"); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2847 | if (radeon_emit_scalars2(dev_priv, header, &cmdbuf)) { |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2848 | DRM_ERROR("radeon_emit_scalars2 failed\n"); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2849 | goto err; |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2850 | } |
| 2851 | break; |
Keith Whitwell | f1c8fe9 | 2002-09-23 17:26:43 +0000 | [diff] [blame] | 2852 | |
| 2853 | case RADEON_CMD_WAIT: |
| 2854 | DRM_DEBUG("RADEON_CMD_WAIT\n"); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2855 | if (radeon_emit_wait(dev, header.wait.flags)) { |
Keith Whitwell | f1c8fe9 | 2002-09-23 17:26:43 +0000 | [diff] [blame] | 2856 | DRM_ERROR("radeon_emit_wait failed\n"); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2857 | goto err; |
Keith Whitwell | f1c8fe9 | 2002-09-23 17:26:43 +0000 | [diff] [blame] | 2858 | } |
| 2859 | break; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2860 | default: |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2861 | DRM_ERROR("bad cmd_type %d at %p\n", |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2862 | header.header.cmd_type, |
| 2863 | cmdbuf.buf - sizeof(header)); |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2864 | goto err; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2865 | } |
| 2866 | } |
| 2867 | |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2868 | if (orig_bufsz != 0) |
| 2869 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2870 | DRM_DEBUG("DONE\n"); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2871 | COMMIT_RING(); |
Eric Anholt | ab59dd2 | 2005-07-20 21:17:47 +0000 | [diff] [blame] | 2872 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2873 | return 0; |
Eric Anholt | 81459d6 | 2005-02-08 04:17:14 +0000 | [diff] [blame] | 2874 | |
| 2875 | err: |
| 2876 | if (orig_bufsz != 0) |
| 2877 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); |
| 2878 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2879 | } |
| 2880 | |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 2881 | static int radeon_cp_getparam(DRM_IOCTL_ARGS) |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2882 | { |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2883 | DRM_DEVICE; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2884 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 2885 | drm_radeon_getparam_t param; |
| 2886 | int value; |
| 2887 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2888 | if (!dev_priv) { |
| 2889 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2890 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2891 | } |
| 2892 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2893 | DRM_COPY_FROM_USER_IOCTL(param, (drm_radeon_getparam_t __user *) data, |
| 2894 | sizeof(param)); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2895 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2896 | DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2897 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2898 | switch (param.param) { |
Michel Daenzer | 062751a | 2003-08-26 15:44:01 +0000 | [diff] [blame] | 2899 | case RADEON_PARAM_GART_BUFFER_OFFSET: |
| 2900 | value = dev_priv->gart_buffers_offset; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2901 | break; |
Michel Daenzer | fd86ac9 | 2002-07-11 20:31:12 +0000 | [diff] [blame] | 2902 | case RADEON_PARAM_LAST_FRAME: |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2903 | dev_priv->stats.last_frame_reads++; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2904 | value = GET_SCRATCH(0); |
Michel Daenzer | fd86ac9 | 2002-07-11 20:31:12 +0000 | [diff] [blame] | 2905 | break; |
| 2906 | case RADEON_PARAM_LAST_DISPATCH: |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2907 | value = GET_SCRATCH(1); |
Michel Daenzer | fd86ac9 | 2002-07-11 20:31:12 +0000 | [diff] [blame] | 2908 | break; |
| 2909 | case RADEON_PARAM_LAST_CLEAR: |
Keith Whitwell | 48cc350 | 2002-08-26 22:16:18 +0000 | [diff] [blame] | 2910 | dev_priv->stats.last_clear_reads++; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2911 | value = GET_SCRATCH(2); |
Michel Daenzer | fd86ac9 | 2002-07-11 20:31:12 +0000 | [diff] [blame] | 2912 | break; |
Michel Daenzer | f40674e | 2002-09-25 19:48:51 +0000 | [diff] [blame] | 2913 | case RADEON_PARAM_IRQ_NR: |
| 2914 | value = dev->irq; |
Keith Whitwell | f1c8fe9 | 2002-09-23 17:26:43 +0000 | [diff] [blame] | 2915 | break; |
Michel Daenzer | 062751a | 2003-08-26 15:44:01 +0000 | [diff] [blame] | 2916 | case RADEON_PARAM_GART_BASE: |
| 2917 | value = dev_priv->gart_vm_start; |
Keith Whitwell | f1c8fe9 | 2002-09-23 17:26:43 +0000 | [diff] [blame] | 2918 | break; |
Keith Whitwell | 13211ad | 2003-04-22 09:49:14 +0000 | [diff] [blame] | 2919 | case RADEON_PARAM_REGISTER_HANDLE: |
Jon Smirl | bb9502a | 2005-08-04 13:59:48 +0000 | [diff] [blame] | 2920 | value = dev_priv->mmio->offset; |
Keith Whitwell | 13211ad | 2003-04-22 09:49:14 +0000 | [diff] [blame] | 2921 | break; |
| 2922 | case RADEON_PARAM_STATUS_HANDLE: |
| 2923 | value = dev_priv->ring_rptr_offset; |
| 2924 | break; |
Dave Airlie | bc14280 | 2004-04-08 12:05:25 +0000 | [diff] [blame] | 2925 | #if BITS_PER_LONG == 32 |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2926 | /* |
| 2927 | * This ioctl() doesn't work on 64-bit platforms because hw_lock is a |
| 2928 | * pointer which can't fit into an int-sized variable. According to |
| 2929 | * Michel Dänzer, the ioctl() is only used on embedded platforms, so |
| 2930 | * not supporting it shouldn't be a problem. If the same functionality |
| 2931 | * is needed on 64-bit platforms, a new ioctl() would have to be added, |
| 2932 | * so backwards-compatibility for the embedded platforms can be |
| 2933 | * maintained. --davidm 4-Feb-2004. |
| 2934 | */ |
Keith Whitwell | 13211ad | 2003-04-22 09:49:14 +0000 | [diff] [blame] | 2935 | case RADEON_PARAM_SAREA_HANDLE: |
| 2936 | /* The lock is the first dword in the sarea. */ |
Dave Airlie | 4cfd0d5 | 2004-07-05 11:44:30 +0000 | [diff] [blame] | 2937 | value = (long)dev->lock.hw_lock; |
| 2938 | break; |
Dave Airlie | bc14280 | 2004-04-08 12:05:25 +0000 | [diff] [blame] | 2939 | #endif |
Michel Daenzer | 062751a | 2003-08-26 15:44:01 +0000 | [diff] [blame] | 2940 | case RADEON_PARAM_GART_TEX_HANDLE: |
| 2941 | value = dev_priv->gart_textures_offset; |
Keith Whitwell | 13211ad | 2003-04-22 09:49:14 +0000 | [diff] [blame] | 2942 | break; |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2943 | default: |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2944 | return DRM_ERR(EINVAL); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2945 | } |
| 2946 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2947 | if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { |
| 2948 | DRM_ERROR("copy_to_user\n"); |
Alan Hourihane | 74ef13f | 2002-07-05 08:31:11 +0000 | [diff] [blame] | 2949 | return DRM_ERR(EFAULT); |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2950 | } |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2951 | |
Keith Whitwell | 2dcada3 | 2002-06-12 15:50:28 +0000 | [diff] [blame] | 2952 | return 0; |
| 2953 | } |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2954 | |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 2955 | static int radeon_cp_setparam(DRM_IOCTL_ARGS) |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2956 | { |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2957 | DRM_DEVICE; |
| 2958 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 2959 | drm_file_t *filp_priv; |
| 2960 | drm_radeon_setparam_t sp; |
Dave Airlie | d4dbf45 | 2004-08-24 11:15:53 +0000 | [diff] [blame] | 2961 | struct drm_radeon_driver_file_fields *radeon_priv; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2962 | |
| 2963 | if (!dev_priv) { |
| 2964 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); |
| 2965 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2966 | } |
| 2967 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2968 | DRM_GET_PRIV_WITH_RETURN(filp_priv, filp); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2969 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2970 | DRM_COPY_FROM_USER_IOCTL(sp, (drm_radeon_setparam_t __user *) data, |
| 2971 | sizeof(sp)); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2972 | |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2973 | switch (sp.param) { |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2974 | case RADEON_SETPARAM_FB_LOCATION: |
Dave Airlie | d4dbf45 | 2004-08-24 11:15:53 +0000 | [diff] [blame] | 2975 | radeon_priv = filp_priv->driver_priv; |
| 2976 | radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2977 | break; |
Roland Scheidegger | 43c3223 | 2005-01-26 17:48:59 +0000 | [diff] [blame] | 2978 | case RADEON_SETPARAM_SWITCH_TILING: |
| 2979 | if (sp.value == 0) { |
| 2980 | DRM_DEBUG( "color tiling disabled\n" ); |
| 2981 | dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO; |
| 2982 | dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO; |
| 2983 | dev_priv->sarea_priv->tiling_enabled = 0; |
| 2984 | } |
| 2985 | else if (sp.value == 1) { |
| 2986 | DRM_DEBUG( "color tiling enabled\n" ); |
| 2987 | dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO; |
| 2988 | dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO; |
| 2989 | dev_priv->sarea_priv->tiling_enabled = 1; |
| 2990 | } |
| 2991 | break; |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2992 | default: |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 2993 | DRM_DEBUG("Invalid parameter %d\n", sp.param); |
| 2994 | return DRM_ERR(EINVAL); |
Michel Daenzer | 2655ccd | 2003-11-04 00:46:05 +0000 | [diff] [blame] | 2995 | } |
| 2996 | |
| 2997 | return 0; |
| 2998 | } |
Dave Airlie | 5c9ed83 | 2004-08-17 13:10:05 +0000 | [diff] [blame] | 2999 | |
| 3000 | /* When a client dies: |
| 3001 | * - Check for and clean up flipped page state |
| 3002 | * - Free any alloced GART memory. |
Roland Scheidegger | 43c3223 | 2005-01-26 17:48:59 +0000 | [diff] [blame] | 3003 | * - Free any alloced radeon surfaces. |
Dave Airlie | 5c9ed83 | 2004-08-17 13:10:05 +0000 | [diff] [blame] | 3004 | * |
| 3005 | * DRM infrastructure takes care of reclaiming dma buffers. |
| 3006 | */ |
Eric Anholt | c789ea1 | 2005-08-05 03:50:23 +0000 | [diff] [blame^] | 3007 | void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp) |
Dave Airlie | 5c9ed83 | 2004-08-17 13:10:05 +0000 | [diff] [blame] | 3008 | { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 3009 | if (dev->dev_private) { |
| 3010 | drm_radeon_private_t *dev_priv = dev->dev_private; |
| 3011 | if (dev_priv->page_flipping) { |
| 3012 | radeon_do_cleanup_pageflip(dev); |
| 3013 | } |
| 3014 | radeon_mem_release(filp, dev_priv->gart_heap); |
| 3015 | radeon_mem_release(filp, dev_priv->fb_heap); |
Roland Scheidegger | 43c3223 | 2005-01-26 17:48:59 +0000 | [diff] [blame] | 3016 | radeon_surfaces_release(filp, dev_priv); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 3017 | } |
Dave Airlie | 5c9ed83 | 2004-08-17 13:10:05 +0000 | [diff] [blame] | 3018 | } |
| 3019 | |
Eric Anholt | c789ea1 | 2005-08-05 03:50:23 +0000 | [diff] [blame^] | 3020 | void radeon_driver_lastclose(drm_device_t * dev) |
Dave Airlie | 5c9ed83 | 2004-08-17 13:10:05 +0000 | [diff] [blame] | 3021 | { |
| 3022 | radeon_do_release(dev); |
| 3023 | } |
| 3024 | |
Eric Anholt | c789ea1 | 2005-08-05 03:50:23 +0000 | [diff] [blame^] | 3025 | int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv) |
Dave Airlie | 5c9ed83 | 2004-08-17 13:10:05 +0000 | [diff] [blame] | 3026 | { |
| 3027 | drm_radeon_private_t *dev_priv = dev->dev_private; |
Dave Airlie | d4dbf45 | 2004-08-24 11:15:53 +0000 | [diff] [blame] | 3028 | struct drm_radeon_driver_file_fields *radeon_priv; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 3029 | |
Dave Airlie | 77045dc | 2005-01-27 09:13:42 +0000 | [diff] [blame] | 3030 | DRM_DEBUG("\n"); |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 3031 | radeon_priv = |
| 3032 | (struct drm_radeon_driver_file_fields *) |
| 3033 | drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES); |
| 3034 | |
Dave Airlie | d4dbf45 | 2004-08-24 11:15:53 +0000 | [diff] [blame] | 3035 | if (!radeon_priv) |
| 3036 | return -ENOMEM; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 3037 | |
Dave Airlie | d4dbf45 | 2004-08-24 11:15:53 +0000 | [diff] [blame] | 3038 | filp_priv->driver_priv = radeon_priv; |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 3039 | |
| 3040 | if (dev_priv) |
Dave Airlie | d4dbf45 | 2004-08-24 11:15:53 +0000 | [diff] [blame] | 3041 | radeon_priv->radeon_fb_delta = dev_priv->fb_location; |
Dave Airlie | 5c9ed83 | 2004-08-17 13:10:05 +0000 | [diff] [blame] | 3042 | else |
Dave Airlie | d4dbf45 | 2004-08-24 11:15:53 +0000 | [diff] [blame] | 3043 | radeon_priv->radeon_fb_delta = 0; |
| 3044 | return 0; |
| 3045 | } |
| 3046 | |
Eric Anholt | c789ea1 | 2005-08-05 03:50:23 +0000 | [diff] [blame^] | 3047 | void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp_priv) |
Dave Airlie | d4dbf45 | 2004-08-24 11:15:53 +0000 | [diff] [blame] | 3048 | { |
Jon Smirl | 9f9a8f1 | 2004-09-30 21:12:10 +0000 | [diff] [blame] | 3049 | struct drm_radeon_driver_file_fields *radeon_priv = |
| 3050 | filp_priv->driver_priv; |
| 3051 | |
Jon Smirl | fa6b1d1 | 2004-09-27 19:51:38 +0000 | [diff] [blame] | 3052 | drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); |
Dave Airlie | 5c9ed83 | 2004-08-17 13:10:05 +0000 | [diff] [blame] | 3053 | } |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 3054 | |
| 3055 | drm_ioctl_desc_t radeon_ioctls[] = { |
Jon Smirl | ea2c7a8 | 2005-08-04 13:15:27 +0000 | [diff] [blame] | 3056 | [DRM_IOCTL_NR(DRM_RADEON_CP_INIT)] = {radeon_cp_init, 1, 1, 1}, |
| 3057 | [DRM_IOCTL_NR(DRM_RADEON_CP_START)] = {radeon_cp_start, 1, 1, 1}, |
| 3058 | [DRM_IOCTL_NR(DRM_RADEON_CP_STOP)] = {radeon_cp_stop, 1, 1, 1}, |
| 3059 | [DRM_IOCTL_NR(DRM_RADEON_CP_RESET)] = {radeon_cp_reset, 1, 1, 1}, |
| 3060 | [DRM_IOCTL_NR(DRM_RADEON_CP_IDLE)] = {radeon_cp_idle, 1, 0, 0}, |
| 3061 | [DRM_IOCTL_NR(DRM_RADEON_CP_RESUME)] = {radeon_cp_resume, 1, 0, 0}, |
| 3062 | [DRM_IOCTL_NR(DRM_RADEON_RESET)] = {radeon_engine_reset, 1, 0, 0}, |
| 3063 | [DRM_IOCTL_NR(DRM_RADEON_FULLSCREEN)] = {radeon_fullscreen, 1, 0, 0}, |
| 3064 | [DRM_IOCTL_NR(DRM_RADEON_SWAP)] = {radeon_cp_swap, 1, 0, 0}, |
| 3065 | [DRM_IOCTL_NR(DRM_RADEON_CLEAR)] = {radeon_cp_clear, 1, 0, 0}, |
| 3066 | [DRM_IOCTL_NR(DRM_RADEON_VERTEX)] = {radeon_cp_vertex, 1, 0, 0}, |
| 3067 | [DRM_IOCTL_NR(DRM_RADEON_INDICES)] = {radeon_cp_indices, 1, 0, 0}, |
| 3068 | [DRM_IOCTL_NR(DRM_RADEON_TEXTURE)] = {radeon_cp_texture, 1, 0, 0}, |
| 3069 | [DRM_IOCTL_NR(DRM_RADEON_STIPPLE)] = {radeon_cp_stipple, 1, 0, 0}, |
| 3070 | [DRM_IOCTL_NR(DRM_RADEON_INDIRECT)] = {radeon_cp_indirect, 1, 1, 1}, |
| 3071 | [DRM_IOCTL_NR(DRM_RADEON_VERTEX2)] = {radeon_cp_vertex2, 1, 0, 0}, |
| 3072 | [DRM_IOCTL_NR(DRM_RADEON_CMDBUF)] = {radeon_cp_cmdbuf, 1, 0, 0}, |
| 3073 | [DRM_IOCTL_NR(DRM_RADEON_GETPARAM)] = {radeon_cp_getparam, 1, 0, 0}, |
| 3074 | [DRM_IOCTL_NR(DRM_RADEON_FLIP)] = {radeon_cp_flip, 1, 0, 0}, |
| 3075 | [DRM_IOCTL_NR(DRM_RADEON_ALLOC)] = {radeon_mem_alloc, 1, 0, 0}, |
| 3076 | [DRM_IOCTL_NR(DRM_RADEON_FREE)] = {radeon_mem_free, 1, 0, 0}, |
| 3077 | [DRM_IOCTL_NR(DRM_RADEON_INIT_HEAP)] = {radeon_mem_init_heap, 1, 1, 1}, |
| 3078 | [DRM_IOCTL_NR(DRM_RADEON_IRQ_EMIT)] = {radeon_irq_emit, 1, 0, 0}, |
| 3079 | [DRM_IOCTL_NR(DRM_RADEON_IRQ_WAIT)] = {radeon_irq_wait, 1, 0, 0}, |
| 3080 | [DRM_IOCTL_NR(DRM_RADEON_SETPARAM)] = {radeon_cp_setparam, 1, 0, 0}, |
| 3081 | [DRM_IOCTL_NR(DRM_RADEON_SURF_ALLOC)] = {radeon_surface_alloc, 1, 0, 0}, |
| 3082 | [DRM_IOCTL_NR(DRM_RADEON_SURF_FREE)] = {radeon_surface_free, 1, 0, 0} |
Dave Airlie | 0d6b7fc | 2005-02-01 11:08:31 +0000 | [diff] [blame] | 3083 | }; |
| 3084 | |
| 3085 | int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); |