David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1 | //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file implements a simple register coalescing pass that attempts to |
| 11 | // aggressively coalesce every register copy that it can. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
Evan Cheng | 3b1f55e | 2007-07-31 22:37:44 +0000 | [diff] [blame] | 15 | #define DEBUG_TYPE "regcoalescing" |
Evan Cheng | a461c4d | 2007-11-05 17:41:38 +0000 | [diff] [blame] | 16 | #include "SimpleRegisterCoalescing.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 17 | #include "VirtRegMap.h" |
Evan Cheng | a461c4d | 2007-11-05 17:41:38 +0000 | [diff] [blame] | 18 | #include "llvm/CodeGen/LiveIntervalAnalysis.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 19 | #include "llvm/Value.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/LiveVariables.h" |
| 21 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 22 | #include "llvm/CodeGen/MachineInstr.h" |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/MachineLoopInfo.h" |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 24 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/Passes.h" |
David Greene | 2c17c4d | 2007-09-06 16:18:45 +0000 | [diff] [blame] | 26 | #include "llvm/CodeGen/RegisterCoalescer.h" |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 27 | #include "llvm/Target/TargetInstrInfo.h" |
| 28 | #include "llvm/Target/TargetMachine.h" |
| 29 | #include "llvm/Support/CommandLine.h" |
| 30 | #include "llvm/Support/Debug.h" |
| 31 | #include "llvm/ADT/SmallSet.h" |
| 32 | #include "llvm/ADT/Statistic.h" |
| 33 | #include "llvm/ADT/STLExtras.h" |
| 34 | #include <algorithm> |
| 35 | #include <cmath> |
| 36 | using namespace llvm; |
| 37 | |
| 38 | STATISTIC(numJoins , "Number of interval joins performed"); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 39 | STATISTIC(numCommutes , "Number of instruction commuting performed"); |
| 40 | STATISTIC(numExtends , "Number of copies extended"); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 41 | STATISTIC(numPeep , "Number of identity moves eliminated after coalescing"); |
| 42 | STATISTIC(numAborts , "Number of times interval joining aborted"); |
| 43 | |
| 44 | char SimpleRegisterCoalescing::ID = 0; |
| 45 | namespace { |
| 46 | static cl::opt<bool> |
| 47 | EnableJoining("join-liveintervals", |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 48 | cl::desc("Coalesce copies (default=true)"), |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 49 | cl::init(true)); |
| 50 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 51 | static cl::opt<bool> |
| 52 | NewHeuristic("new-coalescer-heuristic", |
| 53 | cl::desc("Use new coalescer heuristic"), |
| 54 | cl::init(false)); |
| 55 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 56 | RegisterPass<SimpleRegisterCoalescing> |
Chris Lattner | e76fad2 | 2007-08-05 18:45:33 +0000 | [diff] [blame] | 57 | X("simple-register-coalescing", "Simple Register Coalescing"); |
David Greene | 2c17c4d | 2007-09-06 16:18:45 +0000 | [diff] [blame] | 58 | |
| 59 | // Declare that we implement the RegisterCoalescer interface |
| 60 | RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 61 | } |
| 62 | |
| 63 | const PassInfo *llvm::SimpleRegisterCoalescingID = X.getPassInfo(); |
| 64 | |
| 65 | void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 66 | AU.addPreserved<LiveIntervals>(); |
Bill Wendling | 67d65bb | 2008-01-04 20:54:55 +0000 | [diff] [blame] | 67 | AU.addPreserved<MachineLoopInfo>(); |
| 68 | AU.addPreservedID(MachineDominatorsID); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 69 | AU.addPreservedID(PHIEliminationID); |
| 70 | AU.addPreservedID(TwoAddressInstructionPassID); |
| 71 | AU.addRequired<LiveVariables>(); |
| 72 | AU.addRequired<LiveIntervals>(); |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 73 | AU.addRequired<MachineLoopInfo>(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 74 | MachineFunctionPass::getAnalysisUsage(AU); |
| 75 | } |
| 76 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 77 | /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 78 | /// being the source and IntB being the dest, thus this defines a value number |
| 79 | /// in IntB. If the source value number (in IntA) is defined by a copy from B, |
| 80 | /// see if we can merge these two pieces of B into a single value number, |
| 81 | /// eliminating a copy. For example: |
| 82 | /// |
| 83 | /// A3 = B0 |
| 84 | /// ... |
| 85 | /// B1 = A3 <- this copy |
| 86 | /// |
| 87 | /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1 |
| 88 | /// value number to be replaced with B0 (which simplifies the B liveinterval). |
| 89 | /// |
| 90 | /// This returns true if an interval was modified. |
| 91 | /// |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 92 | bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, |
| 93 | LiveInterval &IntB, |
| 94 | MachineInstr *CopyMI) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 95 | unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI)); |
| 96 | |
| 97 | // BValNo is a value number in B that is defined by a copy from A. 'B3' in |
| 98 | // the example above. |
| 99 | LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 100 | VNInfo *BValNo = BLR->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 101 | |
| 102 | // Get the location that B is defined at. Two options: either this value has |
| 103 | // an unknown definition point or it is defined at CopyIdx. If unknown, we |
| 104 | // can't process it. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 105 | if (!BValNo->copy) return false; |
| 106 | assert(BValNo->def == CopyIdx && "Copy doesn't define the value?"); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 107 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 108 | // AValNo is the value number in A that defines the copy, A3 in the example. |
| 109 | LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1); |
| 110 | VNInfo *AValNo = ALR->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 111 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 112 | // If AValNo is defined as a copy from IntB, we can potentially process this. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 113 | // Get the instruction that defines this value number. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 114 | unsigned SrcReg = li_->getVNInfoSourceReg(AValNo); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 115 | if (!SrcReg) return false; // Not defined by a copy. |
| 116 | |
| 117 | // If the value number is not defined by a copy instruction, ignore it. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 118 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 119 | // If the source register comes from an interval other than IntB, we can't |
| 120 | // handle this. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 121 | if (SrcReg != IntB.reg) return false; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 122 | |
| 123 | // Get the LiveRange in IntB that this value number starts with. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 124 | LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 125 | |
| 126 | // Make sure that the end of the live range is inside the same block as |
| 127 | // CopyMI. |
| 128 | MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1); |
| 129 | if (!ValLREndInst || |
| 130 | ValLREndInst->getParent() != CopyMI->getParent()) return false; |
| 131 | |
| 132 | // Okay, we now know that ValLR ends in the same block that the CopyMI |
| 133 | // live-range starts. If there are no intervening live ranges between them in |
| 134 | // IntB, we can merge them. |
| 135 | if (ValLR+1 != BLR) return false; |
Evan Cheng | dc5294f | 2007-08-14 23:19:28 +0000 | [diff] [blame] | 136 | |
| 137 | // If a live interval is a physical register, conservatively check if any |
| 138 | // of its sub-registers is overlapping the live interval of the virtual |
| 139 | // register. If so, do not coalesce. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 140 | if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) && |
| 141 | *tri_->getSubRegisters(IntB.reg)) { |
| 142 | for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) |
Evan Cheng | dc5294f | 2007-08-14 23:19:28 +0000 | [diff] [blame] | 143 | if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) { |
| 144 | DOUT << "Interfere with sub-register "; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 145 | DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); |
Evan Cheng | dc5294f | 2007-08-14 23:19:28 +0000 | [diff] [blame] | 146 | return false; |
| 147 | } |
| 148 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 149 | |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 150 | DOUT << "\nExtending: "; IntB.print(DOUT, tri_); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 151 | |
Evan Cheng | a8d94f1 | 2007-08-07 23:49:57 +0000 | [diff] [blame] | 152 | unsigned FillerStart = ValLR->end, FillerEnd = BLR->start; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 153 | // We are about to delete CopyMI, so need to remove it as the 'instruction |
Evan Cheng | a8d94f1 | 2007-08-07 23:49:57 +0000 | [diff] [blame] | 154 | // that defines this value #'. Update the the valnum with the new defining |
| 155 | // instruction #. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 156 | BValNo->def = FillerStart; |
| 157 | BValNo->copy = NULL; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 158 | |
| 159 | // Okay, we can merge them. We need to insert a new liverange: |
| 160 | // [ValLR.end, BLR.begin) of either value number, then we merge the |
| 161 | // two value numbers. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 162 | IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo)); |
| 163 | |
| 164 | // If the IntB live range is assigned to a physical register, and if that |
| 165 | // physreg has aliases, |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 166 | if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 167 | // Update the liveintervals of sub-registers. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 168 | for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 169 | LiveInterval &AliasLI = li_->getInterval(*AS); |
| 170 | AliasLI.addRange(LiveRange(FillerStart, FillerEnd, |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 171 | AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator()))); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 172 | } |
| 173 | } |
| 174 | |
| 175 | // Okay, merge "B1" into the same value number as "B0". |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 176 | if (BValNo != ValLR->valno) |
| 177 | IntB.MergeValueNumberInto(BValNo, ValLR->valno); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 178 | DOUT << " result = "; IntB.print(DOUT, tri_); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 179 | DOUT << "\n"; |
| 180 | |
| 181 | // If the source instruction was killing the source register before the |
| 182 | // merge, unset the isKill marker given the live range has been extended. |
| 183 | int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true); |
| 184 | if (UIdx != -1) |
Chris Lattner | f738230 | 2007-12-30 21:56:09 +0000 | [diff] [blame] | 185 | ValLREndInst->getOperand(UIdx).setIsKill(false); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 186 | |
| 187 | ++numExtends; |
| 188 | return true; |
| 189 | } |
| 190 | |
Evan Cheng | 559f422 | 2008-02-16 02:32:17 +0000 | [diff] [blame] | 191 | /// HasOtherReachingDefs - Return true if there are definitions of IntB |
| 192 | /// other than BValNo val# that can reach uses of AValno val# of IntA. |
| 193 | bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA, |
| 194 | LiveInterval &IntB, |
| 195 | VNInfo *AValNo, |
| 196 | VNInfo *BValNo) { |
| 197 | for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end(); |
| 198 | AI != AE; ++AI) { |
| 199 | if (AI->valno != AValNo) continue; |
| 200 | LiveInterval::Ranges::iterator BI = |
| 201 | std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start); |
| 202 | if (BI != IntB.ranges.begin()) |
| 203 | --BI; |
| 204 | for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) { |
| 205 | if (BI->valno == BValNo) |
| 206 | continue; |
| 207 | if (BI->start <= AI->start && BI->end > AI->start) |
| 208 | return true; |
| 209 | if (BI->start > AI->start && BI->start < AI->end) |
| 210 | return true; |
| 211 | } |
| 212 | } |
| 213 | return false; |
| 214 | } |
| 215 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 216 | /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA |
| 217 | /// being the source and IntB being the dest, thus this defines a value number |
| 218 | /// in IntB. If the source value number (in IntA) is defined by a commutable |
| 219 | /// instruction and its other operand is coalesced to the copy dest register, |
| 220 | /// see if we can transform the copy into a noop by commuting the definition. For |
| 221 | /// example, |
| 222 | /// |
| 223 | /// A3 = op A2 B0<kill> |
| 224 | /// ... |
| 225 | /// B1 = A3 <- this copy |
| 226 | /// ... |
| 227 | /// = op A3 <- more uses |
| 228 | /// |
| 229 | /// ==> |
| 230 | /// |
| 231 | /// B2 = op B0 A2<kill> |
| 232 | /// ... |
| 233 | /// B1 = B2 <- now an identify copy |
| 234 | /// ... |
| 235 | /// = op B2 <- more uses |
| 236 | /// |
| 237 | /// This returns true if an interval was modified. |
| 238 | /// |
| 239 | bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, |
| 240 | LiveInterval &IntB, |
| 241 | MachineInstr *CopyMI) { |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 242 | unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI)); |
| 243 | |
Evan Cheng | a9407f5 | 2008-02-18 18:56:31 +0000 | [diff] [blame] | 244 | // FIXME: For now, only eliminate the copy by commuting its def when the |
| 245 | // source register is a virtual register. We want to guard against cases |
| 246 | // where the copy is a back edge copy and commuting the def lengthen the |
| 247 | // live interval of the source register to the entire loop. |
| 248 | if (TargetRegisterInfo::isPhysicalRegister(IntA.reg)) |
Evan Cheng | 96cfff0 | 2008-02-18 08:40:53 +0000 | [diff] [blame] | 249 | return false; |
| 250 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 251 | // BValNo is a value number in B that is defined by a copy from A. 'B3' in |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 252 | // the example above. |
| 253 | LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); |
| 254 | VNInfo *BValNo = BLR->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 255 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 256 | // Get the location that B is defined at. Two options: either this value has |
| 257 | // an unknown definition point or it is defined at CopyIdx. If unknown, we |
| 258 | // can't process it. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 259 | if (!BValNo->copy) return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 260 | assert(BValNo->def == CopyIdx && "Copy doesn't define the value?"); |
| 261 | |
| 262 | // AValNo is the value number in A that defines the copy, A3 in the example. |
| 263 | LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1); |
| 264 | VNInfo *AValNo = ALR->valno; |
Evan Cheng | e35a6d1 | 2008-02-13 08:41:08 +0000 | [diff] [blame] | 265 | // If other defs can reach uses of this def, then it's not safe to perform |
| 266 | // the optimization. |
| 267 | if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill) |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 268 | return false; |
| 269 | MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def); |
| 270 | const TargetInstrDesc &TID = DefMI->getDesc(); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 271 | unsigned NewDstIdx; |
| 272 | if (!TID.isCommutable() || |
| 273 | !tii_->CommuteChangesDestination(DefMI, NewDstIdx)) |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 274 | return false; |
| 275 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 276 | MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); |
| 277 | unsigned NewReg = NewDstMO.getReg(); |
| 278 | if (NewReg != IntB.reg || !NewDstMO.isKill()) |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 279 | return false; |
| 280 | |
| 281 | // Make sure there are no other definitions of IntB that would reach the |
| 282 | // uses which the new definition can reach. |
Evan Cheng | 559f422 | 2008-02-16 02:32:17 +0000 | [diff] [blame] | 283 | if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo)) |
| 284 | return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 285 | |
Evan Cheng | ed70cbb3 | 2008-03-26 19:03:01 +0000 | [diff] [blame] | 286 | // If some of the uses of IntA.reg is already coalesced away, return false. |
| 287 | // It's not possible to determine whether it's safe to perform the coalescing. |
| 288 | for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg), |
| 289 | UE = mri_->use_end(); UI != UE; ++UI) { |
| 290 | MachineInstr *UseMI = &*UI; |
| 291 | unsigned UseIdx = li_->getInstructionIndex(UseMI); |
| 292 | LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx); |
| 293 | if (ULR->valno == AValNo && JoinedCopies.count(UseMI)) |
| 294 | return false; |
| 295 | } |
| 296 | |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 297 | // At this point we have decided that it is legal to do this |
| 298 | // transformation. Start by commuting the instruction. |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 299 | MachineBasicBlock *MBB = DefMI->getParent(); |
| 300 | MachineInstr *NewMI = tii_->commuteInstruction(DefMI); |
Evan Cheng | 559f422 | 2008-02-16 02:32:17 +0000 | [diff] [blame] | 301 | if (!NewMI) |
| 302 | return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 303 | if (NewMI != DefMI) { |
| 304 | li_->ReplaceMachineInstrInMaps(DefMI, NewMI); |
| 305 | MBB->insert(DefMI, NewMI); |
| 306 | MBB->erase(DefMI); |
| 307 | } |
Evan Cheng | 6130f66 | 2008-03-05 00:59:57 +0000 | [diff] [blame] | 308 | unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 309 | NewMI->getOperand(OpIdx).setIsKill(); |
| 310 | |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 311 | bool BHasPHIKill = BValNo->hasPHIKill; |
| 312 | SmallVector<VNInfo*, 4> BDeadValNos; |
| 313 | SmallVector<unsigned, 4> BKills; |
| 314 | std::map<unsigned, unsigned> BExtend; |
Evan Cheng | 4ff3f1c | 2008-03-10 08:11:32 +0000 | [diff] [blame] | 315 | |
| 316 | // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g. |
| 317 | // A = or A, B |
| 318 | // ... |
| 319 | // B = A |
| 320 | // ... |
| 321 | // C = A<kill> |
| 322 | // ... |
| 323 | // = B |
| 324 | // |
| 325 | // then do not add kills of A to the newly created B interval. |
| 326 | bool Extended = BLR->end > ALR->end && ALR->end != ALR->start; |
| 327 | if (Extended) |
| 328 | BExtend[ALR->end] = BLR->end; |
| 329 | |
| 330 | // Update uses of IntA of the specific Val# with IntB. |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 331 | for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg), |
| 332 | UE = mri_->use_end(); UI != UE;) { |
| 333 | MachineOperand &UseMO = UI.getOperand(); |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 334 | MachineInstr *UseMI = &*UI; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 335 | ++UI; |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 336 | if (JoinedCopies.count(UseMI)) |
Evan Cheng | ed70cbb3 | 2008-03-26 19:03:01 +0000 | [diff] [blame] | 337 | continue; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 338 | unsigned UseIdx = li_->getInstructionIndex(UseMI); |
| 339 | LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx); |
| 340 | if (ULR->valno != AValNo) |
| 341 | continue; |
| 342 | UseMO.setReg(NewReg); |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 343 | if (UseMI == CopyMI) |
| 344 | continue; |
Evan Cheng | 4ff3f1c | 2008-03-10 08:11:32 +0000 | [diff] [blame] | 345 | if (UseMO.isKill()) { |
| 346 | if (Extended) |
| 347 | UseMO.setIsKill(false); |
| 348 | else |
| 349 | BKills.push_back(li_->getUseIndex(UseIdx)+1); |
| 350 | } |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 351 | unsigned SrcReg, DstReg; |
| 352 | if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) |
| 353 | continue; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 354 | if (DstReg == IntB.reg) { |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 355 | // This copy will become a noop. If it's defining a new val#, |
| 356 | // remove that val# as well. However this live range is being |
| 357 | // extended to the end of the existing live range defined by the copy. |
| 358 | unsigned DefIdx = li_->getDefIndex(UseIdx); |
| 359 | LiveInterval::iterator DLR = IntB.FindLiveRangeContaining(DefIdx); |
| 360 | BHasPHIKill |= DLR->valno->hasPHIKill; |
| 361 | assert(DLR->valno->def == DefIdx); |
| 362 | BDeadValNos.push_back(DLR->valno); |
| 363 | BExtend[DLR->start] = DLR->end; |
| 364 | JoinedCopies.insert(UseMI); |
| 365 | // If this is a kill but it's going to be removed, the last use |
| 366 | // of the same val# is the new kill. |
Evan Cheng | 4ff3f1c | 2008-03-10 08:11:32 +0000 | [diff] [blame] | 367 | if (UseMO.isKill()) |
Evan Cheng | cdbcfcc | 2008-02-13 09:56:03 +0000 | [diff] [blame] | 368 | BKills.pop_back(); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 369 | } |
| 370 | } |
| 371 | |
| 372 | // We need to insert a new liverange: [ALR.start, LastUse). It may be we can |
| 373 | // simply extend BLR if CopyMI doesn't end the range. |
| 374 | DOUT << "\nExtending: "; IntB.print(DOUT, tri_); |
| 375 | |
| 376 | IntB.removeValNo(BValNo); |
| 377 | for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) |
| 378 | IntB.removeValNo(BDeadValNos[i]); |
Evan Cheng | 82a6d23 | 2008-03-19 02:26:36 +0000 | [diff] [blame] | 379 | VNInfo *ValNo = IntB.getNextValue(AValNo->def, 0, li_->getVNInfoAllocator()); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 380 | for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end(); |
| 381 | AI != AE; ++AI) { |
| 382 | if (AI->valno != AValNo) continue; |
| 383 | unsigned End = AI->end; |
| 384 | std::map<unsigned, unsigned>::iterator EI = BExtend.find(End); |
| 385 | if (EI != BExtend.end()) |
| 386 | End = EI->second; |
| 387 | IntB.addRange(LiveRange(AI->start, End, ValNo)); |
| 388 | } |
| 389 | IntB.addKills(ValNo, BKills); |
| 390 | ValNo->hasPHIKill = BHasPHIKill; |
| 391 | |
| 392 | DOUT << " result = "; IntB.print(DOUT, tri_); |
| 393 | DOUT << "\n"; |
| 394 | |
| 395 | DOUT << "\nShortening: "; IntA.print(DOUT, tri_); |
| 396 | IntA.removeValNo(AValNo); |
| 397 | DOUT << " result = "; IntA.print(DOUT, tri_); |
| 398 | DOUT << "\n"; |
| 399 | |
| 400 | ++numCommutes; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 401 | return true; |
| 402 | } |
| 403 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 404 | /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy. |
| 405 | /// |
| 406 | bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI, |
| 407 | unsigned DstReg) { |
| 408 | MachineBasicBlock *MBB = CopyMI->getParent(); |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 409 | const MachineLoop *L = loopInfo->getLoopFor(MBB); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 410 | if (!L) |
| 411 | return false; |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 412 | if (MBB != L->getLoopLatch()) |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 413 | return false; |
| 414 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 415 | LiveInterval &LI = li_->getInterval(DstReg); |
| 416 | unsigned DefIdx = li_->getInstructionIndex(CopyMI); |
| 417 | LiveInterval::const_iterator DstLR = |
| 418 | LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx)); |
| 419 | if (DstLR == LI.end()) |
| 420 | return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 421 | unsigned KillIdx = li_->getInstructionIndex(&MBB->back()) + InstrSlots::NUM; |
| 422 | if (DstLR->valno->kills.size() == 1 && |
| 423 | DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill) |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 424 | return true; |
| 425 | return false; |
| 426 | } |
| 427 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 428 | /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and |
| 429 | /// update the subregister number if it is not zero. If DstReg is a |
| 430 | /// physical register and the existing subregister number of the def / use |
| 431 | /// being updated is not zero, make sure to set it to the correct physical |
| 432 | /// subregister. |
| 433 | void |
| 434 | SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, |
| 435 | unsigned SubIdx) { |
| 436 | bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); |
| 437 | if (DstIsPhys && SubIdx) { |
| 438 | // Figure out the real physical register we are updating with. |
| 439 | DstReg = tri_->getSubReg(DstReg, SubIdx); |
| 440 | SubIdx = 0; |
| 441 | } |
| 442 | |
| 443 | for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg), |
| 444 | E = mri_->reg_end(); I != E; ) { |
| 445 | MachineOperand &O = I.getOperand(); |
Evan Cheng | 70366b9 | 2008-03-21 19:09:30 +0000 | [diff] [blame] | 446 | MachineInstr *UseMI = &*I; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 447 | ++I; |
| 448 | if (DstIsPhys) { |
| 449 | unsigned UseSubIdx = O.getSubReg(); |
| 450 | unsigned UseDstReg = DstReg; |
| 451 | if (UseSubIdx) |
| 452 | UseDstReg = tri_->getSubReg(DstReg, UseSubIdx); |
| 453 | O.setReg(UseDstReg); |
| 454 | O.setSubReg(0); |
| 455 | } else { |
| 456 | unsigned OldSubIdx = O.getSubReg(); |
Evan Cheng | c886c46 | 2008-02-26 08:03:41 +0000 | [diff] [blame] | 457 | // Sub-register indexes goes from small to large. e.g. |
| 458 | // RAX: 0 -> AL, 1 -> AH, 2 -> AX, 3 -> EAX |
| 459 | // EAX: 0 -> AL, 1 -> AH, 2 -> AX |
| 460 | // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose |
| 461 | // sub-register 2 is also AX. |
| 462 | if (SubIdx && OldSubIdx && SubIdx != OldSubIdx) |
| 463 | assert(OldSubIdx < SubIdx && "Conflicting sub-register index!"); |
| 464 | else if (SubIdx) |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 465 | O.setSubReg(SubIdx); |
Evan Cheng | 70366b9 | 2008-03-21 19:09:30 +0000 | [diff] [blame] | 466 | // Remove would-be duplicated kill marker. |
| 467 | if (O.isKill() && UseMI->killsRegister(DstReg)) |
| 468 | O.setIsKill(false); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 469 | O.setReg(DstReg); |
| 470 | } |
| 471 | } |
| 472 | } |
| 473 | |
Evan Cheng | 4ff3f1c | 2008-03-10 08:11:32 +0000 | [diff] [blame] | 474 | /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate |
| 475 | /// due to live range lengthening as the result of coalescing. |
| 476 | void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg, |
| 477 | LiveInterval &LI) { |
| 478 | for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg), |
| 479 | UE = mri_->use_end(); UI != UE; ++UI) { |
| 480 | MachineOperand &UseMO = UI.getOperand(); |
| 481 | if (UseMO.isKill()) { |
| 482 | MachineInstr *UseMI = UseMO.getParent(); |
| 483 | unsigned SReg, DReg; |
| 484 | if (!tii_->isMoveInstr(*UseMI, SReg, DReg)) |
| 485 | continue; |
| 486 | unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI)); |
| 487 | if (JoinedCopies.count(UseMI)) |
| 488 | continue; |
| 489 | LiveInterval::const_iterator UI = LI.FindLiveRangeContaining(UseIdx); |
| 490 | assert(UI != LI.end()); |
| 491 | if (!LI.isKill(UI->valno, UseIdx+1)) |
| 492 | UseMO.setIsKill(false); |
| 493 | } |
| 494 | } |
| 495 | } |
| 496 | |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 497 | /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range |
| 498 | /// from a physical register live interval as well as from the live intervals |
| 499 | /// of its sub-registers. |
| 500 | static void removeRange(LiveInterval &li, unsigned Start, unsigned End, |
| 501 | LiveIntervals *li_, const TargetRegisterInfo *tri_) { |
| 502 | li.removeRange(Start, End, true); |
| 503 | if (TargetRegisterInfo::isPhysicalRegister(li.reg)) { |
| 504 | for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) { |
| 505 | if (!li_->hasInterval(*SR)) |
| 506 | continue; |
| 507 | LiveInterval &sli = li_->getInterval(*SR); |
| 508 | unsigned RemoveEnd = Start; |
| 509 | while (RemoveEnd != End) { |
| 510 | LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start); |
| 511 | if (LR == sli.end()) |
| 512 | break; |
| 513 | RemoveEnd = (LR->end < End) ? LR->end : End; |
| 514 | sli.removeRange(Start, RemoveEnd, true); |
| 515 | Start = RemoveEnd; |
| 516 | } |
| 517 | } |
| 518 | } |
| 519 | } |
| 520 | |
| 521 | /// removeIntervalIfEmpty - Check if the live interval of a physical register |
| 522 | /// is empty, if so remove it and also remove the empty intervals of its |
| 523 | /// sub-registers. |
| 524 | static void removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_, |
| 525 | const TargetRegisterInfo *tri_) { |
| 526 | if (li.empty()) { |
| 527 | li_->removeInterval(li.reg); |
| 528 | if (TargetRegisterInfo::isPhysicalRegister(li.reg)) |
| 529 | for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) { |
| 530 | if (!li_->hasInterval(*SR)) |
| 531 | continue; |
| 532 | LiveInterval &sli = li_->getInterval(*SR); |
| 533 | if (sli.empty()) |
| 534 | li_->removeInterval(*SR); |
| 535 | } |
| 536 | } |
| 537 | } |
| 538 | |
| 539 | /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy. |
| 540 | /// |
Evan Cheng | ecb2a8b | 2008-03-05 22:09:42 +0000 | [diff] [blame] | 541 | void SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li, |
| 542 | MachineInstr *CopyMI) { |
| 543 | unsigned CopyIdx = li_->getInstructionIndex(CopyMI); |
| 544 | LiveInterval::iterator MLR = |
| 545 | li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx)); |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 546 | if (MLR == li.end()) |
| 547 | return; // Already removed by ShortenDeadCopySrcLiveRange. |
Evan Cheng | ecb2a8b | 2008-03-05 22:09:42 +0000 | [diff] [blame] | 548 | unsigned RemoveStart = MLR->start; |
| 549 | unsigned RemoveEnd = MLR->end; |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 550 | // Remove the liverange that's defined by this. |
| 551 | if (RemoveEnd == li_->getDefIndex(CopyIdx)+1) { |
| 552 | removeRange(li, RemoveStart, RemoveEnd, li_, tri_); |
| 553 | removeIntervalIfEmpty(li, li_, tri_); |
Evan Cheng | ecb2a8b | 2008-03-05 22:09:42 +0000 | [diff] [blame] | 554 | } |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 555 | } |
| 556 | |
Evan Cheng | 0c28432 | 2008-03-26 20:15:49 +0000 | [diff] [blame^] | 557 | /// PropagateDeadness - Propagate the dead marker to the instruction which |
| 558 | /// defines the val#. |
| 559 | static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI, |
| 560 | unsigned &LRStart, LiveIntervals *li_, |
| 561 | const TargetRegisterInfo* tri_) { |
| 562 | MachineInstr *DefMI = |
| 563 | li_->getInstructionFromIndex(li_->getDefIndex(LRStart)); |
| 564 | if (DefMI && DefMI != CopyMI) { |
| 565 | int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_); |
| 566 | if (DeadIdx != -1) { |
| 567 | DefMI->getOperand(DeadIdx).setIsDead(); |
| 568 | // A dead def should have a single cycle interval. |
| 569 | ++LRStart; |
| 570 | } |
| 571 | } |
| 572 | } |
| 573 | |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 574 | /// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially |
| 575 | /// extended by a dead copy. Mark the last use (if any) of the val# as kill |
| 576 | /// as ends the live range there. If there isn't another use, then this |
| 577 | /// live range is dead. |
| 578 | void |
| 579 | SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li, |
| 580 | MachineInstr *CopyMI) { |
| 581 | unsigned CopyIdx = li_->getInstructionIndex(CopyMI); |
| 582 | if (CopyIdx == 0) { |
| 583 | // FIXME: special case: function live in. It can be a general case if the |
| 584 | // first instruction index starts at > 0 value. |
| 585 | assert(TargetRegisterInfo::isPhysicalRegister(li.reg)); |
| 586 | // Live-in to the function but dead. Remove it from entry live-in set. |
| 587 | mf_->begin()->removeLiveIn(li.reg); |
| 588 | LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx); |
| 589 | removeRange(li, LR->start, LR->end, li_, tri_); |
| 590 | removeIntervalIfEmpty(li, li_, tri_); |
| 591 | return; |
| 592 | } |
| 593 | |
| 594 | LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1); |
| 595 | if (LR == li.end()) |
| 596 | // Livein but defined by a phi. |
| 597 | return; |
| 598 | |
| 599 | unsigned RemoveStart = LR->start; |
| 600 | unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1; |
| 601 | if (LR->end > RemoveEnd) |
| 602 | // More uses past this copy? Nothing to do. |
| 603 | return; |
| 604 | |
| 605 | unsigned LastUseIdx; |
| 606 | MachineOperand *LastUse = |
| 607 | lastRegisterUse(LR->start, CopyIdx-1, li.reg, LastUseIdx); |
| 608 | if (LastUse) { |
| 609 | // There are uses before the copy, just shorten the live range to the end |
| 610 | // of last use. |
| 611 | LastUse->setIsKill(); |
| 612 | MachineInstr *LastUseMI = LastUse->getParent(); |
| 613 | removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_); |
| 614 | unsigned SrcReg, DstReg; |
| 615 | if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg) && |
| 616 | DstReg == li.reg) { |
| 617 | // Last use is itself an identity code. |
| 618 | int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_); |
| 619 | LastUseMI->getOperand(DeadIdx).setIsDead(); |
| 620 | } |
| 621 | return; |
| 622 | } |
| 623 | |
| 624 | // Is it livein? |
| 625 | MachineBasicBlock *CopyMBB = CopyMI->getParent(); |
| 626 | unsigned MBBStart = li_->getMBBStartIdx(CopyMBB); |
| 627 | if (LR->start <= MBBStart && LR->end > MBBStart) { |
| 628 | if (LR->start == 0) { |
| 629 | assert(TargetRegisterInfo::isPhysicalRegister(li.reg)); |
| 630 | // Live-in to the function but dead. Remove it from entry live-in set. |
| 631 | mf_->begin()->removeLiveIn(li.reg); |
| 632 | } |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 633 | // FIXME: Shorten intervals in BBs that reaches this BB. |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 634 | } |
| 635 | |
Evan Cheng | 0c28432 | 2008-03-26 20:15:49 +0000 | [diff] [blame^] | 636 | if (LR->valno->def == RemoveStart) |
| 637 | // If the def MI defines the val#, propagate the dead marker. |
| 638 | PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_); |
| 639 | |
| 640 | removeRange(li, RemoveStart, LR->end, li_, tri_); |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 641 | removeIntervalIfEmpty(li, li_, tri_); |
Evan Cheng | ecb2a8b | 2008-03-05 22:09:42 +0000 | [diff] [blame] | 642 | } |
| 643 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 644 | /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, |
| 645 | /// which are the src/dst of the copy instruction CopyMI. This returns true |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 646 | /// if the copy was successfully coalesced away. If it is not currently |
| 647 | /// possible to coalesce this interval, but it may be possible if other |
| 648 | /// things get coalesced, then it returns true by reference in 'Again'. |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 649 | bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 650 | MachineInstr *CopyMI = TheCopy.MI; |
| 651 | |
| 652 | Again = false; |
| 653 | if (JoinedCopies.count(CopyMI)) |
| 654 | return false; // Already done. |
| 655 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 656 | DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI; |
| 657 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 658 | unsigned SrcReg; |
| 659 | unsigned DstReg; |
| 660 | bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG; |
| 661 | unsigned SubIdx = 0; |
| 662 | if (isExtSubReg) { |
| 663 | DstReg = CopyMI->getOperand(0).getReg(); |
| 664 | SrcReg = CopyMI->getOperand(1).getReg(); |
| 665 | } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) { |
| 666 | assert(0 && "Unrecognized copy instruction!"); |
| 667 | return false; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 668 | } |
| 669 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 670 | // If they are already joined we continue. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 671 | if (SrcReg == DstReg) { |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 672 | DOUT << "\tCopy already coalesced.\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 673 | return false; // Not coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 674 | } |
| 675 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 676 | bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); |
| 677 | bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 678 | |
| 679 | // If they are both physical registers, we cannot join them. |
| 680 | if (SrcIsPhys && DstIsPhys) { |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 681 | DOUT << "\tCan not coalesce physregs.\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 682 | return false; // Not coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 683 | } |
| 684 | |
| 685 | // We only join virtual registers with allocatable physical registers. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 686 | if (SrcIsPhys && !allocatableRegs_[SrcReg]) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 687 | DOUT << "\tSrc reg is unallocatable physreg.\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 688 | return false; // Not coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 689 | } |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 690 | if (DstIsPhys && !allocatableRegs_[DstReg]) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 691 | DOUT << "\tDst reg is unallocatable physreg.\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 692 | return false; // Not coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 693 | } |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 694 | |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 695 | unsigned RealDstReg = 0; |
| 696 | if (isExtSubReg) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 697 | SubIdx = CopyMI->getOperand(2).getImm(); |
| 698 | if (SrcIsPhys) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 699 | // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be |
| 700 | // coalesced with AX. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 701 | SrcReg = tri_->getSubReg(SrcReg, SubIdx); |
| 702 | SubIdx = 0; |
| 703 | } else if (DstIsPhys) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 704 | // If this is a extract_subreg where dst is a physical register, e.g. |
| 705 | // cl = EXTRACT_SUBREG reg1024, 1 |
| 706 | // then create and update the actual physical register allocated to RHS. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 707 | const TargetRegisterClass *RC = mri_->getRegClass(SrcReg); |
| 708 | for (const unsigned *SRs = tri_->getSuperRegisters(DstReg); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 709 | unsigned SR = *SRs; ++SRs) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 710 | if (DstReg == tri_->getSubReg(SR, SubIdx) && |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 711 | RC->contains(SR)) { |
| 712 | RealDstReg = SR; |
| 713 | break; |
| 714 | } |
| 715 | } |
| 716 | assert(RealDstReg && "Invalid extra_subreg instruction!"); |
| 717 | |
| 718 | // For this type of EXTRACT_SUBREG, conservatively |
| 719 | // check if the live interval of the source register interfere with the |
| 720 | // actual super physical register we are trying to coalesce with. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 721 | LiveInterval &RHS = li_->getInterval(SrcReg); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 722 | if (li_->hasInterval(RealDstReg) && |
| 723 | RHS.overlaps(li_->getInterval(RealDstReg))) { |
| 724 | DOUT << "Interfere with register "; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 725 | DEBUG(li_->getInterval(RealDstReg).print(DOUT, tri_)); |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 726 | return false; // Not coalescable |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 727 | } |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 728 | for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR) |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 729 | if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) { |
| 730 | DOUT << "Interfere with sub-register "; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 731 | DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 732 | return false; // Not coalescable |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 733 | } |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 734 | SubIdx = 0; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 735 | } else { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 736 | unsigned SrcSize= li_->getInterval(SrcReg).getSize() / InstrSlots::NUM; |
| 737 | unsigned DstSize= li_->getInterval(DstReg).getSize() / InstrSlots::NUM; |
| 738 | const TargetRegisterClass *RC = mri_->getRegClass(DstReg); |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 739 | unsigned Threshold = allocatableRCRegs_[RC].count(); |
Evan Cheng | 52c7ff7 | 2007-10-12 09:15:53 +0000 | [diff] [blame] | 740 | // Be conservative. If both sides are virtual registers, do not coalesce |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 741 | // if this will cause a high use density interval to target a smaller set |
| 742 | // of registers. |
| 743 | if (DstSize > Threshold || SrcSize > Threshold) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 744 | LiveVariables::VarInfo &svi = lv_->getVarInfo(SrcReg); |
| 745 | LiveVariables::VarInfo &dvi = lv_->getVarInfo(DstReg); |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 746 | if ((float)dvi.NumUses / DstSize < (float)svi.NumUses / SrcSize) { |
| 747 | Again = true; // May be possible to coalesce later. |
| 748 | return false; |
| 749 | } |
| 750 | } |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 751 | } |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 752 | } else if (differingRegisterClasses(SrcReg, DstReg)) { |
| 753 | // FIXME: What if the resul of a EXTRACT_SUBREG is then coalesced |
| 754 | // with another? If it's the resulting destination register, then |
| 755 | // the subidx must be propagated to uses (but only those defined |
| 756 | // by the EXTRACT_SUBREG). If it's being coalesced into another |
| 757 | // register, it should be safe because register is assumed to have |
| 758 | // the register class of the super-register. |
| 759 | |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 760 | // If they are not of the same register class, we cannot join them. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 761 | DOUT << "\tSrc/Dest are different register classes.\n"; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 762 | // Allow the coalescer to try again in case either side gets coalesced to |
| 763 | // a physical register that's compatible with the other side. e.g. |
| 764 | // r1024 = MOV32to32_ r1025 |
| 765 | // but later r1024 is assigned EAX then r1025 may be coalesced with EAX. |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 766 | Again = true; // May be possible to coalesce later. |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 767 | return false; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 768 | } |
| 769 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 770 | LiveInterval &SrcInt = li_->getInterval(SrcReg); |
| 771 | LiveInterval &DstInt = li_->getInterval(DstReg); |
| 772 | assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg && |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 773 | "Register mapping is horribly broken!"); |
| 774 | |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 775 | DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_); |
| 776 | DOUT << " and "; DstInt.print(DOUT, tri_); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 777 | DOUT << ": "; |
| 778 | |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 779 | // Check if it is necessary to propagate "isDead" property. |
Evan Cheng | 6130f66 | 2008-03-05 00:59:57 +0000 | [diff] [blame] | 780 | MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 781 | bool isDead = mopd->isDead(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 782 | |
| 783 | // We need to be careful about coalescing a source physical register with a |
| 784 | // virtual register. Once the coalescing is done, it cannot be broken and |
| 785 | // these are not spillable! If the destination interval uses are far away, |
| 786 | // think twice about coalescing them! |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 787 | if (!isDead && (SrcIsPhys || DstIsPhys) && !isExtSubReg) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 788 | LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 789 | unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg; |
| 790 | unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg; |
| 791 | const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg); |
Evan Cheng | 6894942 | 2007-12-20 02:23:25 +0000 | [diff] [blame] | 792 | unsigned Threshold = allocatableRCRegs_[RC].count() * 2; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 793 | if (TheCopy.isBackEdge) |
| 794 | Threshold *= 2; // Favors back edge copies. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 795 | |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 796 | // If the virtual register live interval is long but it has low use desity, |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 797 | // do not join them, instead mark the physical register as its allocation |
| 798 | // preference. |
| 799 | unsigned Length = JoinVInt.getSize() / InstrSlots::NUM; |
| 800 | LiveVariables::VarInfo &vi = lv_->getVarInfo(JoinVReg); |
| 801 | if (Length > Threshold && |
| 802 | (((float)vi.NumUses / Length) < (1.0 / Threshold))) { |
| 803 | JoinVInt.preference = JoinPReg; |
| 804 | ++numAborts; |
| 805 | DOUT << "\tMay tie down a physical register, abort!\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 806 | Again = true; // May be possible to coalesce later. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 807 | return false; |
| 808 | } |
| 809 | } |
| 810 | |
| 811 | // Okay, attempt to join these two intervals. On failure, this returns false. |
| 812 | // Otherwise, if one of the intervals being joined is a physreg, this method |
| 813 | // always canonicalizes DstInt to be it. The output "SrcInt" will not have |
| 814 | // been modified, so we can use this information below to update aliases. |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 815 | bool Swapped = false; |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 816 | if (!JoinIntervals(DstInt, SrcInt, Swapped)) { |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 817 | // Coalescing failed. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 818 | |
| 819 | // If we can eliminate the copy without merging the live ranges, do so now. |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 820 | if (!isExtSubReg && |
| 821 | (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) || |
| 822 | RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) { |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 823 | JoinedCopies.insert(CopyMI); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 824 | return true; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 825 | } |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 826 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 827 | // Otherwise, we are unable to join the intervals. |
| 828 | DOUT << "Interference!\n"; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 829 | Again = true; // May be possible to coalesce later. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 830 | return false; |
| 831 | } |
| 832 | |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 833 | LiveInterval *ResSrcInt = &SrcInt; |
| 834 | LiveInterval *ResDstInt = &DstInt; |
| 835 | if (Swapped) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 836 | std::swap(SrcReg, DstReg); |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 837 | std::swap(ResSrcInt, ResDstInt); |
| 838 | } |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 839 | assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 840 | "LiveInterval::join didn't work right!"); |
| 841 | |
| 842 | // If we're about to merge live ranges into a physical register live range, |
| 843 | // we have to update any aliased register's live ranges to indicate that they |
| 844 | // have clobbered values for this range. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 845 | if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 846 | // If this is a extract_subreg where dst is a physical register, e.g. |
| 847 | // cl = EXTRACT_SUBREG reg1024, 1 |
| 848 | // then create and update the actual physical register allocated to RHS. |
| 849 | if (RealDstReg) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 850 | LiveInterval &RealDstInt = li_->getOrCreateInterval(RealDstReg); |
Evan Cheng | f5c7359 | 2007-10-15 18:33:50 +0000 | [diff] [blame] | 851 | SmallSet<const VNInfo*, 4> CopiedValNos; |
| 852 | for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(), |
| 853 | E = ResSrcInt->ranges.end(); I != E; ++I) { |
| 854 | LiveInterval::const_iterator DstLR = |
| 855 | ResDstInt->FindLiveRangeContaining(I->start); |
| 856 | assert(DstLR != ResDstInt->end() && "Invalid joined interval!"); |
| 857 | const VNInfo *DstValNo = DstLR->valno; |
| 858 | if (CopiedValNos.insert(DstValNo)) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 859 | VNInfo *ValNo = RealDstInt.getNextValue(DstValNo->def, DstValNo->copy, |
Evan Cheng | f5c7359 | 2007-10-15 18:33:50 +0000 | [diff] [blame] | 860 | li_->getVNInfoAllocator()); |
Evan Cheng | c3fc7d9 | 2007-11-29 09:49:23 +0000 | [diff] [blame] | 861 | ValNo->hasPHIKill = DstValNo->hasPHIKill; |
Evan Cheng | f5c7359 | 2007-10-15 18:33:50 +0000 | [diff] [blame] | 862 | RealDstInt.addKills(ValNo, DstValNo->kills); |
| 863 | RealDstInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo); |
| 864 | } |
Evan Cheng | 3472925 | 2007-10-14 10:08:34 +0000 | [diff] [blame] | 865 | } |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 866 | DstReg = RealDstReg; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 867 | } |
| 868 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 869 | // Update the liveintervals of sub-registers. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 870 | for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS) |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 871 | li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt, |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 872 | li_->getVNInfoAllocator()); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 873 | } else { |
| 874 | // Merge use info if the destination is a virtual register. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 875 | LiveVariables::VarInfo& dVI = lv_->getVarInfo(DstReg); |
| 876 | LiveVariables::VarInfo& sVI = lv_->getVarInfo(SrcReg); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 877 | dVI.NumUses += sVI.NumUses; |
| 878 | } |
| 879 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 880 | // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the |
| 881 | // larger super-register. |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 882 | if (isExtSubReg && !SrcIsPhys && !DstIsPhys) { |
| 883 | if (!Swapped) { |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 884 | ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator()); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 885 | std::swap(SrcReg, DstReg); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 886 | std::swap(ResSrcInt, ResDstInt); |
| 887 | } |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 888 | } |
| 889 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 890 | if (NewHeuristic) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 891 | // Add all copies that define val# in the source interval into the queue. |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 892 | for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(), |
| 893 | e = ResSrcInt->vni_end(); i != e; ++i) { |
| 894 | const VNInfo *vni = *i; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 895 | if (!vni->def || vni->def == ~1U || vni->def == ~0U) |
| 896 | continue; |
| 897 | MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def); |
| 898 | unsigned NewSrcReg, NewDstReg; |
| 899 | if (CopyMI && |
| 900 | JoinedCopies.count(CopyMI) == 0 && |
| 901 | tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg)) { |
| 902 | unsigned LoopDepth = loopInfo->getLoopDepth(CopyMI->getParent()); |
| 903 | JoinQueue->push(CopyRec(CopyMI, LoopDepth, |
| 904 | isBackEdgeCopy(CopyMI, DstReg))); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 905 | } |
| 906 | } |
| 907 | } |
| 908 | |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 909 | DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_); |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 910 | DOUT << "\n"; |
| 911 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 912 | // Remember to delete the copy instruction. |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 913 | JoinedCopies.insert(CopyMI); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 914 | |
Evan Cheng | 4ff3f1c | 2008-03-10 08:11:32 +0000 | [diff] [blame] | 915 | // Some live range has been lengthened due to colaescing, eliminate the |
| 916 | // unnecessary kills. |
| 917 | RemoveUnnecessaryKills(SrcReg, *ResDstInt); |
| 918 | if (TargetRegisterInfo::isVirtualRegister(DstReg)) |
| 919 | RemoveUnnecessaryKills(DstReg, *ResDstInt); |
| 920 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 921 | // SrcReg is guarateed to be the register whose live interval that is |
| 922 | // being merged. |
| 923 | li_->removeInterval(SrcReg); |
| 924 | UpdateRegDefsUses(SrcReg, DstReg, SubIdx); |
| 925 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 926 | ++numJoins; |
| 927 | return true; |
| 928 | } |
| 929 | |
| 930 | /// ComputeUltimateVN - Assuming we are going to join two live intervals, |
| 931 | /// compute what the resultant value numbers for each value in the input two |
| 932 | /// ranges will be. This is complicated by copies between the two which can |
| 933 | /// and will commonly cause multiple value numbers to be merged into one. |
| 934 | /// |
| 935 | /// VN is the value number that we're trying to resolve. InstDefiningValue |
| 936 | /// keeps track of the new InstDefiningValue assignment for the result |
| 937 | /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of |
| 938 | /// whether a value in this or other is a copy from the opposite set. |
| 939 | /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have |
| 940 | /// already been assigned. |
| 941 | /// |
| 942 | /// ThisFromOther[x] - If x is defined as a copy from the other interval, this |
| 943 | /// contains the value number the copy is from. |
| 944 | /// |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 945 | static unsigned ComputeUltimateVN(VNInfo *VNI, |
| 946 | SmallVector<VNInfo*, 16> &NewVNInfo, |
Evan Cheng | fadfb5b | 2007-08-31 21:23:06 +0000 | [diff] [blame] | 947 | DenseMap<VNInfo*, VNInfo*> &ThisFromOther, |
| 948 | DenseMap<VNInfo*, VNInfo*> &OtherFromThis, |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 949 | SmallVector<int, 16> &ThisValNoAssignments, |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 950 | SmallVector<int, 16> &OtherValNoAssignments) { |
| 951 | unsigned VN = VNI->id; |
| 952 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 953 | // If the VN has already been computed, just return it. |
| 954 | if (ThisValNoAssignments[VN] >= 0) |
| 955 | return ThisValNoAssignments[VN]; |
| 956 | // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?"); |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 957 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 958 | // If this val is not a copy from the other val, then it must be a new value |
| 959 | // number in the destination. |
Evan Cheng | fadfb5b | 2007-08-31 21:23:06 +0000 | [diff] [blame] | 960 | DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI); |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 961 | if (I == ThisFromOther.end()) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 962 | NewVNInfo.push_back(VNI); |
| 963 | return ThisValNoAssignments[VN] = NewVNInfo.size()-1; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 964 | } |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 965 | VNInfo *OtherValNo = I->second; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 966 | |
| 967 | // Otherwise, this *is* a copy from the RHS. If the other side has already |
| 968 | // been computed, return it. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 969 | if (OtherValNoAssignments[OtherValNo->id] >= 0) |
| 970 | return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id]; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 971 | |
| 972 | // Mark this value number as currently being computed, then ask what the |
| 973 | // ultimate value # of the other value is. |
| 974 | ThisValNoAssignments[VN] = -2; |
| 975 | unsigned UltimateVN = |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 976 | ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther, |
| 977 | OtherValNoAssignments, ThisValNoAssignments); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 978 | return ThisValNoAssignments[VN] = UltimateVN; |
| 979 | } |
| 980 | |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 981 | static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 982 | return std::find(V.begin(), V.end(), Val) != V.end(); |
| 983 | } |
| 984 | |
| 985 | /// SimpleJoin - Attempt to joint the specified interval into this one. The |
| 986 | /// caller of this method must guarantee that the RHS only contains a single |
| 987 | /// value number and that the RHS is not defined by a copy from this |
| 988 | /// interval. This returns false if the intervals are not joinable, or it |
| 989 | /// joins them and returns true. |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 990 | bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){ |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 991 | assert(RHS.containsOneValue()); |
| 992 | |
| 993 | // Some number (potentially more than one) value numbers in the current |
| 994 | // interval may be defined as copies from the RHS. Scan the overlapping |
| 995 | // portions of the LHS and RHS, keeping track of this and looking for |
| 996 | // overlapping live ranges that are NOT defined as copies. If these exist, we |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 997 | // cannot coalesce. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 998 | |
| 999 | LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end(); |
| 1000 | LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end(); |
| 1001 | |
| 1002 | if (LHSIt->start < RHSIt->start) { |
| 1003 | LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start); |
| 1004 | if (LHSIt != LHS.begin()) --LHSIt; |
| 1005 | } else if (RHSIt->start < LHSIt->start) { |
| 1006 | RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start); |
| 1007 | if (RHSIt != RHS.begin()) --RHSIt; |
| 1008 | } |
| 1009 | |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1010 | SmallVector<VNInfo*, 8> EliminatedLHSVals; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1011 | |
| 1012 | while (1) { |
| 1013 | // Determine if these live intervals overlap. |
| 1014 | bool Overlaps = false; |
| 1015 | if (LHSIt->start <= RHSIt->start) |
| 1016 | Overlaps = LHSIt->end > RHSIt->start; |
| 1017 | else |
| 1018 | Overlaps = RHSIt->end > LHSIt->start; |
| 1019 | |
| 1020 | // If the live intervals overlap, there are two interesting cases: if the |
| 1021 | // LHS interval is defined by a copy from the RHS, it's ok and we record |
| 1022 | // that the LHS value # is the same as the RHS. If it's not, then we cannot |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1023 | // coalesce these live ranges and we bail out. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1024 | if (Overlaps) { |
| 1025 | // If we haven't already recorded that this value # is safe, check it. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1026 | if (!InVector(LHSIt->valno, EliminatedLHSVals)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1027 | // Copy from the RHS? |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1028 | unsigned SrcReg = li_->getVNInfoSourceReg(LHSIt->valno); |
| 1029 | if (SrcReg != RHS.reg) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1030 | return false; // Nope, bail out. |
| 1031 | |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1032 | EliminatedLHSVals.push_back(LHSIt->valno); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1033 | } |
| 1034 | |
| 1035 | // We know this entire LHS live range is okay, so skip it now. |
| 1036 | if (++LHSIt == LHSEnd) break; |
| 1037 | continue; |
| 1038 | } |
| 1039 | |
| 1040 | if (LHSIt->end < RHSIt->end) { |
| 1041 | if (++LHSIt == LHSEnd) break; |
| 1042 | } else { |
| 1043 | // One interesting case to check here. It's possible that we have |
| 1044 | // something like "X3 = Y" which defines a new value number in the LHS, |
| 1045 | // and is the last use of this liverange of the RHS. In this case, we |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1046 | // want to notice this copy (so that it gets coalesced away) even though |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1047 | // the live ranges don't actually overlap. |
| 1048 | if (LHSIt->start == RHSIt->end) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1049 | if (InVector(LHSIt->valno, EliminatedLHSVals)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1050 | // We already know that this value number is going to be merged in |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1051 | // if coalescing succeeds. Just skip the liverange. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1052 | if (++LHSIt == LHSEnd) break; |
| 1053 | } else { |
| 1054 | // Otherwise, if this is a copy from the RHS, mark it as being merged |
| 1055 | // in. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1056 | if (li_->getVNInfoSourceReg(LHSIt->valno) == RHS.reg) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1057 | EliminatedLHSVals.push_back(LHSIt->valno); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1058 | |
| 1059 | // We know this entire LHS live range is okay, so skip it now. |
| 1060 | if (++LHSIt == LHSEnd) break; |
| 1061 | } |
| 1062 | } |
| 1063 | } |
| 1064 | |
| 1065 | if (++RHSIt == RHSEnd) break; |
| 1066 | } |
| 1067 | } |
| 1068 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1069 | // If we got here, we know that the coalescing will be successful and that |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1070 | // the value numbers in EliminatedLHSVals will all be merged together. Since |
| 1071 | // the most common case is that EliminatedLHSVals has a single number, we |
| 1072 | // optimize for it: if there is more than one value, we merge them all into |
| 1073 | // the lowest numbered one, then handle the interval as if we were merging |
| 1074 | // with one value number. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1075 | VNInfo *LHSValNo; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1076 | if (EliminatedLHSVals.size() > 1) { |
| 1077 | // Loop through all the equal value numbers merging them into the smallest |
| 1078 | // one. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1079 | VNInfo *Smallest = EliminatedLHSVals[0]; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1080 | for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1081 | if (EliminatedLHSVals[i]->id < Smallest->id) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1082 | // Merge the current notion of the smallest into the smaller one. |
| 1083 | LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]); |
| 1084 | Smallest = EliminatedLHSVals[i]; |
| 1085 | } else { |
| 1086 | // Merge into the smallest. |
| 1087 | LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest); |
| 1088 | } |
| 1089 | } |
| 1090 | LHSValNo = Smallest; |
| 1091 | } else { |
| 1092 | assert(!EliminatedLHSVals.empty() && "No copies from the RHS?"); |
| 1093 | LHSValNo = EliminatedLHSVals[0]; |
| 1094 | } |
| 1095 | |
| 1096 | // Okay, now that there is a single LHS value number that we're merging the |
| 1097 | // RHS into, update the value number info for the LHS to indicate that the |
| 1098 | // value number is defined where the RHS value number was. |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 1099 | const VNInfo *VNI = RHS.getValNumInfo(0); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1100 | LHSValNo->def = VNI->def; |
| 1101 | LHSValNo->copy = VNI->copy; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1102 | |
| 1103 | // Okay, the final step is to loop over the RHS live intervals, adding them to |
| 1104 | // the LHS. |
Evan Cheng | c3fc7d9 | 2007-11-29 09:49:23 +0000 | [diff] [blame] | 1105 | LHSValNo->hasPHIKill |= VNI->hasPHIKill; |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 1106 | LHS.addKills(LHSValNo, VNI->kills); |
Evan Cheng | 430a7b0 | 2007-08-14 01:56:58 +0000 | [diff] [blame] | 1107 | LHS.MergeRangesInAsValue(RHS, LHSValNo); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1108 | LHS.weight += RHS.weight; |
| 1109 | if (RHS.preference && !LHS.preference) |
| 1110 | LHS.preference = RHS.preference; |
| 1111 | |
| 1112 | return true; |
| 1113 | } |
| 1114 | |
| 1115 | /// JoinIntervals - Attempt to join these two intervals. On failure, this |
| 1116 | /// returns false. Otherwise, if one of the intervals being joined is a |
| 1117 | /// physreg, this method always canonicalizes LHS to be it. The output |
| 1118 | /// "RHS" will not have been modified, so we can use this information |
| 1119 | /// below to update aliases. |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 1120 | bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, |
| 1121 | LiveInterval &RHS, bool &Swapped) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1122 | // Compute the final value assignment, assuming that the live ranges can be |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1123 | // coalesced. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1124 | SmallVector<int, 16> LHSValNoAssignments; |
| 1125 | SmallVector<int, 16> RHSValNoAssignments; |
Evan Cheng | fadfb5b | 2007-08-31 21:23:06 +0000 | [diff] [blame] | 1126 | DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS; |
| 1127 | DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1128 | SmallVector<VNInfo*, 16> NewVNInfo; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1129 | |
| 1130 | // If a live interval is a physical register, conservatively check if any |
| 1131 | // of its sub-registers is overlapping the live interval of the virtual |
| 1132 | // register. If so, do not coalesce. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1133 | if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) && |
| 1134 | *tri_->getSubRegisters(LHS.reg)) { |
| 1135 | for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1136 | if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) { |
| 1137 | DOUT << "Interfere with sub-register "; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1138 | DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1139 | return false; |
| 1140 | } |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1141 | } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) && |
| 1142 | *tri_->getSubRegisters(RHS.reg)) { |
| 1143 | for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1144 | if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) { |
| 1145 | DOUT << "Interfere with sub-register "; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1146 | DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1147 | return false; |
| 1148 | } |
| 1149 | } |
| 1150 | |
| 1151 | // Compute ultimate value numbers for the LHS and RHS values. |
| 1152 | if (RHS.containsOneValue()) { |
| 1153 | // Copies from a liveinterval with a single value are simple to handle and |
| 1154 | // very common, handle the special case here. This is important, because |
| 1155 | // often RHS is small and LHS is large (e.g. a physreg). |
| 1156 | |
| 1157 | // Find out if the RHS is defined as a copy from some value in the LHS. |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1158 | int RHSVal0DefinedFromLHS = -1; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1159 | int RHSValID = -1; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1160 | VNInfo *RHSValNoInfo = NULL; |
Evan Cheng | f3bb2e6 | 2007-09-05 21:46:51 +0000 | [diff] [blame] | 1161 | VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1162 | unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0); |
| 1163 | if ((RHSSrcReg == 0 || RHSSrcReg != LHS.reg)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1164 | // If RHS is not defined as a copy from the LHS, we can use simpler and |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1165 | // faster checks to see if the live ranges are coalescable. This joiner |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1166 | // can't swap the LHS/RHS intervals though. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1167 | if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1168 | return SimpleJoin(LHS, RHS); |
| 1169 | } else { |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1170 | RHSValNoInfo = RHSValNoInfo0; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1171 | } |
| 1172 | } else { |
| 1173 | // It was defined as a copy from the LHS, find out what value # it is. |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1174 | RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1175 | RHSValID = RHSValNoInfo->id; |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1176 | RHSVal0DefinedFromLHS = RHSValID; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1177 | } |
| 1178 | |
| 1179 | LHSValNoAssignments.resize(LHS.getNumValNums(), -1); |
| 1180 | RHSValNoAssignments.resize(RHS.getNumValNums(), -1); |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1181 | NewVNInfo.resize(LHS.getNumValNums(), NULL); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1182 | |
| 1183 | // Okay, *all* of the values in LHS that are defined as a copy from RHS |
| 1184 | // should now get updated. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1185 | for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); |
| 1186 | i != e; ++i) { |
| 1187 | VNInfo *VNI = *i; |
| 1188 | unsigned VN = VNI->id; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1189 | if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) { |
| 1190 | if (LHSSrcReg != RHS.reg) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1191 | // If this is not a copy from the RHS, its value number will be |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1192 | // unmodified by the coalescing. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1193 | NewVNInfo[VN] = VNI; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1194 | LHSValNoAssignments[VN] = VN; |
| 1195 | } else if (RHSValID == -1) { |
| 1196 | // Otherwise, it is a copy from the RHS, and we don't already have a |
| 1197 | // value# for it. Keep the current value number, but remember it. |
| 1198 | LHSValNoAssignments[VN] = RHSValID = VN; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1199 | NewVNInfo[VN] = RHSValNoInfo; |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1200 | LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1201 | } else { |
| 1202 | // Otherwise, use the specified value #. |
| 1203 | LHSValNoAssignments[VN] = RHSValID; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1204 | if (VN == (unsigned)RHSValID) { // Else this val# is dead. |
| 1205 | NewVNInfo[VN] = RHSValNoInfo; |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1206 | LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0; |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1207 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1208 | } |
| 1209 | } else { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1210 | NewVNInfo[VN] = VNI; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1211 | LHSValNoAssignments[VN] = VN; |
| 1212 | } |
| 1213 | } |
| 1214 | |
| 1215 | assert(RHSValID != -1 && "Didn't find value #?"); |
| 1216 | RHSValNoAssignments[0] = RHSValID; |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1217 | if (RHSVal0DefinedFromLHS != -1) { |
Evan Cheng | 3430135 | 2007-09-01 02:03:17 +0000 | [diff] [blame] | 1218 | // This path doesn't go through ComputeUltimateVN so just set |
| 1219 | // it to anything. |
| 1220 | RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1; |
Evan Cheng | 4f8ff16 | 2007-08-11 00:59:19 +0000 | [diff] [blame] | 1221 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1222 | } else { |
| 1223 | // Loop over the value numbers of the LHS, seeing if any are defined from |
| 1224 | // the RHS. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1225 | for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); |
| 1226 | i != e; ++i) { |
| 1227 | VNInfo *VNI = *i; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1228 | if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy? |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1229 | continue; |
| 1230 | |
| 1231 | // DstReg is known to be a register in the LHS interval. If the src is |
| 1232 | // from the RHS interval, we can use its value #. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1233 | if (li_->getVNInfoSourceReg(VNI) != RHS.reg) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1234 | continue; |
| 1235 | |
| 1236 | // Figure out the value # from the RHS. |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 1237 | LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1238 | } |
| 1239 | |
| 1240 | // Loop over the value numbers of the RHS, seeing if any are defined from |
| 1241 | // the LHS. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1242 | for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end(); |
| 1243 | i != e; ++i) { |
| 1244 | VNInfo *VNI = *i; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1245 | if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy? |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1246 | continue; |
| 1247 | |
| 1248 | // DstReg is known to be a register in the RHS interval. If the src is |
| 1249 | // from the LHS interval, we can use its value #. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1250 | if (li_->getVNInfoSourceReg(VNI) != LHS.reg) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1251 | continue; |
| 1252 | |
| 1253 | // Figure out the value # from the LHS. |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 1254 | RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1255 | } |
| 1256 | |
| 1257 | LHSValNoAssignments.resize(LHS.getNumValNums(), -1); |
| 1258 | RHSValNoAssignments.resize(RHS.getNumValNums(), -1); |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1259 | NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1260 | |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1261 | for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); |
| 1262 | i != e; ++i) { |
| 1263 | VNInfo *VNI = *i; |
| 1264 | unsigned VN = VNI->id; |
| 1265 | if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1266 | continue; |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1267 | ComputeUltimateVN(VNI, NewVNInfo, |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1268 | LHSValsDefinedFromRHS, RHSValsDefinedFromLHS, |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1269 | LHSValNoAssignments, RHSValNoAssignments); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1270 | } |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1271 | for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end(); |
| 1272 | i != e; ++i) { |
| 1273 | VNInfo *VNI = *i; |
| 1274 | unsigned VN = VNI->id; |
| 1275 | if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1276 | continue; |
| 1277 | // If this value number isn't a copy from the LHS, it's a new number. |
Evan Cheng | c14b144 | 2007-08-31 08:04:17 +0000 | [diff] [blame] | 1278 | if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1279 | NewVNInfo.push_back(VNI); |
| 1280 | RHSValNoAssignments[VN] = NewVNInfo.size()-1; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1281 | continue; |
| 1282 | } |
| 1283 | |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1284 | ComputeUltimateVN(VNI, NewVNInfo, |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1285 | RHSValsDefinedFromLHS, LHSValsDefinedFromRHS, |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1286 | RHSValNoAssignments, LHSValNoAssignments); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1287 | } |
| 1288 | } |
| 1289 | |
| 1290 | // Armed with the mappings of LHS/RHS values to ultimate values, walk the |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1291 | // interval lists to see if these intervals are coalescable. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1292 | LiveInterval::const_iterator I = LHS.begin(); |
| 1293 | LiveInterval::const_iterator IE = LHS.end(); |
| 1294 | LiveInterval::const_iterator J = RHS.begin(); |
| 1295 | LiveInterval::const_iterator JE = RHS.end(); |
| 1296 | |
| 1297 | // Skip ahead until the first place of potential sharing. |
| 1298 | if (I->start < J->start) { |
| 1299 | I = std::upper_bound(I, IE, J->start); |
| 1300 | if (I != LHS.begin()) --I; |
| 1301 | } else if (J->start < I->start) { |
| 1302 | J = std::upper_bound(J, JE, I->start); |
| 1303 | if (J != RHS.begin()) --J; |
| 1304 | } |
| 1305 | |
| 1306 | while (1) { |
| 1307 | // Determine if these two live ranges overlap. |
| 1308 | bool Overlaps; |
| 1309 | if (I->start < J->start) { |
| 1310 | Overlaps = I->end > J->start; |
| 1311 | } else { |
| 1312 | Overlaps = J->end > I->start; |
| 1313 | } |
| 1314 | |
| 1315 | // If so, check value # info to determine if they are really different. |
| 1316 | if (Overlaps) { |
| 1317 | // If the live range overlap will map to the same value number in the |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1318 | // result liverange, we can still coalesce them. If not, we can't. |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1319 | if (LHSValNoAssignments[I->valno->id] != |
| 1320 | RHSValNoAssignments[J->valno->id]) |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1321 | return false; |
| 1322 | } |
| 1323 | |
| 1324 | if (I->end < J->end) { |
| 1325 | ++I; |
| 1326 | if (I == IE) break; |
| 1327 | } else { |
| 1328 | ++J; |
| 1329 | if (J == JE) break; |
| 1330 | } |
| 1331 | } |
| 1332 | |
Evan Cheng | 3472925 | 2007-10-14 10:08:34 +0000 | [diff] [blame] | 1333 | // Update kill info. Some live ranges are extended due to copy coalescing. |
| 1334 | for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(), |
| 1335 | E = LHSValsDefinedFromRHS.end(); I != E; ++I) { |
| 1336 | VNInfo *VNI = I->first; |
| 1337 | unsigned LHSValID = LHSValNoAssignments[VNI->id]; |
| 1338 | LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def); |
Evan Cheng | c3fc7d9 | 2007-11-29 09:49:23 +0000 | [diff] [blame] | 1339 | NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill; |
Evan Cheng | 3472925 | 2007-10-14 10:08:34 +0000 | [diff] [blame] | 1340 | RHS.addKills(NewVNInfo[LHSValID], VNI->kills); |
| 1341 | } |
| 1342 | |
| 1343 | // Update kill info. Some live ranges are extended due to copy coalescing. |
| 1344 | for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(), |
| 1345 | E = RHSValsDefinedFromLHS.end(); I != E; ++I) { |
| 1346 | VNInfo *VNI = I->first; |
| 1347 | unsigned RHSValID = RHSValNoAssignments[VNI->id]; |
| 1348 | LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def); |
Evan Cheng | c3fc7d9 | 2007-11-29 09:49:23 +0000 | [diff] [blame] | 1349 | NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill; |
Evan Cheng | 3472925 | 2007-10-14 10:08:34 +0000 | [diff] [blame] | 1350 | LHS.addKills(NewVNInfo[RHSValID], VNI->kills); |
| 1351 | } |
| 1352 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1353 | // If we get here, we know that we can coalesce the live ranges. Ask the |
| 1354 | // intervals to coalesce themselves now. |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 1355 | if ((RHS.ranges.size() > LHS.ranges.size() && |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1356 | TargetRegisterInfo::isVirtualRegister(LHS.reg)) || |
| 1357 | TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1358 | RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo); |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 1359 | Swapped = true; |
| 1360 | } else { |
Evan Cheng | 7ecb38b | 2007-08-29 20:45:00 +0000 | [diff] [blame] | 1361 | LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo); |
Evan Cheng | 1a66f0a | 2007-08-28 08:28:51 +0000 | [diff] [blame] | 1362 | Swapped = false; |
| 1363 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1364 | return true; |
| 1365 | } |
| 1366 | |
| 1367 | namespace { |
| 1368 | // DepthMBBCompare - Comparison predicate that sort first based on the loop |
| 1369 | // depth of the basic block (the unsigned), and then on the MBB number. |
| 1370 | struct DepthMBBCompare { |
| 1371 | typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; |
| 1372 | bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { |
| 1373 | if (LHS.first > RHS.first) return true; // Deeper loops first |
| 1374 | return LHS.first == RHS.first && |
| 1375 | LHS.second->getNumber() < RHS.second->getNumber(); |
| 1376 | } |
| 1377 | }; |
| 1378 | } |
| 1379 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1380 | /// getRepIntervalSize - Returns the size of the interval that represents the |
| 1381 | /// specified register. |
| 1382 | template<class SF> |
| 1383 | unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) { |
| 1384 | return Rc->getRepIntervalSize(Reg); |
| 1385 | } |
| 1386 | |
| 1387 | /// CopyRecSort::operator - Join priority queue sorting function. |
| 1388 | /// |
| 1389 | bool CopyRecSort::operator()(CopyRec left, CopyRec right) const { |
| 1390 | // Inner loops first. |
| 1391 | if (left.LoopDepth > right.LoopDepth) |
| 1392 | return false; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1393 | else if (left.LoopDepth == right.LoopDepth) |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1394 | if (left.isBackEdge && !right.isBackEdge) |
| 1395 | return false; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1396 | return true; |
| 1397 | } |
| 1398 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1399 | void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB, |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1400 | std::vector<CopyRec> &TryAgain) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1401 | DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n"; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1402 | |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1403 | std::vector<CopyRec> VirtCopies; |
| 1404 | std::vector<CopyRec> PhysCopies; |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 1405 | unsigned LoopDepth = loopInfo->getLoopDepth(MBB); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1406 | for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); |
| 1407 | MII != E;) { |
| 1408 | MachineInstr *Inst = MII++; |
| 1409 | |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1410 | // If this isn't a copy nor a extract_subreg, we can't join intervals. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1411 | unsigned SrcReg, DstReg; |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1412 | if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) { |
| 1413 | DstReg = Inst->getOperand(0).getReg(); |
| 1414 | SrcReg = Inst->getOperand(1).getReg(); |
| 1415 | } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) |
| 1416 | continue; |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1417 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1418 | bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); |
| 1419 | bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1420 | if (NewHeuristic) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1421 | JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg))); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1422 | } else { |
| 1423 | if (SrcIsPhys || DstIsPhys) |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1424 | PhysCopies.push_back(CopyRec(Inst, 0, false)); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1425 | else |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1426 | VirtCopies.push_back(CopyRec(Inst, 0, false)); |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1427 | } |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1428 | } |
| 1429 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1430 | if (NewHeuristic) |
| 1431 | return; |
| 1432 | |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1433 | // Try coalescing physical register + virtual register first. |
| 1434 | for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) { |
| 1435 | CopyRec &TheCopy = PhysCopies[i]; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1436 | bool Again = false; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1437 | if (!JoinCopy(TheCopy, Again)) |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1438 | if (Again) |
| 1439 | TryAgain.push_back(TheCopy); |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1440 | } |
| 1441 | for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) { |
| 1442 | CopyRec &TheCopy = VirtCopies[i]; |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1443 | bool Again = false; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1444 | if (!JoinCopy(TheCopy, Again)) |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1445 | if (Again) |
| 1446 | TryAgain.push_back(TheCopy); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1447 | } |
| 1448 | } |
| 1449 | |
| 1450 | void SimpleRegisterCoalescing::joinIntervals() { |
| 1451 | DOUT << "********** JOINING INTERVALS ***********\n"; |
| 1452 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1453 | if (NewHeuristic) |
| 1454 | JoinQueue = new JoinPriorityQueue<CopyRecSort>(this); |
| 1455 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1456 | std::vector<CopyRec> TryAgainList; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1457 | if (loopInfo->begin() == loopInfo->end()) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1458 | // If there are no loops in the function, join intervals in function order. |
| 1459 | for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); |
| 1460 | I != E; ++I) |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1461 | CopyCoalesceInMBB(I, TryAgainList); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1462 | } else { |
| 1463 | // Otherwise, join intervals in inner loops before other intervals. |
| 1464 | // Unfortunately we can't just iterate over loop hierarchy here because |
| 1465 | // there may be more MBB's than BB's. Collect MBB's for sorting. |
| 1466 | |
| 1467 | // Join intervals in the function prolog first. We want to join physical |
| 1468 | // registers with virtual registers before the intervals got too long. |
| 1469 | std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 1470 | for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){ |
| 1471 | MachineBasicBlock *MBB = I; |
| 1472 | MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I)); |
| 1473 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1474 | |
| 1475 | // Sort by loop depth. |
| 1476 | std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); |
| 1477 | |
| 1478 | // Finally, join intervals in loop nest order. |
| 1479 | for (unsigned i = 0, e = MBBs.size(); i != e; ++i) |
Evan Cheng | 8b0b874 | 2007-10-16 08:04:24 +0000 | [diff] [blame] | 1480 | CopyCoalesceInMBB(MBBs[i].second, TryAgainList); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1481 | } |
| 1482 | |
| 1483 | // Joining intervals can allow other intervals to be joined. Iteratively join |
| 1484 | // until we make no progress. |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1485 | if (NewHeuristic) { |
| 1486 | SmallVector<CopyRec, 16> TryAgain; |
| 1487 | bool ProgressMade = true; |
| 1488 | while (ProgressMade) { |
| 1489 | ProgressMade = false; |
| 1490 | while (!JoinQueue->empty()) { |
| 1491 | CopyRec R = JoinQueue->pop(); |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1492 | bool Again = false; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1493 | bool Success = JoinCopy(R, Again); |
| 1494 | if (Success) |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1495 | ProgressMade = true; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1496 | else if (Again) |
| 1497 | TryAgain.push_back(R); |
| 1498 | } |
| 1499 | |
| 1500 | if (ProgressMade) { |
| 1501 | while (!TryAgain.empty()) { |
| 1502 | JoinQueue->push(TryAgain.back()); |
| 1503 | TryAgain.pop_back(); |
| 1504 | } |
| 1505 | } |
| 1506 | } |
| 1507 | } else { |
| 1508 | bool ProgressMade = true; |
| 1509 | while (ProgressMade) { |
| 1510 | ProgressMade = false; |
| 1511 | |
| 1512 | for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) { |
| 1513 | CopyRec &TheCopy = TryAgainList[i]; |
| 1514 | if (TheCopy.MI) { |
| 1515 | bool Again = false; |
| 1516 | bool Success = JoinCopy(TheCopy, Again); |
| 1517 | if (Success || !Again) { |
| 1518 | TheCopy.MI = 0; // Mark this one as done. |
| 1519 | ProgressMade = true; |
| 1520 | } |
Evan Cheng | 0547bab | 2007-11-01 06:22:48 +0000 | [diff] [blame] | 1521 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1522 | } |
| 1523 | } |
| 1524 | } |
| 1525 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1526 | if (NewHeuristic) |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1527 | delete JoinQueue; |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1528 | } |
| 1529 | |
| 1530 | /// Return true if the two specified registers belong to different register |
| 1531 | /// classes. The registers may be either phys or virt regs. |
| 1532 | bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA, |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1533 | unsigned RegB) const { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1534 | |
| 1535 | // Get the register classes for the first reg. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1536 | if (TargetRegisterInfo::isPhysicalRegister(RegA)) { |
| 1537 | assert(TargetRegisterInfo::isVirtualRegister(RegB) && |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1538 | "Shouldn't consider two physregs!"); |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1539 | return !mri_->getRegClass(RegB)->contains(RegA); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1540 | } |
| 1541 | |
| 1542 | // Compare against the regclass for the second reg. |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1543 | const TargetRegisterClass *RegClass = mri_->getRegClass(RegA); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1544 | if (TargetRegisterInfo::isVirtualRegister(RegB)) |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1545 | return RegClass != mri_->getRegClass(RegB); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1546 | else |
| 1547 | return !RegClass->contains(RegB); |
| 1548 | } |
| 1549 | |
| 1550 | /// lastRegisterUse - Returns the last use of the specific register between |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1551 | /// cycles Start and End or NULL if there are no uses. |
| 1552 | MachineOperand * |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 1553 | SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1554 | unsigned Reg, unsigned &UseIdx) const{ |
| 1555 | UseIdx = 0; |
| 1556 | if (TargetRegisterInfo::isVirtualRegister(Reg)) { |
| 1557 | MachineOperand *LastUse = NULL; |
| 1558 | for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg), |
| 1559 | E = mri_->use_end(); I != E; ++I) { |
| 1560 | MachineOperand &Use = I.getOperand(); |
| 1561 | MachineInstr *UseMI = Use.getParent(); |
Evan Cheng | a2fb634 | 2008-03-25 02:02:19 +0000 | [diff] [blame] | 1562 | unsigned SrcReg, DstReg; |
| 1563 | if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg) && SrcReg == DstReg) |
| 1564 | // Ignore identity copies. |
| 1565 | continue; |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1566 | unsigned Idx = li_->getInstructionIndex(UseMI); |
| 1567 | if (Idx >= Start && Idx < End && Idx >= UseIdx) { |
| 1568 | LastUse = &Use; |
| 1569 | UseIdx = Idx; |
| 1570 | } |
| 1571 | } |
| 1572 | return LastUse; |
| 1573 | } |
| 1574 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1575 | int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM; |
| 1576 | int s = Start; |
| 1577 | while (e >= s) { |
| 1578 | // Skip deleted instructions |
| 1579 | MachineInstr *MI = li_->getInstructionFromIndex(e); |
| 1580 | while ((e - InstrSlots::NUM) >= s && !MI) { |
| 1581 | e -= InstrSlots::NUM; |
| 1582 | MI = li_->getInstructionFromIndex(e); |
| 1583 | } |
| 1584 | if (e < s || MI == NULL) |
| 1585 | return NULL; |
| 1586 | |
Evan Cheng | a2fb634 | 2008-03-25 02:02:19 +0000 | [diff] [blame] | 1587 | // Ignore identity copies. |
| 1588 | unsigned SrcReg, DstReg; |
| 1589 | if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg)) |
| 1590 | for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { |
| 1591 | MachineOperand &Use = MI->getOperand(i); |
| 1592 | if (Use.isRegister() && Use.isUse() && Use.getReg() && |
| 1593 | tri_->regsOverlap(Use.getReg(), Reg)) { |
| 1594 | UseIdx = e; |
| 1595 | return &Use; |
| 1596 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1597 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1598 | |
| 1599 | e -= InstrSlots::NUM; |
| 1600 | } |
| 1601 | |
| 1602 | return NULL; |
| 1603 | } |
| 1604 | |
| 1605 | |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1606 | void SimpleRegisterCoalescing::printRegName(unsigned reg) const { |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1607 | if (TargetRegisterInfo::isPhysicalRegister(reg)) |
Bill Wendling | e6d088a | 2008-02-26 21:47:57 +0000 | [diff] [blame] | 1608 | cerr << tri_->getName(reg); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1609 | else |
| 1610 | cerr << "%reg" << reg; |
| 1611 | } |
| 1612 | |
| 1613 | void SimpleRegisterCoalescing::releaseMemory() { |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1614 | JoinedCopies.clear(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1615 | } |
| 1616 | |
| 1617 | static bool isZeroLengthInterval(LiveInterval *li) { |
| 1618 | for (LiveInterval::Ranges::const_iterator |
| 1619 | i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i) |
| 1620 | if (i->end - i->start > LiveIntervals::InstrSlots::NUM) |
| 1621 | return false; |
| 1622 | return true; |
| 1623 | } |
| 1624 | |
| 1625 | bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { |
| 1626 | mf_ = &fn; |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 1627 | mri_ = &fn.getRegInfo(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1628 | tm_ = &fn.getTarget(); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1629 | tri_ = tm_->getRegisterInfo(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1630 | tii_ = tm_->getInstrInfo(); |
| 1631 | li_ = &getAnalysis<LiveIntervals>(); |
| 1632 | lv_ = &getAnalysis<LiveVariables>(); |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 1633 | loopInfo = &getAnalysis<MachineLoopInfo>(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1634 | |
| 1635 | DOUT << "********** SIMPLE REGISTER COALESCING **********\n" |
| 1636 | << "********** Function: " |
| 1637 | << ((Value*)mf_->getFunction())->getName() << '\n'; |
| 1638 | |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1639 | allocatableRegs_ = tri_->getAllocatableSet(fn); |
| 1640 | for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(), |
| 1641 | E = tri_->regclass_end(); I != E; ++I) |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 1642 | allocatableRCRegs_.insert(std::make_pair(*I, |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1643 | tri_->getAllocatableSet(fn, *I))); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1644 | |
Gabor Greif | e510b3a | 2007-07-09 12:00:59 +0000 | [diff] [blame] | 1645 | // Join (coalesce) intervals if requested. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1646 | if (EnableJoining) { |
| 1647 | joinIntervals(); |
| 1648 | DOUT << "********** INTERVALS POST JOINING **********\n"; |
Bill Wendling | 2674d71 | 2008-01-04 08:59:18 +0000 | [diff] [blame] | 1649 | for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){ |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1650 | I->second.print(DOUT, tri_); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1651 | DOUT << "\n"; |
| 1652 | } |
Evan Cheng | 32dfbea | 2007-10-12 08:50:34 +0000 | [diff] [blame] | 1653 | |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1654 | // Delete all coalesced copies. |
| 1655 | for (SmallPtrSet<MachineInstr*,32>::iterator I = JoinedCopies.begin(), |
| 1656 | E = JoinedCopies.end(); I != E; ++I) { |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 1657 | MachineInstr *CopyMI = *I; |
| 1658 | unsigned SrcReg, DstReg; |
| 1659 | tii_->isMoveInstr(*CopyMI, SrcReg, DstReg); |
| 1660 | if (CopyMI->registerDefIsDead(DstReg)) { |
| 1661 | LiveInterval &li = li_->getInterval(DstReg); |
| 1662 | ShortenDeadCopySrcLiveRange(li, CopyMI); |
| 1663 | ShortenDeadCopyLiveRange(li, CopyMI); |
| 1664 | } |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1665 | li_->RemoveMachineInstrFromMaps(*I); |
| 1666 | (*I)->eraseFromParent(); |
Evan Cheng | 7007143 | 2008-02-13 03:01:43 +0000 | [diff] [blame] | 1667 | ++numPeep; |
Evan Cheng | 8fc9a10 | 2007-11-06 08:52:21 +0000 | [diff] [blame] | 1668 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1669 | } |
| 1670 | |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1671 | // Perform a final pass over the instructions and compute spill weights |
| 1672 | // and remove identity moves. |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1673 | for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); |
| 1674 | mbbi != mbbe; ++mbbi) { |
| 1675 | MachineBasicBlock* mbb = mbbi; |
Evan Cheng | 22f07ff | 2007-12-11 02:09:15 +0000 | [diff] [blame] | 1676 | unsigned loopDepth = loopInfo->getLoopDepth(mbb); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1677 | |
| 1678 | for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); |
| 1679 | mii != mie; ) { |
| 1680 | // if the move will be an identity move delete it |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1681 | unsigned srcReg, dstReg; |
| 1682 | if (tii_->isMoveInstr(*mii, srcReg, dstReg) && srcReg == dstReg) { |
Evan Cheng | 3c88d74 | 2008-03-18 08:26:47 +0000 | [diff] [blame] | 1683 | if (li_->hasInterval(srcReg)) { |
| 1684 | LiveInterval &RegInt = li_->getInterval(srcReg); |
| 1685 | // If def of this move instruction is dead, remove its live range |
| 1686 | // from the dstination register's live interval. |
| 1687 | if (mii->registerDefIsDead(dstReg)) { |
| 1688 | ShortenDeadCopySrcLiveRange(RegInt, mii); |
| 1689 | ShortenDeadCopyLiveRange(RegInt, mii); |
| 1690 | } |
| 1691 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1692 | li_->RemoveMachineInstrFromMaps(mii); |
| 1693 | mii = mbbi->erase(mii); |
| 1694 | ++numPeep; |
| 1695 | } else { |
| 1696 | SmallSet<unsigned, 4> UniqueUses; |
| 1697 | for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { |
| 1698 | const MachineOperand &mop = mii->getOperand(i); |
| 1699 | if (mop.isRegister() && mop.getReg() && |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1700 | TargetRegisterInfo::isVirtualRegister(mop.getReg())) { |
Evan Cheng | c8d044e | 2008-02-15 18:24:29 +0000 | [diff] [blame] | 1701 | unsigned reg = mop.getReg(); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1702 | // Multiple uses of reg by the same instruction. It should not |
| 1703 | // contribute to spill weight again. |
| 1704 | if (UniqueUses.count(reg) != 0) |
| 1705 | continue; |
| 1706 | LiveInterval &RegInt = li_->getInterval(reg); |
Evan Cheng | 81a0382 | 2007-11-17 00:40:40 +0000 | [diff] [blame] | 1707 | RegInt.weight += |
| 1708 | li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth); |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1709 | UniqueUses.insert(reg); |
| 1710 | } |
| 1711 | } |
| 1712 | ++mii; |
| 1713 | } |
| 1714 | } |
| 1715 | } |
| 1716 | |
| 1717 | for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) { |
| 1718 | LiveInterval &LI = I->second; |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 1719 | if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1720 | // If the live interval length is essentially zero, i.e. in every live |
| 1721 | // range the use follows def immediately, it doesn't make sense to spill |
| 1722 | // it and hope it will be easier to allocate for this li. |
| 1723 | if (isZeroLengthInterval(&LI)) |
| 1724 | LI.weight = HUGE_VALF; |
Evan Cheng | 5ef3a04 | 2007-12-06 00:01:56 +0000 | [diff] [blame] | 1725 | else { |
| 1726 | bool isLoad = false; |
Evan Cheng | 63a18c4 | 2008-02-09 08:36:28 +0000 | [diff] [blame] | 1727 | if (li_->isReMaterializable(LI, isLoad)) { |
Evan Cheng | 5ef3a04 | 2007-12-06 00:01:56 +0000 | [diff] [blame] | 1728 | // If all of the definitions of the interval are re-materializable, |
| 1729 | // it is a preferred candidate for spilling. If non of the defs are |
| 1730 | // loads, then it's potentially very cheap to re-materialize. |
| 1731 | // FIXME: this gets much more complicated once we support non-trivial |
| 1732 | // re-materialization. |
| 1733 | if (isLoad) |
| 1734 | LI.weight *= 0.9F; |
| 1735 | else |
| 1736 | LI.weight *= 0.5F; |
| 1737 | } |
| 1738 | } |
David Greene | 2513330 | 2007-06-08 17:18:56 +0000 | [diff] [blame] | 1739 | |
| 1740 | // Slightly prefer live interval that has been assigned a preferred reg. |
| 1741 | if (LI.preference) |
| 1742 | LI.weight *= 1.01F; |
| 1743 | |
| 1744 | // Divide the weight of the interval by its size. This encourages |
| 1745 | // spilling of intervals that are large and have few uses, and |
| 1746 | // discourages spilling of small intervals with many uses. |
| 1747 | LI.weight /= LI.getSize(); |
| 1748 | } |
| 1749 | } |
| 1750 | |
| 1751 | DEBUG(dump()); |
| 1752 | return true; |
| 1753 | } |
| 1754 | |
| 1755 | /// print - Implement the dump method. |
| 1756 | void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const { |
| 1757 | li_->print(O, m); |
| 1758 | } |
David Greene | 2c17c4d | 2007-09-06 16:18:45 +0000 | [diff] [blame] | 1759 | |
| 1760 | RegisterCoalescer* llvm::createSimpleRegisterCoalescer() { |
| 1761 | return new SimpleRegisterCoalescing(); |
| 1762 | } |
| 1763 | |
| 1764 | // Make sure that anything that uses RegisterCoalescer pulls in this file... |
| 1765 | DEFINING_FILE_FOR(SimpleRegisterCoalescing) |