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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 0d65a1fca37178c63dcc067077bfec56104f3abf / . / docs / CommandGuide / llc.pod
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Brian Gaekee993d202004-05-14 19:50:33 +0000[diff] [blame]1=pod
2
3=head1 NAME
4
5llc - LLVM static compiler
6
7=head1 SYNOPSIS
8
Misha Brukmanc08937a2004-07-02 16:06:19 +0000[diff] [blame]9B<llc> [I<options>] [I<filename>]
Brian Gaekee993d202004-05-14 19:50:33 +0000[diff] [blame]10
11=head1 DESCRIPTION
12
13The B<llc> command compiles LLVM bytecode into assembly language for a
14specified architecture. The assembly language output can then be passed through
15a native assembler and linker to generate native code.
16
17The choice of architecture for the output assembly code is determined as
18follows, by attempting to satisfy each of the following rules in turn (first
19one wins):
20
21=over
22
23=item *
24
25If the user has specified an architecture with the -m option, use that
26architecture.
27
28=item *
29
30Examine the input LLVM bytecode file: if it is little endian and has a
31pointer size of 32 bits, select the Intel IA-32 architecture. If it is big
32endian and has a pointer size of 64 bits, select the SparcV9 architecture.
33
34=item *
35
36If B<llc> was compiled on an architecture for which it can generate code, select
37the architecture upon which B<llc> was compiled.
38
39=item *
40
41Exit with an error message telling the user to specify the output
42architecture explicitly.
43
44=back
45
46=head1 OPTIONS
47
48If I<filename> is - or omitted, B<llc> reads LLVM bytecode from standard input.
49Otherwise, it will read LLVM bytecode from I<filename>.
50
51If the B<-o> option is omitted, then B<llc> will send its output to standard
52output if the input is from standard input. If the B<-o> option specifies -,
53then the output will also be sent to standard output.
54
55If no B<-o> option is specified and an input file other than - is specified,
56then B<llc> creates the output filename by taking the input filename,
57removing any existing F<.bc> extension, and adding a F<.s> suffix.
58
59Other B<llc> options are as follows:
60
61=over
62
63=item B<-f>
64
65Overwrite output files. By default, B<llc> will refuse to overwrite
66an output file which already exists.
67
68=item B<-march>=I<arch>
69
70Specify the architecture for which to generate assembly. Valid
71architectures are:
72
73=over
74
75=item I<x86>
76
77Intel IA-32 (Pentium and above)
78
Misha Brukman0d65a1f2004-11-15 20:22:49 +0000[diff] [blame^]79=item I<ppc32>
80
8132-bit PowerPC (MacOS X, 32-bit ABI)
82
Brian Gaekee993d202004-05-14 19:50:33 +0000[diff] [blame]83=item I<sparcv9>
84
8564-bit SPARC V9
86
87=item I<c>
88
89Emit C code, not assembly
90
91=back
92
93=item B<-enable-correct-eh-support>
94
95Instruct the B<-lowerinvoke> pass to insert code for correct exception handling
96support. This is expensive and is by default omitted for efficiency.
97
98=item B<-help>
99
100Print a summary of command line options.
101
102=item B<-stats>
103
104Print statistics recorded by code-generation passes.
105
106=item B<-time-passes>
107
108Record the amount of time needed for each pass and print a report to standard
109error.
110
111=back
112
113=head2 Intel IA-32-specific Options
114
115=over
116
117=item B<--disable-fp-elim>
118
119Disable frame pointer elimination optimization.
120
121=item B<--disable-pattern-isel>
122
123Use the 'simple' X86 instruction selector (the default).
124
125=item B<--print-machineinstrs>
126
127Print generated machine code.
128
129=item B<--regalloc>=I<allocator>
130
131Specify the register allocator to use. The default I<allocator> is I<local>.
132Valid register allocators are:
133
134=over
135
136=item I<simple>
137
138Very simple "always spill" register allocator
139
140=item I<local>
141
142Local register allocator
143
144=item I<linearscan>
145
Alkis Evlogimenosc8dec2c2004-07-21 08:18:50 +0000[diff] [blame]146Linear scan global register allocator
Brian Gaekee993d202004-05-14 19:50:33 +0000[diff] [blame]147
Misha Brukman1e635c32004-07-21 12:53:14 +0000[diff] [blame]148=item I<iterativescan>
Alkis Evlogimenos910d0d62004-07-21 08:24:35 +0000[diff] [blame]149
150Iterative scan global register allocator
151
Brian Gaekee993d202004-05-14 19:50:33 +0000[diff] [blame]152=back
153
154=item B<--spiller>=I<spiller>
155
156Specify the spiller to use for register allocators that support it. Currently
157this option is used only by the linear scan register allocator. The default
158I<spiller> is I<local>. Valid spillers are:
159
160=over
161
162=item I<simple>
163
164Simple spiller
165
166=item I<local>
167
168Local spiller
169
170=back
171
172=back
173
174=head2 SPARCV9-specific Options
175
176=over
177
178=item B<--disable-peephole>
179
180Disable peephole optimization pass.
181
182=item B<--disable-sched>
183
184Disable local scheduling pass.
185
186=item B<--disable-strip>
187
188The Sparc backend embeds the LLVM bytecode into the assembly output. This
189option requests that symbol names be retained; by default, they are stripped out.
190
191=item B<--enable-maps>
192
193Emit LLVM-to-machine code mapping information into the assembly output.
194
195=back
196
197=head1 EXIT STATUS
198
199If B<llc> succeeds, it will exit with 0. Otherwise, if an error occurs,
200it will exit with a non-zero value.
201
202=head1 SEE ALSO
203
Misha Brukmanc08937a2004-07-02 16:06:19 +0000[diff] [blame]204L<lli|lli>
Brian Gaekee993d202004-05-14 19:50:33 +0000[diff] [blame]205
206=head1 AUTHORS
207
208Maintained by the LLVM Team (L<http://llvm.cs.uiuc.edu>).
209
210=cut