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Evan Cheng94214702011-07-01 20:45:01 +00001//===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "llvm/MC/MCSubtargetInfo.h"
11#include "llvm/MC/MCInstrItineraries.h"
12#include "llvm/MC/SubtargetFeature.h"
13#include "llvm/ADT/StringRef.h"
Evan Cheng59ee62d2011-07-11 03:57:24 +000014#include "llvm/ADT/Triple.h"
Evan Cheng94214702011-07-01 20:45:01 +000015#include "llvm/Support/raw_ostream.h"
16#include <algorithm>
17
18using namespace llvm;
19
Andrew Trick2661b412012-07-07 04:00:00 +000020MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors.
21
Evan Cheng59ee62d2011-07-11 03:57:24 +000022void
23MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
24 const SubtargetFeatureKV *PF,
25 const SubtargetFeatureKV *PD,
Andrew Trick2661b412012-07-07 04:00:00 +000026 const SubtargetInfoKV *ProcSched,
Andrew Trickdb7afac2012-09-17 22:18:55 +000027 const MCWriteProcResEntry *WPR,
28 const MCWriteLatencyEntry *WL,
29 const MCReadAdvanceEntry *RA,
Evan Cheng59ee62d2011-07-11 03:57:24 +000030 const InstrStage *IS,
31 const unsigned *OC,
32 const unsigned *FP,
33 unsigned NF, unsigned NP) {
34 TargetTriple = TT;
Evan Cheng0ddff1b2011-07-07 07:07:08 +000035 ProcFeatures = PF;
36 ProcDesc = PD;
Andrew Trick72d048b2012-09-14 20:26:41 +000037 ProcSchedModels = ProcSched;
Andrew Trickdb7afac2012-09-17 22:18:55 +000038 WriteProcResTable = WPR;
39 WriteLatencyTable = WL;
40 ReadAdvanceTable = RA;
41
Evan Cheng0ddff1b2011-07-07 07:07:08 +000042 Stages = IS;
43 OperandCycles = OC;
Andrew Tricka11a6282012-07-07 03:59:48 +000044 ForwardingPaths = FP;
Evan Cheng0ddff1b2011-07-07 07:07:08 +000045 NumFeatures = NF;
46 NumProcs = NP;
47
48 SubtargetFeatures Features(FS);
49 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
50 ProcFeatures, NumFeatures);
Evan Cheng0ddff1b2011-07-07 07:07:08 +000051
Andrew Trickdb7afac2012-09-17 22:18:55 +000052 CPUSchedModel = getSchedModelForCPU(CPU);
53}
Evan Cheng0ddff1b2011-07-07 07:07:08 +000054
55/// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
56/// feature string) and recompute feature bits.
57uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) {
58 SubtargetFeatures Features(FS);
59 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
60 ProcFeatures, NumFeatures);
61 return FeatureBits;
62}
63
Evan Chengffc0e732011-07-09 05:47:46 +000064/// ToggleFeature - Toggle a feature and returns the re-computed feature
65/// bits. This version does not change the implied bits.
66uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
67 FeatureBits ^= FB;
68 return FeatureBits;
69}
70
71/// ToggleFeature - Toggle a feature and returns the re-computed feature
72/// bits. This version will also change all implied bits.
73uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
74 SubtargetFeatures Features;
75 FeatureBits = Features.ToggleFeature(FeatureBits, FS,
76 ProcFeatures, NumFeatures);
77 return FeatureBits;
78}
79
80
Roman Divacky98eb98b2012-09-05 21:43:57 +000081const MCSchedModel *
Andrew Trick2661b412012-07-07 04:00:00 +000082MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
Andrew Trick72d048b2012-09-14 20:26:41 +000083 assert(ProcSchedModels && "Processor machine model not available!");
Evan Cheng94214702011-07-01 20:45:01 +000084
85#ifndef NDEBUG
86 for (size_t i = 1; i < NumProcs; i++) {
Andrew Trick72d048b2012-09-14 20:26:41 +000087 assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 &&
Andrew Trick2661b412012-07-07 04:00:00 +000088 "Processor machine model table is not sorted");
Evan Cheng94214702011-07-01 20:45:01 +000089 }
90#endif
91
92 // Find entry
93 SubtargetInfoKV KV;
94 KV.Key = CPU.data();
95 const SubtargetInfoKV *Found =
Andrew Trick72d048b2012-09-14 20:26:41 +000096 std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, KV);
97 if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) {
Evan Cheng94214702011-07-01 20:45:01 +000098 errs() << "'" << CPU
99 << "' is not a recognized processor for this target"
100 << " (ignoring processor)\n";
Andrew Trick2661b412012-07-07 04:00:00 +0000101 return &MCSchedModel::DefaultSchedModel;
Evan Cheng94214702011-07-01 20:45:01 +0000102 }
Andrew Trick2661b412012-07-07 04:00:00 +0000103 assert(Found->Value && "Missing processor SchedModel value");
Roman Divacky98eb98b2012-09-05 21:43:57 +0000104 return (const MCSchedModel *)Found->Value;
Andrew Trick2661b412012-07-07 04:00:00 +0000105}
Evan Cheng94214702011-07-01 20:45:01 +0000106
Andrew Trick2661b412012-07-07 04:00:00 +0000107InstrItineraryData
108MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
Roman Divacky98eb98b2012-09-05 21:43:57 +0000109 const MCSchedModel *SchedModel = getSchedModelForCPU(CPU);
Andrew Trick2661b412012-07-07 04:00:00 +0000110 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
Evan Cheng94214702011-07-01 20:45:01 +0000111}
Andrew Trick99ab6c62012-09-14 20:26:46 +0000112
113/// Initialize an InstrItineraryData instance.
114void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
115 InstrItins =
Andrew Trick12886db2012-09-17 22:19:08 +0000116 InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths);
Andrew Trick99ab6c62012-09-14 20:26:46 +0000117}