Evan Cheng | 9421470 | 2011-07-01 20:45:01 +0000 | [diff] [blame] | 1 | //===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | #include "llvm/MC/MCSubtargetInfo.h" |
| 11 | #include "llvm/MC/MCInstrItineraries.h" |
| 12 | #include "llvm/MC/SubtargetFeature.h" |
| 13 | #include "llvm/ADT/StringRef.h" |
Evan Cheng | 59ee62d | 2011-07-11 03:57:24 +0000 | [diff] [blame] | 14 | #include "llvm/ADT/Triple.h" |
Evan Cheng | 9421470 | 2011-07-01 20:45:01 +0000 | [diff] [blame] | 15 | #include "llvm/Support/raw_ostream.h" |
| 16 | #include <algorithm> |
| 17 | |
| 18 | using namespace llvm; |
| 19 | |
Andrew Trick | 2661b41 | 2012-07-07 04:00:00 +0000 | [diff] [blame] | 20 | MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors. |
| 21 | |
Evan Cheng | 59ee62d | 2011-07-11 03:57:24 +0000 | [diff] [blame] | 22 | void |
| 23 | MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, |
| 24 | const SubtargetFeatureKV *PF, |
| 25 | const SubtargetFeatureKV *PD, |
Andrew Trick | 2661b41 | 2012-07-07 04:00:00 +0000 | [diff] [blame] | 26 | const SubtargetInfoKV *ProcSched, |
Andrew Trick | db7afac | 2012-09-17 22:18:55 +0000 | [diff] [blame] | 27 | const MCWriteProcResEntry *WPR, |
| 28 | const MCWriteLatencyEntry *WL, |
| 29 | const MCReadAdvanceEntry *RA, |
Evan Cheng | 59ee62d | 2011-07-11 03:57:24 +0000 | [diff] [blame] | 30 | const InstrStage *IS, |
| 31 | const unsigned *OC, |
| 32 | const unsigned *FP, |
| 33 | unsigned NF, unsigned NP) { |
| 34 | TargetTriple = TT; |
Evan Cheng | 0ddff1b | 2011-07-07 07:07:08 +0000 | [diff] [blame] | 35 | ProcFeatures = PF; |
| 36 | ProcDesc = PD; |
Andrew Trick | 72d048b | 2012-09-14 20:26:41 +0000 | [diff] [blame] | 37 | ProcSchedModels = ProcSched; |
Andrew Trick | db7afac | 2012-09-17 22:18:55 +0000 | [diff] [blame] | 38 | WriteProcResTable = WPR; |
| 39 | WriteLatencyTable = WL; |
| 40 | ReadAdvanceTable = RA; |
| 41 | |
Evan Cheng | 0ddff1b | 2011-07-07 07:07:08 +0000 | [diff] [blame] | 42 | Stages = IS; |
| 43 | OperandCycles = OC; |
Andrew Trick | a11a628 | 2012-07-07 03:59:48 +0000 | [diff] [blame] | 44 | ForwardingPaths = FP; |
Evan Cheng | 0ddff1b | 2011-07-07 07:07:08 +0000 | [diff] [blame] | 45 | NumFeatures = NF; |
| 46 | NumProcs = NP; |
| 47 | |
| 48 | SubtargetFeatures Features(FS); |
| 49 | FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs, |
| 50 | ProcFeatures, NumFeatures); |
Evan Cheng | 0ddff1b | 2011-07-07 07:07:08 +0000 | [diff] [blame] | 51 | |
Andrew Trick | db7afac | 2012-09-17 22:18:55 +0000 | [diff] [blame] | 52 | CPUSchedModel = getSchedModelForCPU(CPU); |
| 53 | } |
Evan Cheng | 0ddff1b | 2011-07-07 07:07:08 +0000 | [diff] [blame] | 54 | |
| 55 | /// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with |
| 56 | /// feature string) and recompute feature bits. |
| 57 | uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) { |
| 58 | SubtargetFeatures Features(FS); |
| 59 | FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs, |
| 60 | ProcFeatures, NumFeatures); |
| 61 | return FeatureBits; |
| 62 | } |
| 63 | |
Evan Cheng | ffc0e73 | 2011-07-09 05:47:46 +0000 | [diff] [blame] | 64 | /// ToggleFeature - Toggle a feature and returns the re-computed feature |
| 65 | /// bits. This version does not change the implied bits. |
| 66 | uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) { |
| 67 | FeatureBits ^= FB; |
| 68 | return FeatureBits; |
| 69 | } |
| 70 | |
| 71 | /// ToggleFeature - Toggle a feature and returns the re-computed feature |
| 72 | /// bits. This version will also change all implied bits. |
| 73 | uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) { |
| 74 | SubtargetFeatures Features; |
| 75 | FeatureBits = Features.ToggleFeature(FeatureBits, FS, |
| 76 | ProcFeatures, NumFeatures); |
| 77 | return FeatureBits; |
| 78 | } |
| 79 | |
| 80 | |
Roman Divacky | 98eb98b | 2012-09-05 21:43:57 +0000 | [diff] [blame] | 81 | const MCSchedModel * |
Andrew Trick | 2661b41 | 2012-07-07 04:00:00 +0000 | [diff] [blame] | 82 | MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const { |
Andrew Trick | 72d048b | 2012-09-14 20:26:41 +0000 | [diff] [blame] | 83 | assert(ProcSchedModels && "Processor machine model not available!"); |
Evan Cheng | 9421470 | 2011-07-01 20:45:01 +0000 | [diff] [blame] | 84 | |
| 85 | #ifndef NDEBUG |
| 86 | for (size_t i = 1; i < NumProcs; i++) { |
Andrew Trick | 72d048b | 2012-09-14 20:26:41 +0000 | [diff] [blame] | 87 | assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 && |
Andrew Trick | 2661b41 | 2012-07-07 04:00:00 +0000 | [diff] [blame] | 88 | "Processor machine model table is not sorted"); |
Evan Cheng | 9421470 | 2011-07-01 20:45:01 +0000 | [diff] [blame] | 89 | } |
| 90 | #endif |
| 91 | |
| 92 | // Find entry |
| 93 | SubtargetInfoKV KV; |
| 94 | KV.Key = CPU.data(); |
| 95 | const SubtargetInfoKV *Found = |
Andrew Trick | 72d048b | 2012-09-14 20:26:41 +0000 | [diff] [blame] | 96 | std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, KV); |
| 97 | if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) { |
Evan Cheng | 9421470 | 2011-07-01 20:45:01 +0000 | [diff] [blame] | 98 | errs() << "'" << CPU |
| 99 | << "' is not a recognized processor for this target" |
| 100 | << " (ignoring processor)\n"; |
Andrew Trick | 2661b41 | 2012-07-07 04:00:00 +0000 | [diff] [blame] | 101 | return &MCSchedModel::DefaultSchedModel; |
Evan Cheng | 9421470 | 2011-07-01 20:45:01 +0000 | [diff] [blame] | 102 | } |
Andrew Trick | 2661b41 | 2012-07-07 04:00:00 +0000 | [diff] [blame] | 103 | assert(Found->Value && "Missing processor SchedModel value"); |
Roman Divacky | 98eb98b | 2012-09-05 21:43:57 +0000 | [diff] [blame] | 104 | return (const MCSchedModel *)Found->Value; |
Andrew Trick | 2661b41 | 2012-07-07 04:00:00 +0000 | [diff] [blame] | 105 | } |
Evan Cheng | 9421470 | 2011-07-01 20:45:01 +0000 | [diff] [blame] | 106 | |
Andrew Trick | 2661b41 | 2012-07-07 04:00:00 +0000 | [diff] [blame] | 107 | InstrItineraryData |
| 108 | MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const { |
Roman Divacky | 98eb98b | 2012-09-05 21:43:57 +0000 | [diff] [blame] | 109 | const MCSchedModel *SchedModel = getSchedModelForCPU(CPU); |
Andrew Trick | 2661b41 | 2012-07-07 04:00:00 +0000 | [diff] [blame] | 110 | return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths); |
Evan Cheng | 9421470 | 2011-07-01 20:45:01 +0000 | [diff] [blame] | 111 | } |
Andrew Trick | 99ab6c6 | 2012-09-14 20:26:46 +0000 | [diff] [blame] | 112 | |
| 113 | /// Initialize an InstrItineraryData instance. |
| 114 | void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const { |
| 115 | InstrItins = |
Andrew Trick | 12886db | 2012-09-17 22:19:08 +0000 | [diff] [blame^] | 116 | InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths); |
Andrew Trick | 99ab6c6 | 2012-09-14 20:26:46 +0000 | [diff] [blame] | 117 | } |