| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 1 | ##===- lib/Target/PowerPC/Makefile -------------------------*- Makefile -*-===## |
| 2 | # |
| 3 | # The LLVM Compiler Infrastructure |
| 4 | # |
| 5 | # This file was developed by the LLVM research group and is distributed under |
| 6 | # the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | # |
| 8 | ##===----------------------------------------------------------------------===## |
| 9 | LEVEL = ../../.. |
| Chris Lattner | 017fdcb | 2004-07-15 02:33:38 +0000 | [diff] [blame] | 10 | LIBRARYNAME = powerpc |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 11 | include $(LEVEL)/Makefile.common |
| 12 | |
| Misha Brukman | 2f94786 | 2004-08-05 18:34:15 +0000 | [diff] [blame] | 13 | TARGET = PowerPC |
| 14 | |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 15 | # Make sure that tblgen is run, first thing. |
| 16 | $(SourceDepend): PowerPCGenRegisterInfo.h.inc PowerPCGenRegisterNames.inc \ |
| 17 | PowerPCGenRegisterInfo.inc PowerPCGenInstrNames.inc \ |
| Nate Begeman | 14d89d6 | 2004-08-14 22:06:38 +0000 | [diff] [blame^] | 18 | PowerPCGenInstrInfo.inc PowerPCGenCodeEmitter.inc \ |
| 19 | PowerPCGenAsmWriter.inc |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 20 | |
| Misha Brukman | 2f94786 | 2004-08-05 18:34:15 +0000 | [diff] [blame] | 21 | TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \ |
| 22 | $(SourceDir)/../Target.td |
| 23 | |
| 24 | $(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN) |
| 25 | @echo "Building $(TARGET).td register names with tblgen" |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 26 | $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@ |
| 27 | |
| Misha Brukman | 2f94786 | 2004-08-05 18:34:15 +0000 | [diff] [blame] | 28 | $(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN) |
| 29 | @echo "Building $(TARGET).td register information header with tblgen" |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 30 | $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@ |
| 31 | |
| Misha Brukman | 2f94786 | 2004-08-05 18:34:15 +0000 | [diff] [blame] | 32 | $(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN) |
| 33 | @echo "Building $(TARGET).td register information implementation with tblgen" |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 34 | $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@ |
| 35 | |
| Misha Brukman | 2f94786 | 2004-08-05 18:34:15 +0000 | [diff] [blame] | 36 | $(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN) |
| 37 | @echo "Building $(TARGET).td instruction names with tblgen" |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 38 | $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@ |
| 39 | |
| Misha Brukman | 2f94786 | 2004-08-05 18:34:15 +0000 | [diff] [blame] | 40 | $(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN) |
| 41 | @echo "Building $(TARGET).td instruction information with tblgen" |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 42 | $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@ |
| 43 | |
| Misha Brukman | f588548 | 2004-08-09 17:24:32 +0000 | [diff] [blame] | 44 | $(TARGET)GenCodeEmitter.inc:: $(TDFILES) $(TBLGEN) |
| 45 | @echo "Building $(TARGET).td code emitter" |
| 46 | $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@ |
| 47 | |
| Nate Begeman | 14d89d6 | 2004-08-14 22:06:38 +0000 | [diff] [blame^] | 48 | $(TARGET)GenAsmWriter.inc:: $(TDFILES) $(TBLGEN) |
| 49 | @echo "Building $(TARGET).td assembly writer with tblgen" |
| 50 | $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-asm-writer -o $@ |
| 51 | |
| Misha Brukman | 5dfe3a9 | 2004-06-21 16:55:25 +0000 | [diff] [blame] | 52 | clean:: |
| 53 | $(VERB) rm -f *.inc |