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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 20b10abf4e88ca532810fbf749b029ce582d6793 / . / test / CodeGen / SPARC / 2011-01-11-CC.ll
blob: 0cb864a7d5d6aa387dfc3e3cb945f3e03ad37b85 [file] [log] [blame]
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]1; RUN: llc -march=sparc <%s | FileCheck %s -check-prefix=V8
2; RUN: llc -march=sparc -mattr=v9 <%s | FileCheck %s -check-prefix=V9
Venkatraman Govindaraju20b10ab2013-10-06 03:36:18 +0000[diff] [blame^]3; RUN: llc -mtriple=sparc64-unknown-linux <%s | FileCheck %s -check-prefix=SPARC64
Venkatraman Govindarajuf27df332011-01-11 22:38:28 +0000[diff] [blame]4
5
6define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind readnone noinline {
7entry:
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]8; V8: addcc
9; V8-NOT: subcc
10; V8: addx
11; V9: addcc
12; V9-NOT: subcc
13; V9: addx
14; V9: mov{{e|ne}} %icc
Venkatraman Govindarajuf27df332011-01-11 22:38:28 +0000[diff] [blame]15 %0 = add i64 %a, %b
16 %1 = icmp ugt i64 %0, %c
17 %2 = zext i1 %1 to i32
18 ret i32 %2
19}
20
21
22define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline {
23entry:
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]24; V8: test_select_int_icc
Venkatraman Govindaraju01021a82013-06-07 00:03:36 +0000[diff] [blame]25; V8: cmp
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]26; V8: {{be|bne}}
27; V9: test_select_int_icc
Venkatraman Govindaraju01021a82013-06-07 00:03:36 +0000[diff] [blame]28; V9: cmp
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]29; V9-NOT: {{be|bne}}
30; V9: mov{{e|ne}} %icc
Venkatraman Govindarajuf27df332011-01-11 22:38:28 +0000[diff] [blame]31 %0 = icmp eq i32 %a, 0
32 %1 = select i1 %0, i32 %b, i32 %c
33 ret i32 %1
34}
35
36
37define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline {
38entry:
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]39; V8: test_select_fp_icc
Venkatraman Govindaraju01021a82013-06-07 00:03:36 +0000[diff] [blame]40; V8: cmp
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]41; V8: {{be|bne}}
42; V9: test_select_fp_icc
Venkatraman Govindaraju01021a82013-06-07 00:03:36 +0000[diff] [blame]43; V9: cmp
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]44; V9-NOT: {{be|bne}}
45; V9: fmovs{{e|ne}} %icc
Venkatraman Govindarajuf27df332011-01-11 22:38:28 +0000[diff] [blame]46 %0 = icmp eq i32 %a, 0
47 %1 = select i1 %0, float %f1, float %f2
48 ret float %1
49}
50
51define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline {
52entry:
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]53; V8: test_select_dfp_icc
Venkatraman Govindaraju01021a82013-06-07 00:03:36 +0000[diff] [blame]54; V8: cmp
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]55; V8: {{be|bne}}
56; V9: test_select_dfp_icc
Venkatraman Govindaraju01021a82013-06-07 00:03:36 +0000[diff] [blame]57; V9: cmp
Benjamin Kramerfba80d92012-10-02 15:49:34 +0000[diff] [blame]58; V9-NOT: {{be|bne}}
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]59; V9: fmovd{{e|ne}} %icc
Venkatraman Govindarajuf27df332011-01-11 22:38:28 +0000[diff] [blame]60 %0 = icmp eq i32 %a, 0
61 %1 = select i1 %0, double %f1, double %f2
62 ret double %1
63}
64
65define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline {
66entry:
Stephen Lincf2ab762013-07-18 22:47:09 +0000[diff] [blame]67;V8-LABEL: test_select_int_fcc:
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]68;V8: fcmps
69;V8: {{fbe|fbne}}
Stephen Lincf2ab762013-07-18 22:47:09 +0000[diff] [blame]70;V9-LABEL: test_select_int_fcc:
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]71;V9: fcmps
72;V9-NOT: {{fbe|fbne}}
73;V9: mov{{e|ne}} %fcc0
Venkatraman Govindarajuf27df332011-01-11 22:38:28 +0000[diff] [blame]74 %0 = fcmp une float %f, 0.000000e+00
75 %a.b = select i1 %0, i32 %a, i32 %b
76 ret i32 %a.b
77}
78
79
80define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline {
81entry:
Stephen Lincf2ab762013-07-18 22:47:09 +0000[diff] [blame]82;V8-LABEL: test_select_fp_fcc:
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]83;V8: fcmps
84;V8: {{fbe|fbne}}
Stephen Lincf2ab762013-07-18 22:47:09 +0000[diff] [blame]85;V9-LABEL: test_select_fp_fcc:
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]86;V9: fcmps
87;V9-NOT: {{fbe|fbne}}
88;V9: fmovs{{e|ne}} %fcc0
Venkatraman Govindarajuf27df332011-01-11 22:38:28 +0000[diff] [blame]89 %0 = fcmp une float %f, 0.000000e+00
90 %1 = select i1 %0, float %f1, float %f2
91 ret float %1
92}
93
94define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline {
95entry:
Stephen Lincf2ab762013-07-18 22:47:09 +0000[diff] [blame]96;V8-LABEL: test_select_dfp_fcc:
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]97;V8: fcmpd
98;V8: {{fbne|fbe}}
Stephen Lincf2ab762013-07-18 22:47:09 +0000[diff] [blame]99;V9-LABEL: test_select_dfp_fcc:
Venkatraman Govindarajue105a392011-01-22 11:36:24 +0000[diff] [blame]100;V9: fcmpd
101;V9-NOT: {{fbne|fbe}}
102;V9: fmovd{{e|ne}} %fcc0
Venkatraman Govindarajuf27df332011-01-11 22:38:28 +0000[diff] [blame]103 %0 = fcmp une double %f, 0.000000e+00
104 %1 = select i1 %0, double %f1, double %f2
105 ret double %1
106}
Venkatraman Govindaraju1c9524b2013-10-04 23:54:30 +0000[diff] [blame]107
108define i32 @test_float_cc(double %a, double %b, i32 %c, i32 %d) {
109entry:
110; V8-LABEL: test_float_cc
111; V8: fcmpd
112; V8: {{fbl|fbuge}} .LBB
113; V8: fcmpd
114; V8: {{fbule|fbg}} .LBB
115
116; V9-LABEL: test_float_cc
117; V9: fcmpd
118; V9: {{fbl|fbuge}} .LBB
119; V9: fcmpd
120; V9: {{fbule|fbg}} .LBB
121
122 %0 = fcmp uge double %a, 0.000000e+00
123 br i1 %0, label %loop, label %loop.2
124
125loop:
126 %1 = icmp eq i32 %c, 10
127 br i1 %1, label %loop, label %exit.0
128
129loop.2:
130 %2 = fcmp ogt double %b, 0.000000e+00
131 br i1 %2, label %exit.1, label %loop
132
133exit.0:
134 ret i32 0
135
136exit.1:
137 ret i32 1
138}
Venkatraman Govindarajubb0ec982013-10-06 02:11:10 +0000[diff] [blame]139
140; V8-LABEL: test_adde_sube
141; V8: addcc
142; V8: addxcc
143; V8: addxcc
144; V8: addxcc
145; V8: subcc
146; V8: subxcc
147; V8: subxcc
148; V8: subxcc
149
150
151; V9-LABEL: test_adde_sube
152; V9: addcc
153; V9: addxcc
154; V9: addxcc
155; V9: addxcc
156; V9: subcc
157; V9: subxcc
158; V9: subxcc
159; V9: subxcc
160
Venkatraman Govindaraju20b10ab2013-10-06 03:36:18 +0000[diff] [blame^]161; SPARC64-LABEL: test_adde_sube
162; SPARC64: addcc
163; SPARC64: addxcc
164; SPARC64: addxcc
165; SPARC64: addxcc
166; SPARC64: subcc
167; SPARC64: subxcc
168; SPARC64: subxcc
169; SPARC64: subxcc
170
Venkatraman Govindarajubb0ec982013-10-06 02:11:10 +0000[diff] [blame]171
172define void @test_adde_sube(i8* %a, i8* %b, i8* %sum, i8* %diff) {
173entry:
174 %0 = bitcast i8* %a to i128*
175 %1 = bitcast i8* %b to i128*
176 %2 = load i128* %0
177 %3 = load i128* %1
178 %4 = add i128 %2, %3
179 %5 = bitcast i8* %sum to i128*
180 store i128 %4, i128* %5
181 tail call void asm sideeffect "", "=*m,*m"(i128 *%0, i128* %5) nounwind
182 %6 = load i128* %0
183 %7 = sub i128 %2, %6
184 %8 = bitcast i8* %diff to i128*
185 store i128 %7, i128* %8
186 ret void
187}