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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 236ccb5fa1cd720da928d85124fdbd0669633e10 / . / lib / Target / ARM / ARMScheduleV7.td
blob: bf5858171de3044d1707f595e060ef40aa2961d7 [file] [log] [blame]
Evan Cheng0d68fde2009-07-21 18:54:14 +0000[diff] [blame]1//===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the ARM v7 processors.
11//
12//===----------------------------------------------------------------------===//
13
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame^]14//
15// Scheduling information derived from "Cortex-A8 Technical Reference Manual".
16//
David Goodwin48e13592009-08-10 15:56:13 +0000[diff] [blame]17// Dual issue pipeline so every itinerary starts with FU_Pipe0 | FU_Pipe1
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame^]18//
Evan Cheng0d68fde2009-07-21 18:54:14 +0000[diff] [blame]19def CortexA8Itineraries : ProcessorItineraries<[
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame^]20
21 // Two fully-pipelined integer ALU pipelines
22 //
23 // No operand cycles
24 InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
25 //
26 // Binary Instructions that produce a result
27 InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
28 InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 2]>,
29 InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1]>,
30 InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1, 1]>,
31 //
32 // Unary Instructions that produce a result
33 InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
34 InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
35 InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
36 //
37 // Compare instructions
38 InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
39 InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
40 InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
41 InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
42 //
43 // Move instructions, unconditional
44 InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1]>,
45 InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
46 InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
47 InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1, 1]>,
48 //
49 // Move instructions, conditional
50 InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
51 InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
52 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
53 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
54
55 // Integer multiply pipeline
56 // Result written in E5, but that is relative to the last cycle of multicycle,
57 // so we use 6 for those cases
58 //
59 InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>], [5, 1, 1]>,
60 InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe1], 0>,
61 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
62 InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe1], 0>,
63 InstrStage<2, [FU_Pipe0]>], [6, 1, 1]>,
64 InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe1], 0>,
65 InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
66 InstrItinData<IIC_iMUL64 , [InstrStage<2, [FU_Pipe1], 0>,
67 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
68 InstrItinData<IIC_iMAC64 , [InstrStage<2, [FU_Pipe1], 0>,
69 InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
70
71 // Integer load pipeline
72 //
David Goodwin48e13592009-08-10 15:56:13 +0000[diff] [blame]73 // loads have an extra cycle of latency, but are fully pipelined
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]74 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame^]75 //
76 // Immediate offset
77 InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Issue], 0>,
78 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
79 InstrStage<1, [FU_LdSt0]>], [3, 1]>,
80 //
81 // Register offset
82 InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Issue], 0>,
83 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
84 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
85 //
86 // Scaled register offset, issues over 2 cycles
87 InstrItinData<IIC_iLoadsi , [InstrStage<2, [FU_Issue], 0>,
88 InstrStage<1, [FU_Pipe0], 0>,
89 InstrStage<1, [FU_Pipe1], 0>,
90 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
91 InstrStage<1, [FU_LdSt0]>], [4, 1, 1]>,
92 //
93 // Immediate offset with update
94 InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Issue], 0>,
95 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
96 InstrStage<1, [FU_LdSt0]>], [3, 2, 1]>,
97 //
98 // Register offset with update
99 InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Issue], 0>,
100 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
101 InstrStage<1, [FU_LdSt0]>], [3, 2, 1, 1]>,
102 //
103 // Scaled register offset with update, issues over 2 cycles
104 InstrItinData<IIC_iLoadsiu , [InstrStage<2, [FU_Issue], 0>,
105 InstrStage<1, [FU_Pipe0], 0>,
106 InstrStage<1, [FU_Pipe1], 0>,
107 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
108 InstrStage<1, [FU_LdSt0]>], [4, 3, 1, 1]>,
109 //
110 // Load multiple
111 InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Issue], 0>,
112 InstrStage<2, [FU_Pipe0], 0>,
113 InstrStage<2, [FU_Pipe1], 0>,
114 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
115 InstrStage<1, [FU_LdSt0]>]>,
116
117 // Integer store pipeline
118 //
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]119 // use FU_Issue to enforce the 1 load/store per cycle limit
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame^]120 //
121 // Immediate offset
122 InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Issue], 0>,
123 InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [3, 1]>,
124 //
125 // Register offset
126 InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Issue], 0>,
127 InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [3, 1, 1]>,
128 //
129 // Scaled register offset, issues over 2 cycles
130 InstrItinData<IIC_iStoresi , [InstrStage<2, [FU_Issue], 0>,
131 InstrStage<1, [FU_Pipe0], 0>,
132 InstrStage<1, [FU_Pipe1], 0>,
133 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
134 InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
135 //
136 // Immediate offset with update
137 InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Issue], 0>,
138 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
139 InstrStage<1, [FU_LdSt0]>], [2, 3, 1]>,
140 //
141 // Register offset with update
142 InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Issue], 0>,
143 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
144 InstrStage<1, [FU_LdSt0]>], [2, 3, 1, 1]>,
145 //
146 // Scaled register offset with update, issues over 2 cycles
147 InstrItinData<IIC_iStoresiu, [InstrStage<2, [FU_Issue], 0>,
148 InstrStage<1, [FU_Pipe0], 0>,
149 InstrStage<1, [FU_Pipe1], 0>,
150 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
151 InstrStage<1, [FU_LdSt0]>], [3, 3, 1, 1]>,
152 //
153 // Store multiple
154 InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Issue], 0>,
155 InstrStage<2, [FU_Pipe0], 0>,
156 InstrStage<2, [FU_Pipe1], 0>,
157 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
158 InstrStage<1, [FU_LdSt0]>]>,
159
160 // Branch
161 //
David Goodwin48e13592009-08-10 15:56:13 +0000[diff] [blame]162 // no delay slots, so the latency of a branch is unimportant
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]163 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
164
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]165 // NFP ALU is not pipelined so stall all issues
166 InstrItinData<IIC_fpALU , [InstrStage<7, [FU_Pipe0], 0>,
167 InstrStage<7, [FU_Pipe1], 0>]>,
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]168 // VFP MPY is not pipelined so stall all issues
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]169 InstrItinData<IIC_fpMPY , [InstrStage<7, [FU_Pipe0], 0>,
170 InstrStage<7, [FU_Pipe1], 0>]>,
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]171 // loads have an extra cycle of latency, but are fully pipelined
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]172 // use FU_Issue to enforce the 1 load/store per cycle limit
173 InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Issue], 0>,
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]174 InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
175 InstrStage<1, [FU_LdSt0]>]>,
David Goodwin4b6e4982009-08-12 18:31:53 +0000[diff] [blame]176 // use FU_Issue to enforce the 1 load/store per cycle limit
177 InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Issue], 0>,
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]178 InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>
179]>;
180
181// FIXME
182def CortexA9Itineraries : ProcessorItineraries<[
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame^]183 InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
184 InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>]>,
185 InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>]>,
186 InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>]>,
187 InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0]>]>,
188 InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>]>,
189 InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>]>,
190 InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0]>]>,
191 InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>]>,
192 InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>]>,
193 InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>]>,
194 InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0]>]>,
195 InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>]>,
196 InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>]>,
197 InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
198 InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
199 InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>]>,
200 InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>]>,
201 InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
202 InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
203 InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>]>,
204 InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>]>,
205 InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
206 InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
207 InstrItinData<IIC_iMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
208 InstrItinData<IIC_iMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
209 InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>,
Evan Chengff5c7c42009-08-15 07:59:10 +0000[diff] [blame]210 InstrStage<1, [FU_LdSt0]>]>,
David Goodwin236ccb52009-08-19 18:00:44 +0000[diff] [blame^]211 InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>,
212 InstrStage<1, [FU_LdSt0]>]>,
213 InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
214 InstrStage<1, [FU_LdSt0]>]>,
215 InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
216 InstrStage<1, [FU_LdSt0]>]>,
217 InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
218 InstrStage<1, [FU_LdSt0]>]>,
219 InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
220 InstrStage<1, [FU_LdSt0]>]>,
221 InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Pipe0]>,
222 InstrStage<2, [FU_LdSt0]>]>,
223 InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>]>,
224 InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>]>,
225 InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
226 InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
227 InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
228 InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
229 InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Pipe0]>]>,
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]230 InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
231 InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
232 InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>,
Evan Chengff5c7c42009-08-15 07:59:10 +0000[diff] [blame]233 InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>,
234 InstrStage<1, [FU_LdSt0]>]>,
David Goodwineb759722009-08-11 22:38:43 +0000[diff] [blame]235 InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>
Evan Cheng0d68fde2009-07-21 18:54:14 +0000[diff] [blame]236]>;