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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.h - Virtual Register Map -*- C++ -*--------===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00007//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements a virtual register map. This maps virtual registers to
11// physical registers and virtual registers to stack slots. It is created and
12// updated by a register allocator and then used by a machine code rewriter that
13// adds spill code and rewrites virtual into physical register references.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000014//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_CODEGEN_VIRTREGMAP_H
18#define LLVM_CODEGEN_VIRTREGMAP_H
19
Owen Anderson49c8aa02009-03-13 05:55:11 +000020#include "llvm/CodeGen/MachineFunctionPass.h"
Lang Hames86511252009-09-04 20:41:11 +000021#include "llvm/CodeGen/LiveInterval.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +000022#include "llvm/Target/TargetRegisterInfo.h"
Evan Cheng4cce6b42008-04-11 17:53:36 +000023#include "llvm/ADT/BitVector.h"
Evan Chengc781a242009-05-03 18:32:42 +000024#include "llvm/ADT/DenseMap.h"
Chris Lattner94c002a2007-02-01 05:32:05 +000025#include "llvm/ADT/IndexedMap.h"
Evan Chengd3653122008-02-27 03:04:06 +000026#include "llvm/ADT/SmallPtrSet.h"
Dan Gohmand68a0762009-01-05 17:59:02 +000027#include "llvm/ADT/SmallVector.h"
Alkis Evlogimenos5f375022004-03-01 20:05:10 +000028#include <map>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000029
30namespace llvm {
Evan Chengc781a242009-05-03 18:32:42 +000031 class LiveIntervals;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000032 class MachineInstr;
David Greene7e231462007-08-07 16:34:05 +000033 class MachineFunction;
Evan Cheng90f95f82009-06-14 20:22:55 +000034 class MachineRegisterInfo;
Chris Lattner29268692006-09-05 02:12:02 +000035 class TargetInstrInfo;
Mike Stumpfe095f32009-05-04 18:40:41 +000036 class TargetRegisterInfo;
Daniel Dunbar1cd1d982009-07-24 10:36:58 +000037 class raw_ostream;
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000038
Owen Anderson49c8aa02009-03-13 05:55:11 +000039 class VirtRegMap : public MachineFunctionPass {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000040 public:
Evan Cheng2638e1a2007-03-20 08:13:50 +000041 enum {
42 NO_PHYS_REG = 0,
Evan Cheng91935142007-04-04 07:40:01 +000043 NO_STACK_SLOT = (1L << 30)-1,
44 MAX_STACK_SLOT = (1L << 18)-1
Evan Cheng2638e1a2007-03-20 08:13:50 +000045 };
46
Chris Lattner35f27052006-05-01 21:16:03 +000047 enum ModRef { isRef = 1, isMod = 2, isModRef = 3 };
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000048 typedef std::multimap<MachineInstr*,
49 std::pair<unsigned, ModRef> > MI2VirtMapTy;
Alkis Evlogimenos5f375022004-03-01 20:05:10 +000050
Chris Lattner8c4d88d2004-09-30 01:54:45 +000051 private:
Evan Cheng90f95f82009-06-14 20:22:55 +000052 MachineRegisterInfo *MRI;
Owen Anderson49c8aa02009-03-13 05:55:11 +000053 const TargetInstrInfo *TII;
Mike Stumpfe095f32009-05-04 18:40:41 +000054 const TargetRegisterInfo *TRI;
Owen Anderson49c8aa02009-03-13 05:55:11 +000055 MachineFunction *MF;
Mike Stumpfe095f32009-05-04 18:40:41 +000056
57 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs;
58
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +000059 /// Virt2PhysMap - This is a virtual to physical register
60 /// mapping. Each virtual register is required to have an entry in
61 /// it; even spilled virtual registers (the register mapped to a
62 /// spilled register is the temporary used to load it from the
63 /// stack).
Chris Lattner94c002a2007-02-01 05:32:05 +000064 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysMap;
Evan Cheng81a03822007-11-17 00:40:40 +000065
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +000066 /// Virt2StackSlotMap - This is virtual register to stack slot
67 /// mapping. Each spilled virtual register has an entry in it
68 /// which corresponds to the stack slot this register is spilled
69 /// at.
Chris Lattner94c002a2007-02-01 05:32:05 +000070 IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
Evan Cheng81a03822007-11-17 00:40:40 +000071
Dan Gohman39e33ac2008-03-12 20:50:04 +000072 /// Virt2ReMatIdMap - This is virtual register to rematerialization id
Evan Cheng81a03822007-11-17 00:40:40 +000073 /// mapping. Each spilled virtual register that should be remat'd has an
74 /// entry in it which corresponds to the remat id.
Evan Cheng549f27d32007-08-13 23:45:17 +000075 IndexedMap<int, VirtReg2IndexFunctor> Virt2ReMatIdMap;
Evan Cheng81a03822007-11-17 00:40:40 +000076
77 /// Virt2SplitMap - This is virtual register to splitted virtual register
78 /// mapping.
79 IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2SplitMap;
80
Evan Chengadf85902007-12-05 09:51:10 +000081 /// Virt2SplitKillMap - This is splitted virtual register to its last use
Evan Chengd120ffd2007-12-05 10:24:35 +000082 /// (kill) index mapping.
Jakob Stoklund Olesen2cfa5b42011-01-09 18:58:33 +000083 IndexedMap<SlotIndex, VirtReg2IndexFunctor> Virt2SplitKillMap;
Evan Chengadf85902007-12-05 09:51:10 +000084
Evan Cheng81a03822007-11-17 00:40:40 +000085 /// ReMatMap - This is virtual register to re-materialized instruction
86 /// mapping. Each virtual register whose definition is going to be
87 /// re-materialized has an entry in it.
88 IndexedMap<MachineInstr*, VirtReg2IndexFunctor> ReMatMap;
89
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +000090 /// MI2VirtMap - This is MachineInstr to virtual register
91 /// mapping. In the case of memory spill code being folded into
92 /// instructions, we need to know which virtual register was
93 /// read/written by this instruction.
Chris Lattner7f690e62004-09-30 02:15:18 +000094 MI2VirtMapTy MI2VirtMap;
Misha Brukmanedf128a2005-04-21 22:36:52 +000095
Evan Cheng81a03822007-11-17 00:40:40 +000096 /// SpillPt2VirtMap - This records the virtual registers which should
97 /// be spilled right after the MachineInstr due to live interval
98 /// splitting.
Evan Chengb50bb8c2007-12-05 08:16:32 +000099 std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > >
100 SpillPt2VirtMap;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000101
Evan Cheng0cbb1162007-11-29 01:06:25 +0000102 /// RestorePt2VirtMap - This records the virtual registers which should
103 /// be restored right before the MachineInstr due to live interval
104 /// splitting.
105 std::map<MachineInstr*, std::vector<unsigned> > RestorePt2VirtMap;
106
Evan Cheng676dd7c2008-03-11 07:19:34 +0000107 /// EmergencySpillMap - This records the physical registers that should
108 /// be spilled / restored around the MachineInstr since the register
109 /// allocator has run out of registers.
110 std::map<MachineInstr*, std::vector<unsigned> > EmergencySpillMap;
111
112 /// EmergencySpillSlots - This records emergency spill slots used to
113 /// spill physical registers when the register allocator runs out of
114 /// registers. Ideally only one stack slot is used per function per
115 /// register class.
116 std::map<const TargetRegisterClass*, int> EmergencySpillSlots;
117
Evan Cheng2638e1a2007-03-20 08:13:50 +0000118 /// ReMatId - Instead of assigning a stack slot to a to be rematerialized
Evan Cheng91935142007-04-04 07:40:01 +0000119 /// virtual register, an unique id is being assigned. This keeps track of
Evan Cheng2638e1a2007-03-20 08:13:50 +0000120 /// the highest id used so far. Note, this starts at (1<<18) to avoid
121 /// conflicts with stack slot numbers.
122 int ReMatId;
123
Evan Chengd3653122008-02-27 03:04:06 +0000124 /// LowSpillSlot, HighSpillSlot - Lowest and highest spill slot indexes.
125 int LowSpillSlot, HighSpillSlot;
126
127 /// SpillSlotToUsesMap - Records uses for each register spill slot.
128 SmallVector<SmallPtrSet<MachineInstr*, 4>, 8> SpillSlotToUsesMap;
129
Evan Cheng4cce6b42008-04-11 17:53:36 +0000130 /// ImplicitDefed - One bit for each virtual register. If set it indicates
131 /// the register is implicitly defined.
132 BitVector ImplicitDefed;
133
Evan Chengc781a242009-05-03 18:32:42 +0000134 /// UnusedRegs - A list of physical registers that have not been used.
135 BitVector UnusedRegs;
136
Jakob Stoklund Olesenb55e91e2010-11-16 00:41:01 +0000137 /// createSpillSlot - Allocate a spill slot for RC from MFI.
138 unsigned createSpillSlot(const TargetRegisterClass *RC);
139
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000140 VirtRegMap(const VirtRegMap&); // DO NOT IMPLEMENT
141 void operator=(const VirtRegMap&); // DO NOT IMPLEMENT
Alkis Evlogimenos79742872004-02-23 23:47:10 +0000142
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000143 public:
Owen Anderson49c8aa02009-03-13 05:55:11 +0000144 static char ID;
Owen Anderson90c579d2010-08-06 18:33:48 +0000145 VirtRegMap() : MachineFunctionPass(ID), Virt2PhysMap(NO_PHYS_REG),
Owen Anderson49c8aa02009-03-13 05:55:11 +0000146 Virt2StackSlotMap(NO_STACK_SLOT),
147 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0),
Lang Hames233a60e2009-11-03 23:52:08 +0000148 Virt2SplitKillMap(SlotIndex()), ReMatMap(NULL),
Owen Anderson49c8aa02009-03-13 05:55:11 +0000149 ReMatId(MAX_STACK_SLOT+1),
150 LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { }
151 virtual bool runOnMachineFunction(MachineFunction &MF);
152
153 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
154 AU.setPreservesAll();
155 MachineFunctionPass::getAnalysisUsage(AU);
156 }
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000157
Jakob Stoklund Olesenf0179002010-07-26 23:44:11 +0000158 MachineFunction &getMachineFunction() const {
Jakob Stoklund Olesenc9672cb2010-12-10 18:36:02 +0000159 assert(MF && "getMachineFunction called before runOnMachineFunction");
Jakob Stoklund Olesenf0179002010-07-26 23:44:11 +0000160 return *MF;
161 }
162
Jakob Stoklund Olesenc9672cb2010-12-10 18:36:02 +0000163 MachineRegisterInfo &getRegInfo() const { return *MRI; }
164 const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
165
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000166 void grow();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000167
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000168 /// @brief returns true if the specified virtual register is
169 /// mapped to a physical register
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000170 bool hasPhys(unsigned virtReg) const {
171 return getPhys(virtReg) != NO_PHYS_REG;
172 }
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000173
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000174 /// @brief returns the physical register mapped to the specified
175 /// virtual register
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000176 unsigned getPhys(unsigned virtReg) const {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000177 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +0000178 return Virt2PhysMap[virtReg];
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000179 }
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000180
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000181 /// @brief creates a mapping for the specified virtual register to
182 /// the specified physical register
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000183 void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000184 assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
185 TargetRegisterInfo::isPhysicalRegister(physReg));
Chris Lattner7f690e62004-09-30 02:15:18 +0000186 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000187 "attempt to assign physical register to already mapped "
188 "virtual register");
Chris Lattner7f690e62004-09-30 02:15:18 +0000189 Virt2PhysMap[virtReg] = physReg;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000190 }
191
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000192 /// @brief clears the specified virtual register's, physical
193 /// register mapping
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000194 void clearVirt(unsigned virtReg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000195 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +0000196 assert(Virt2PhysMap[virtReg] != NO_PHYS_REG &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000197 "attempt to clear a not assigned virtual register");
Chris Lattner7f690e62004-09-30 02:15:18 +0000198 Virt2PhysMap[virtReg] = NO_PHYS_REG;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000199 }
200
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000201 /// @brief clears all virtual to physical register mappings
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000202 void clearAllVirt() {
Chris Lattner7f690e62004-09-30 02:15:18 +0000203 Virt2PhysMap.clear();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000204 grow();
205 }
206
Evan Cheng90f95f82009-06-14 20:22:55 +0000207 /// @brief returns the register allocation preference.
208 unsigned getRegAllocPref(unsigned virtReg);
209
Evan Cheng81a03822007-11-17 00:40:40 +0000210 /// @brief records virtReg is a split live interval from SReg.
211 void setIsSplitFromReg(unsigned virtReg, unsigned SReg) {
212 Virt2SplitMap[virtReg] = SReg;
213 }
214
215 /// @brief returns the live interval virtReg is split from.
216 unsigned getPreSplitReg(unsigned virtReg) {
217 return Virt2SplitMap[virtReg];
218 }
219
Dan Gohman39e33ac2008-03-12 20:50:04 +0000220 /// @brief returns true if the specified virtual register is not
Evan Cheng549f27d32007-08-13 23:45:17 +0000221 /// mapped to a stack slot or rematerialized.
222 bool isAssignedReg(unsigned virtReg) const {
Evan Cheng81a03822007-11-17 00:40:40 +0000223 if (getStackSlot(virtReg) == NO_STACK_SLOT &&
224 getReMatId(virtReg) == NO_STACK_SLOT)
225 return true;
226 // Split register can be assigned a physical register as well as a
227 // stack slot or remat id.
228 return (Virt2SplitMap[virtReg] && Virt2PhysMap[virtReg] != NO_PHYS_REG);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000229 }
230
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000231 /// @brief returns the stack slot mapped to the specified virtual
232 /// register
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000233 int getStackSlot(unsigned virtReg) const {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000234 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +0000235 return Virt2StackSlotMap[virtReg];
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000236 }
237
Evan Cheng549f27d32007-08-13 23:45:17 +0000238 /// @brief returns the rematerialization id mapped to the specified virtual
239 /// register
240 int getReMatId(unsigned virtReg) const {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000241 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
Evan Cheng549f27d32007-08-13 23:45:17 +0000242 return Virt2ReMatIdMap[virtReg];
243 }
244
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000245 /// @brief create a mapping for the specifed virtual register to
246 /// the next available stack slot
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000247 int assignVirt2StackSlot(unsigned virtReg);
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000248 /// @brief create a mapping for the specified virtual register to
249 /// the specified stack slot
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000250 void assignVirt2StackSlot(unsigned virtReg, int frameIndex);
251
Evan Cheng2638e1a2007-03-20 08:13:50 +0000252 /// @brief assign an unique re-materialization id to the specified
253 /// virtual register.
254 int assignVirtReMatId(unsigned virtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000255 /// @brief assign an unique re-materialization id to the specified
256 /// virtual register.
257 void assignVirtReMatId(unsigned virtReg, int id);
Evan Cheng2638e1a2007-03-20 08:13:50 +0000258
259 /// @brief returns true if the specified virtual register is being
260 /// re-materialized.
261 bool isReMaterialized(unsigned virtReg) const {
Evan Cheng549f27d32007-08-13 23:45:17 +0000262 return ReMatMap[virtReg] != NULL;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000263 }
264
265 /// @brief returns the original machine instruction being re-issued
266 /// to re-materialize the specified virtual register.
Evan Cheng549f27d32007-08-13 23:45:17 +0000267 MachineInstr *getReMaterializedMI(unsigned virtReg) const {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000268 return ReMatMap[virtReg];
269 }
270
271 /// @brief records the specified virtual register will be
272 /// re-materialized and the original instruction which will be re-issed
Evan Cheng549f27d32007-08-13 23:45:17 +0000273 /// for this purpose. If parameter all is true, then all uses of the
274 /// registers are rematerialized and it's safe to delete the definition.
Evan Cheng2638e1a2007-03-20 08:13:50 +0000275 void setVirtIsReMaterialized(unsigned virtReg, MachineInstr *def) {
276 ReMatMap[virtReg] = def;
277 }
278
Evan Chengadf85902007-12-05 09:51:10 +0000279 /// @brief record the last use (kill) of a split virtual register.
Lang Hames233a60e2009-11-03 23:52:08 +0000280 void addKillPoint(unsigned virtReg, SlotIndex index) {
Evan Chengd120ffd2007-12-05 10:24:35 +0000281 Virt2SplitKillMap[virtReg] = index;
Evan Chengadf85902007-12-05 09:51:10 +0000282 }
283
Lang Hames233a60e2009-11-03 23:52:08 +0000284 SlotIndex getKillPoint(unsigned virtReg) const {
Evan Chengd120ffd2007-12-05 10:24:35 +0000285 return Virt2SplitKillMap[virtReg];
286 }
287
288 /// @brief remove the last use (kill) of a split virtual register.
Evan Chengadf85902007-12-05 09:51:10 +0000289 void removeKillPoint(unsigned virtReg) {
Lang Hames233a60e2009-11-03 23:52:08 +0000290 Virt2SplitKillMap[virtReg] = SlotIndex();
Evan Chengadf85902007-12-05 09:51:10 +0000291 }
292
Evan Chengcada2452007-11-28 01:28:46 +0000293 /// @brief returns true if the specified MachineInstr is a spill point.
294 bool isSpillPt(MachineInstr *Pt) const {
295 return SpillPt2VirtMap.find(Pt) != SpillPt2VirtMap.end();
296 }
297
Evan Cheng81a03822007-11-17 00:40:40 +0000298 /// @brief returns the virtual registers that should be spilled due to
299 /// splitting right after the specified MachineInstr.
Evan Chengb50bb8c2007-12-05 08:16:32 +0000300 std::vector<std::pair<unsigned,bool> > &getSpillPtSpills(MachineInstr *Pt) {
Evan Cheng81a03822007-11-17 00:40:40 +0000301 return SpillPt2VirtMap[Pt];
302 }
303
304 /// @brief records the specified MachineInstr as a spill point for virtReg.
Evan Chengb50bb8c2007-12-05 08:16:32 +0000305 void addSpillPoint(unsigned virtReg, bool isKill, MachineInstr *Pt) {
Evan Chengc781a242009-05-03 18:32:42 +0000306 std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > >::iterator
307 I = SpillPt2VirtMap.find(Pt);
308 if (I != SpillPt2VirtMap.end())
309 I->second.push_back(std::make_pair(virtReg, isKill));
Evan Chengcada2452007-11-28 01:28:46 +0000310 else {
Evan Chengb50bb8c2007-12-05 08:16:32 +0000311 std::vector<std::pair<unsigned,bool> > Virts;
312 Virts.push_back(std::make_pair(virtReg, isKill));
Evan Chengcada2452007-11-28 01:28:46 +0000313 SpillPt2VirtMap.insert(std::make_pair(Pt, Virts));
314 }
Evan Cheng81a03822007-11-17 00:40:40 +0000315 }
316
Evan Chengc1f53c72008-03-11 21:34:46 +0000317 /// @brief - transfer spill point information from one instruction to
318 /// another.
Evan Cheng81a03822007-11-17 00:40:40 +0000319 void transferSpillPts(MachineInstr *Old, MachineInstr *New) {
Evan Chengc781a242009-05-03 18:32:42 +0000320 std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > >::iterator
Evan Chengb50bb8c2007-12-05 08:16:32 +0000321 I = SpillPt2VirtMap.find(Old);
Evan Chengcada2452007-11-28 01:28:46 +0000322 if (I == SpillPt2VirtMap.end())
323 return;
324 while (!I->second.empty()) {
Evan Chengb50bb8c2007-12-05 08:16:32 +0000325 unsigned virtReg = I->second.back().first;
326 bool isKill = I->second.back().second;
Evan Chengcada2452007-11-28 01:28:46 +0000327 I->second.pop_back();
Evan Chengb50bb8c2007-12-05 08:16:32 +0000328 addSpillPoint(virtReg, isKill, New);
Evan Cheng81a03822007-11-17 00:40:40 +0000329 }
Evan Chengcada2452007-11-28 01:28:46 +0000330 SpillPt2VirtMap.erase(I);
Evan Cheng81a03822007-11-17 00:40:40 +0000331 }
332
Evan Cheng0cbb1162007-11-29 01:06:25 +0000333 /// @brief returns true if the specified MachineInstr is a restore point.
334 bool isRestorePt(MachineInstr *Pt) const {
335 return RestorePt2VirtMap.find(Pt) != RestorePt2VirtMap.end();
336 }
337
338 /// @brief returns the virtual registers that should be restoreed due to
339 /// splitting right after the specified MachineInstr.
340 std::vector<unsigned> &getRestorePtRestores(MachineInstr *Pt) {
341 return RestorePt2VirtMap[Pt];
342 }
343
344 /// @brief records the specified MachineInstr as a restore point for virtReg.
345 void addRestorePoint(unsigned virtReg, MachineInstr *Pt) {
Evan Chengc781a242009-05-03 18:32:42 +0000346 std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
347 RestorePt2VirtMap.find(Pt);
348 if (I != RestorePt2VirtMap.end())
349 I->second.push_back(virtReg);
Evan Cheng0cbb1162007-11-29 01:06:25 +0000350 else {
351 std::vector<unsigned> Virts;
352 Virts.push_back(virtReg);
353 RestorePt2VirtMap.insert(std::make_pair(Pt, Virts));
354 }
355 }
356
Evan Cheng676dd7c2008-03-11 07:19:34 +0000357 /// @brief - transfer restore point information from one instruction to
358 /// another.
Evan Cheng0cbb1162007-11-29 01:06:25 +0000359 void transferRestorePts(MachineInstr *Old, MachineInstr *New) {
Evan Chengc781a242009-05-03 18:32:42 +0000360 std::map<MachineInstr*, std::vector<unsigned> >::iterator I =
Evan Cheng0cbb1162007-11-29 01:06:25 +0000361 RestorePt2VirtMap.find(Old);
362 if (I == RestorePt2VirtMap.end())
363 return;
364 while (!I->second.empty()) {
365 unsigned virtReg = I->second.back();
366 I->second.pop_back();
367 addRestorePoint(virtReg, New);
368 }
369 RestorePt2VirtMap.erase(I);
370 }
371
Evan Cheng676dd7c2008-03-11 07:19:34 +0000372 /// @brief records that the specified physical register must be spilled
373 /// around the specified machine instr.
374 void addEmergencySpill(unsigned PhysReg, MachineInstr *MI) {
375 if (EmergencySpillMap.find(MI) != EmergencySpillMap.end())
376 EmergencySpillMap[MI].push_back(PhysReg);
377 else {
378 std::vector<unsigned> PhysRegs;
379 PhysRegs.push_back(PhysReg);
380 EmergencySpillMap.insert(std::make_pair(MI, PhysRegs));
381 }
382 }
383
384 /// @brief returns true if one or more physical registers must be spilled
385 /// around the specified instruction.
386 bool hasEmergencySpills(MachineInstr *MI) const {
387 return EmergencySpillMap.find(MI) != EmergencySpillMap.end();
388 }
389
390 /// @brief returns the physical registers to be spilled and restored around
391 /// the instruction.
392 std::vector<unsigned> &getEmergencySpills(MachineInstr *MI) {
393 return EmergencySpillMap[MI];
394 }
395
Evan Chengc1f53c72008-03-11 21:34:46 +0000396 /// @brief - transfer emergency spill information from one instruction to
397 /// another.
398 void transferEmergencySpills(MachineInstr *Old, MachineInstr *New) {
399 std::map<MachineInstr*,std::vector<unsigned> >::iterator I =
400 EmergencySpillMap.find(Old);
401 if (I == EmergencySpillMap.end())
402 return;
403 while (!I->second.empty()) {
404 unsigned virtReg = I->second.back();
405 I->second.pop_back();
406 addEmergencySpill(virtReg, New);
407 }
408 EmergencySpillMap.erase(I);
409 }
410
Evan Cheng676dd7c2008-03-11 07:19:34 +0000411 /// @brief return or get a emergency spill slot for the register class.
412 int getEmergencySpillSlot(const TargetRegisterClass *RC);
413
Evan Chengd3653122008-02-27 03:04:06 +0000414 /// @brief Return lowest spill slot index.
415 int getLowSpillSlot() const {
416 return LowSpillSlot;
417 }
418
419 /// @brief Return highest spill slot index.
420 int getHighSpillSlot() const {
421 return HighSpillSlot;
422 }
423
424 /// @brief Records a spill slot use.
425 void addSpillSlotUse(int FrameIndex, MachineInstr *MI);
426
427 /// @brief Returns true if spill slot has been used.
428 bool isSpillSlotUsed(int FrameIndex) const {
429 assert(FrameIndex >= 0 && "Spill slot index should not be negative!");
430 return !SpillSlotToUsesMap[FrameIndex-LowSpillSlot].empty();
431 }
432
Evan Cheng4cce6b42008-04-11 17:53:36 +0000433 /// @brief Mark the specified register as being implicitly defined.
434 void setIsImplicitlyDefined(unsigned VirtReg) {
Jakob Stoklund Olesenc7d67f92011-01-08 23:11:07 +0000435 ImplicitDefed.set(TargetRegisterInfo::virtReg2Index(VirtReg));
Evan Cheng4cce6b42008-04-11 17:53:36 +0000436 }
437
438 /// @brief Returns true if the virtual register is implicitly defined.
439 bool isImplicitlyDefined(unsigned VirtReg) const {
Jakob Stoklund Olesenc7d67f92011-01-08 23:11:07 +0000440 return ImplicitDefed[TargetRegisterInfo::virtReg2Index(VirtReg)];
Evan Cheng4cce6b42008-04-11 17:53:36 +0000441 }
442
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000443 /// @brief Updates information about the specified virtual register's value
Evan Chengaee4af62007-12-02 08:30:39 +0000444 /// folded into newMI machine instruction.
445 void virtFolded(unsigned VirtReg, MachineInstr *OldMI, MachineInstr *NewMI,
446 ModRef MRInfo);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000447
Evan Cheng7f566252007-10-13 02:50:24 +0000448 /// @brief Updates information about the specified virtual register's value
449 /// folded into the specified machine instruction.
450 void virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo);
451
Alkis Evlogimenosc736b3a2004-10-01 00:35:07 +0000452 /// @brief returns the virtual registers' values folded in memory
453 /// operands of this instruction
Chris Lattner7f690e62004-09-30 02:15:18 +0000454 std::pair<MI2VirtMapTy::const_iterator, MI2VirtMapTy::const_iterator>
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000455 getFoldedVirts(MachineInstr* MI) const {
Chris Lattner7f690e62004-09-30 02:15:18 +0000456 return MI2VirtMap.equal_range(MI);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000457 }
Chris Lattner35f27052006-05-01 21:16:03 +0000458
Evan Chengcada2452007-11-28 01:28:46 +0000459 /// RemoveMachineInstrFromMaps - MI is being erased, remove it from the
460 /// the folded instruction map and spill point map.
Evan Chengd3653122008-02-27 03:04:06 +0000461 void RemoveMachineInstrFromMaps(MachineInstr *MI);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000462
Evan Chengc781a242009-05-03 18:32:42 +0000463 /// FindUnusedRegisters - Gather a list of allocatable registers that
464 /// have not been allocated to any virtual register.
Evan Cheng90f95f82009-06-14 20:22:55 +0000465 bool FindUnusedRegisters(LiveIntervals* LIs);
Evan Chengc781a242009-05-03 18:32:42 +0000466
467 /// HasUnusedRegisters - Return true if there are any allocatable registers
468 /// that have not been allocated to any virtual register.
469 bool HasUnusedRegisters() const {
470 return !UnusedRegs.none();
471 }
472
473 /// setRegisterUsed - Remember the physical register is now used.
474 void setRegisterUsed(unsigned Reg) {
475 UnusedRegs.reset(Reg);
476 }
477
478 /// isRegisterUnused - Return true if the physical register has not been
479 /// used.
480 bool isRegisterUnused(unsigned Reg) const {
481 return UnusedRegs[Reg];
482 }
483
484 /// getFirstUnusedRegister - Return the first physical register that has not
485 /// been used.
486 unsigned getFirstUnusedRegister(const TargetRegisterClass *RC) {
487 int Reg = UnusedRegs.find_first();
488 while (Reg != -1) {
Mike Stumpfe095f32009-05-04 18:40:41 +0000489 if (allocatableRCRegs[RC][Reg])
Evan Chengc781a242009-05-03 18:32:42 +0000490 return (unsigned)Reg;
491 Reg = UnusedRegs.find_next(Reg);
492 }
493 return 0;
494 }
495
Daniel Dunbar1cd1d982009-07-24 10:36:58 +0000496 void print(raw_ostream &OS, const Module* M = 0) const;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000497 void dump() const;
498 };
499
Daniel Dunbar1cd1d982009-07-24 10:36:58 +0000500 inline raw_ostream &operator<<(raw_ostream &OS, const VirtRegMap &VRM) {
501 VRM.print(OS);
502 return OS;
503 }
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000504} // End llvm namespace
505
506#endif