blob: ae6221af9d813808f4fa9fbabb90019b80a9380e [file] [log] [blame]
Dan Gohman36a09472009-09-08 23:54:48 +00001; RUN: llc < %s -march=x86 | not grep and
2; RUN: llc < %s -march=x86-64 > %t
Dan Gohman11ba3b12008-07-30 18:09:17 +00003; RUN: not grep and %t
4; RUN: not grep movzbq %t
5; RUN: not grep movzwq %t
6; RUN: not grep movzlq %t
7
8; These should use movzbl instead of 'and 255'.
9; This related to not having a ZERO_EXTEND_REG opcode.
10
Dan Gohman8a1510d2008-08-06 18:27:21 +000011define i32 @a(i32 %d) nounwind {
12 %e = add i32 %d, 1
13 %retval = and i32 %e, 255
14 ret i32 %retval
15}
16define i32 @b(float %d) nounwind {
17 %tmp12 = fptoui float %d to i8
18 %retval = zext i8 %tmp12 to i32
19 ret i32 %retval
20}
Dan Gohman11ba3b12008-07-30 18:09:17 +000021define i32 @c(i32 %d) nounwind {
22 %e = add i32 %d, 1
23 %retval = and i32 %e, 65535
24 ret i32 %retval
25}
Dan Gohman8a1510d2008-08-06 18:27:21 +000026define i64 @d(i64 %d) nounwind {
27 %e = add i64 %d, 1
28 %retval = and i64 %e, 255
29 ret i64 %retval
30}
Dan Gohman11ba3b12008-07-30 18:09:17 +000031define i64 @e(i64 %d) nounwind {
32 %e = add i64 %d, 1
33 %retval = and i64 %e, 65535
34 ret i64 %retval
35}
36define i64 @f(i64 %d) nounwind {
37 %e = add i64 %d, 1
38 %retval = and i64 %e, 4294967295
39 ret i64 %retval
40}
41
42define i32 @g(i8 %d) nounwind {
43 %e = add i8 %d, 1
44 %retval = zext i8 %e to i32
45 ret i32 %retval
46}
47define i32 @h(i16 %d) nounwind {
48 %e = add i16 %d, 1
49 %retval = zext i16 %e to i32
50 ret i32 %retval
51}
52define i64 @i(i8 %d) nounwind {
53 %e = add i8 %d, 1
54 %retval = zext i8 %e to i64
55 ret i64 %retval
56}
57define i64 @j(i16 %d) nounwind {
58 %e = add i16 %d, 1
59 %retval = zext i16 %e to i64
60 ret i64 %retval
61}
62define i64 @k(i32 %d) nounwind {
63 %e = add i32 %d, 1
64 %retval = zext i32 %e to i64
65 ret i64 %retval
66}