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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / c1f7bdcafb0c72ff8eba11dad2b1dccb5951fdbf / . / lib / Target / CellSPU / SPUInstrInfo.td
blob: 2ec14d241b590526670f009d3977e4aae18e7d29 [file] [log] [blame]
Scott Michel8b6b4202007-12-04 22:35:58 +0000[diff] [blame]1//==- SPUInstrInfo.td - Describe the Cell SPU Instructions -*- tablegen -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
Scott Michel43e7c5e2007-12-05 01:40:25 +0000[diff] [blame]5// This file was developed by a team from the Computer Systems Research
6// Department at The Aerospace Corporation and is distributed under the
7// University of Illinois Open Source License. See LICENSE.TXT for details.
Scott Michel8b6b4202007-12-04 22:35:58 +0000[diff] [blame]8//
9//===----------------------------------------------------------------------===//
10// Cell SPU Instructions:
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// TODO Items (not urgent today, but would be nice, low priority)
15//
16// ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
17// concatenating the byte argument b as "bbbb". Could recognize this bit pattern
18// in 16-bit and 32-bit constants and reduce instruction count.
19//===----------------------------------------------------------------------===//
20
21//===----------------------------------------------------------------------===//
22// Pseudo instructions:
23//===----------------------------------------------------------------------===//
24
25let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in {
26 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
27 "${:comment} ADJCALLSTACKDOWN",
28 [(callseq_start imm:$amt)]>;
29 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt),
30 "${:comment} ADJCALLSTACKUP",
31 [(callseq_end imm:$amt)]>;
32}
33
34//===----------------------------------------------------------------------===//
35// DWARF debugging Pseudo Instructions
36//===----------------------------------------------------------------------===//
37
38def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
39 "${:comment} .loc $file, $line, $col",
40 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
41 (i32 imm:$file))]>;
42
43//===----------------------------------------------------------------------===//
44// Loads:
45// NB: The ordering is actually important, since the instruction selection
46// will try each of the instructions in sequence, i.e., the D-form first with
47// the 10-bit displacement, then the A-form with the 16 bit displacement, and
48// finally the X-form with the register-register.
49//===----------------------------------------------------------------------===//
50
51let isLoad = 1 in {
52 def LQDv16i8:
53 RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
54 "lqd\t$rT, $src", LoadStore,
55 [(set (v16i8 VECREG:$rT), (load dform_addr:$src))]>;
56
57 def LQDv8i16:
58 RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
59 "lqd\t$rT, $src", LoadStore,
60 [(set (v8i16 VECREG:$rT), (load dform_addr:$src))]>;
61
62 def LQDv4i32:
63 RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
64 "lqd\t$rT, $src", LoadStore,
65 [(set (v4i32 VECREG:$rT), (load dform_addr:$src))]>;
66
67 def LQDv2i64:
68 RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
69 "lqd\t$rT, $src", LoadStore,
70 [(set (v2i64 VECREG:$rT), (load dform_addr:$src))]>;
71
72 def LQDv4f32:
73 RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
74 "lqd\t$rT, $src", LoadStore,
75 [(set (v4f32 VECREG:$rT), (load dform_addr:$src))]>;
76
77 def LQDv2f64:
78 RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
79 "lqd\t$rT, $src", LoadStore,
80 [(set (v2f64 VECREG:$rT), (load dform_addr:$src))]>;
81
82 def LQDr128:
83 RI10Form<0b00101100, (outs GPRC:$rT), (ins memri10:$src),
84 "lqd\t$rT, $src", LoadStore,
85 [(set GPRC:$rT, (load dform_addr:$src))]>;
86
87 def LQDr64:
88 RI10Form<0b00101100, (outs R64C:$rT), (ins memri10:$src),
89 "lqd\t$rT, $src", LoadStore,
90 [(set R64C:$rT, (load dform_addr:$src))]>;
91
92 def LQDr32:
93 RI10Form<0b00101100, (outs R32C:$rT), (ins memri10:$src),
94 "lqd\t$rT, $src", LoadStore,
95 [(set R32C:$rT, (load dform_addr:$src))]>;
96
97 // Floating Point
98 def LQDf32:
99 RI10Form<0b00101100, (outs R32FP:$rT), (ins memri10:$src),
100 "lqd\t$rT, $src", LoadStore,
101 [(set R32FP:$rT, (load dform_addr:$src))]>;
102
103 def LQDf64:
104 RI10Form<0b00101100, (outs R64FP:$rT), (ins memri10:$src),
105 "lqd\t$rT, $src", LoadStore,
106 [(set R64FP:$rT, (load dform_addr:$src))]>;
107 // END Floating Point
108
109 def LQDr16:
110 RI10Form<0b00101100, (outs R16C:$rT), (ins memri10:$src),
111 "lqd\t$rT, $src", LoadStore,
112 [(set R16C:$rT, (load dform_addr:$src))]>;
113
114 def LQAv16i8:
115 RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
116 "lqa\t$rT, $src", LoadStore,
117 [(set (v16i8 VECREG:$rT), (load aform_addr:$src))]>;
118
119 def LQAv8i16:
120 RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
121 "lqa\t$rT, $src", LoadStore,
122 [(set (v8i16 VECREG:$rT), (load aform_addr:$src))]>;
123
124 def LQAv4i32:
125 RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
126 "lqa\t$rT, $src", LoadStore,
127 [(set (v4i32 VECREG:$rT), (load aform_addr:$src))]>;
128
129 def LQAv2i64:
130 RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
131 "lqa\t$rT, $src", LoadStore,
132 [(set (v2i64 VECREG:$rT), (load aform_addr:$src))]>;
133
134 def LQAv4f32:
135 RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
136 "lqa\t$rT, $src", LoadStore,
137 [(set (v4f32 VECREG:$rT), (load aform_addr:$src))]>;
138
139 def LQAv2f64:
140 RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
141 "lqa\t$rT, $src", LoadStore,
142 [(set (v2f64 VECREG:$rT), (load aform_addr:$src))]>;
143
144 def LQAr128:
145 RI16Form<0b100001100, (outs GPRC:$rT), (ins addr256k:$src),
146 "lqa\t$rT, $src", LoadStore,
147 [(set GPRC:$rT, (load aform_addr:$src))]>;
148
149 def LQAr64:
150 RI16Form<0b100001100, (outs R64C:$rT), (ins addr256k:$src),
151 "lqa\t$rT, $src", LoadStore,
152 [(set R64C:$rT, (load aform_addr:$src))]>;
153
154 def LQAr32:
155 RI16Form<0b100001100, (outs R32C:$rT), (ins addr256k:$src),
156 "lqa\t$rT, $src", LoadStore,
157 [(set R32C:$rT, (load aform_addr:$src))]>;
158
159 def LQAf32:
160 RI16Form<0b100001100, (outs R32FP:$rT), (ins addr256k:$src),
161 "lqa\t$rT, $src", LoadStore,
162 [(set R32FP:$rT, (load aform_addr:$src))]>;
163
164 def LQAf64:
165 RI16Form<0b100001100, (outs R64FP:$rT), (ins addr256k:$src),
166 "lqa\t$rT, $src", LoadStore,
167 [(set R64FP:$rT, (load aform_addr:$src))]>;
168
169 def LQAr16:
170 RI16Form<0b100001100, (outs R16C:$rT), (ins addr256k:$src),
171 "lqa\t$rT, $src", LoadStore,
172 [(set R16C:$rT, (load aform_addr:$src))]>;
173
174 def LQXv16i8:
175 RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
176 "lqx\t$rT, $src", LoadStore,
177 [(set (v16i8 VECREG:$rT), (load xform_addr:$src))]>;
178
179 def LQXv8i16:
180 RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
181 "lqx\t$rT, $src", LoadStore,
182 [(set (v8i16 VECREG:$rT), (load xform_addr:$src))]>;
183
184 def LQXv4i32:
185 RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
186 "lqx\t$rT, $src", LoadStore,
187 [(set (v4i32 VECREG:$rT), (load xform_addr:$src))]>;
188
189 def LQXv2i64:
190 RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
191 "lqx\t$rT, $src", LoadStore,
192 [(set (v2i64 VECREG:$rT), (load xform_addr:$src))]>;
193
194 def LQXv4f32:
195 RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
196 "lqx\t$rT, $src", LoadStore,
197 [(set (v4f32 VECREG:$rT), (load xform_addr:$src))]>;
198
199 def LQXv2f64:
200 RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
201 "lqx\t$rT, $src", LoadStore,
202 [(set (v2f64 VECREG:$rT), (load xform_addr:$src))]>;
203
204 def LQXr128:
205 RRForm<0b00100011100, (outs GPRC:$rT), (ins memrr:$src),
206 "lqx\t$rT, $src", LoadStore,
207 [(set GPRC:$rT, (load xform_addr:$src))]>;
208
209 def LQXr64:
210 RRForm<0b00100011100, (outs R64C:$rT), (ins memrr:$src),
211 "lqx\t$rT, $src", LoadStore,
212 [(set R64C:$rT, (load xform_addr:$src))]>;
213
214 def LQXr32:
215 RRForm<0b00100011100, (outs R32C:$rT), (ins memrr:$src),
216 "lqx\t$rT, $src", LoadStore,
217 [(set R32C:$rT, (load xform_addr:$src))]>;
218
219 def LQXf32:
220 RRForm<0b00100011100, (outs R32FP:$rT), (ins memrr:$src),
221 "lqx\t$rT, $src", LoadStore,
222 [(set R32FP:$rT, (load xform_addr:$src))]>;
223
224 def LQXf64:
225 RRForm<0b00100011100, (outs R64FP:$rT), (ins memrr:$src),
226 "lqx\t$rT, $src", LoadStore,
227 [(set R64FP:$rT, (load xform_addr:$src))]>;
228
229 def LQXr16:
230 RRForm<0b00100011100, (outs R16C:$rT), (ins memrr:$src),
231 "lqx\t$rT, $src", LoadStore,
232 [(set R16C:$rT, (load xform_addr:$src))]>;
233
234/* Load quadword, PC relative: Not much use at this point in time.
235 Might be of use later for relocatable code.
236 def LQR : RI16Form<0b111001100, (outs VECREG:$rT), (ins s16imm:$disp),
237 "lqr\t$rT, $disp", LoadStore,
238 [(set VECREG:$rT, (load iaddr:$disp))]>;
239 */
240
241 // Catch-all for unaligned loads:
242}
243
244//===----------------------------------------------------------------------===//
245// Stores:
246//===----------------------------------------------------------------------===//
247
248let isStore = 1 in {
249 def STQDv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
250 "stqd\t$rT, $src", LoadStore,
251 [(store (v16i8 VECREG:$rT), dform_addr:$src)]>;
252
253 def STQDv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
254 "stqd\t$rT, $src", LoadStore,
255 [(store (v8i16 VECREG:$rT), dform_addr:$src)]>;
256
257 def STQDv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
258 "stqd\t$rT, $src", LoadStore,
259 [(store (v4i32 VECREG:$rT), dform_addr:$src)]>;
260
261 def STQDv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
262 "stqd\t$rT, $src", LoadStore,
263 [(store (v2i64 VECREG:$rT), dform_addr:$src)]>;
264
265 def STQDv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
266 "stqd\t$rT, $src", LoadStore,
267 [(store (v4f32 VECREG:$rT), dform_addr:$src)]>;
268
269 def STQDv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
270 "stqd\t$rT, $src", LoadStore,
271 [(store (v2f64 VECREG:$rT), dform_addr:$src)]>;
272
273 def STQDr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memri10:$src),
274 "stqd\t$rT, $src", LoadStore,
275 [(store GPRC:$rT, dform_addr:$src)]>;
276
277 def STQDr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, memri10:$src),
278 "stqd\t$rT, $src", LoadStore,
279 [(store R64C:$rT, dform_addr:$src)]>;
280
281 def STQDr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, memri10:$src),
282 "stqd\t$rT, $src", LoadStore,
283 [(store R32C:$rT, dform_addr:$src)]>;
284
285 // Floating Point
286 def STQDf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, memri10:$src),
287 "stqd\t$rT, $src", LoadStore,
288 [(store R32FP:$rT, dform_addr:$src)]>;
289
290 def STQDf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, memri10:$src),
291 "stqd\t$rT, $src", LoadStore,
292 [(store R64FP:$rT, dform_addr:$src)]>;
293
294 def STQDr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, memri10:$src),
295 "stqd\t$rT, $src", LoadStore,
296 [(store R16C:$rT, dform_addr:$src)]>;
297
298 def STQAv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
299 "stqa\t$rT, $src", LoadStore,
300 [(store (v16i8 VECREG:$rT), aform_addr:$src)]>;
301
302 def STQAv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
303 "stqa\t$rT, $src", LoadStore,
304 [(store (v8i16 VECREG:$rT), aform_addr:$src)]>;
305
306 def STQAv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
307 "stqa\t$rT, $src", LoadStore,
308 [(store (v4i32 VECREG:$rT), aform_addr:$src)]>;
309
310 def STQAv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
311 "stqa\t$rT, $src", LoadStore,
312 [(store (v2i64 VECREG:$rT), aform_addr:$src)]>;
313
314 def STQAv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
315 "stqa\t$rT, $src", LoadStore,
316 [(store (v4f32 VECREG:$rT), aform_addr:$src)]>;
317
318 def STQAv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
319 "stqa\t$rT, $src", LoadStore,
320 [(store (v2f64 VECREG:$rT), aform_addr:$src)]>;
321
322 def STQAr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, addr256k:$src),
323 "stqa\t$rT, $src", LoadStore,
324 [(store GPRC:$rT, aform_addr:$src)]>;
325
326 def STQAr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, addr256k:$src),
327 "stqa\t$rT, $src", LoadStore,
328 [(store R64C:$rT, aform_addr:$src)]>;
329
330 def STQAr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, addr256k:$src),
331 "stqa\t$rT, $src", LoadStore,
332 [(store R32C:$rT, aform_addr:$src)]>;
333
334 // Floating Point
335 def STQAf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, addr256k:$src),
336 "stqa\t$rT, $src", LoadStore,
337 [(store R32FP:$rT, aform_addr:$src)]>;
338
339 def STQAf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, addr256k:$src),
340 "stqa\t$rT, $src", LoadStore,
341 [(store R64FP:$rT, aform_addr:$src)]>;
342
343 def STQXv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
344 "stqx\t$rT, $src", LoadStore,
345 [(store (v16i8 VECREG:$rT), xform_addr:$src)]>;
346
347 def STQXv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
348 "stqx\t$rT, $src", LoadStore,
349 [(store (v8i16 VECREG:$rT), xform_addr:$src)]>;
350
351 def STQXv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
352 "stqx\t$rT, $src", LoadStore,
353 [(store (v4i32 VECREG:$rT), xform_addr:$src)]>;
354
355 def STQXv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
356 "stqx\t$rT, $src", LoadStore,
357 [(store (v2i64 VECREG:$rT), xform_addr:$src)]>;
358
359 def STQXv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
360 "stqx\t$rT, $src", LoadStore,
361 [(store (v4f32 VECREG:$rT), xform_addr:$src)]>;
362
363 def STQXv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
364 "stqx\t$rT, $src", LoadStore,
365 [(store (v2f64 VECREG:$rT), xform_addr:$src)]>;
366
367 def STQXr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memrr:$src),
368 "stqx\t$rT, $src", LoadStore,
369 [(store GPRC:$rT, xform_addr:$src)]>;
370
371 def STQXr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, memrr:$src),
372 "stqx\t$rT, $src", LoadStore,
373 [(store R64C:$rT, xform_addr:$src)]>;
374
375 def STQXr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, memrr:$src),
376 "stqx\t$rT, $src", LoadStore,
377 [(store R32C:$rT, xform_addr:$src)]>;
378
379 // Floating Point
380 def STQXf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, memrr:$src),
381 "stqx\t$rT, $src", LoadStore,
382 [(store R32FP:$rT, xform_addr:$src)]>;
383
384 def STQXf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, memrr:$src),
385 "stqx\t$rT, $src", LoadStore,
386 [(store R64FP:$rT, xform_addr:$src)]>;
387
388 def STQXr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, memrr:$src),
389 "stqx\t$rT, $src", LoadStore,
390 [(store R16C:$rT, xform_addr:$src)]>;
391
392/* Store quadword, PC relative: Not much use at this point in time. Might
393 be useful for relocatable code.
394 def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
395 "stqr\t$rT, $disp", LoadStore,
396 [(store VECREG:$rT, iaddr:$disp)]>;
397 */
398}
399
400//===----------------------------------------------------------------------===//
401// Generate Controls for Insertion:
402//===----------------------------------------------------------------------===//
403
404def CBD :
405 RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
406 "cbd\t$rT, $src", ShuffleOp,
407 [(set (v16i8 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
408
409def CBX : RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src),
410 "cbx\t$rT, $src", ShuffleOp,
411 [(set (v16i8 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
412
413def CHD : RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
414 "chd\t$rT, $src", ShuffleOp,
415 [(set (v8i16 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
416
417def CHX : RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src),
418 "chx\t$rT, $src", ShuffleOp,
419 [(set (v8i16 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
420
421def CWD : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
422 "cwd\t$rT, $src", ShuffleOp,
423 [(set (v4i32 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
424
425def CWX : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
426 "cwx\t$rT, $src", ShuffleOp,
427 [(set (v4i32 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
428
429def CDD : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
430 "cdd\t$rT, $src", ShuffleOp,
431 [(set (v2i64 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
432
433def CDX : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
434 "cdx\t$rT, $src", ShuffleOp,
435 [(set (v2i64 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
436
437//===----------------------------------------------------------------------===//
438// Constant formation:
439//===----------------------------------------------------------------------===//
440
441def ILHv8i16:
442 RI16Form<0b110000010, (outs VECREG:$rT), (ins s16imm:$val),
443 "ilh\t$rT, $val", ImmLoad,
444 [(set (v8i16 VECREG:$rT), (v8i16 v8i16SExt16Imm:$val))]>;
445
446def ILHr16:
447 RI16Form<0b110000010, (outs R16C:$rT), (ins s16imm:$val),
448 "ilh\t$rT, $val", ImmLoad,
449 [(set R16C:$rT, immSExt16:$val)]>;
450
451// IL does sign extension!
452def ILr64:
453 RI16Form<0b100000010, (outs R64C:$rT), (ins s16imm_i64:$val),
454 "il\t$rT, $val", ImmLoad,
455 [(set R64C:$rT, immSExt16:$val)]>;
456
457def ILv2i64:
458 RI16Form<0b100000010, (outs VECREG:$rT), (ins s16imm_i64:$val),
459 "il\t$rT, $val", ImmLoad,
460 [(set VECREG:$rT, (v2i64 v2i64SExt16Imm:$val))]>;
461
462def ILv4i32:
463 RI16Form<0b100000010, (outs VECREG:$rT), (ins s16imm:$val),
464 "il\t$rT, $val", ImmLoad,
465 [(set VECREG:$rT, (v4i32 v4i32SExt16Imm:$val))]>;
466
467def ILr32:
468 RI16Form<0b100000010, (outs R32C:$rT), (ins s16imm_i32:$val),
469 "il\t$rT, $val", ImmLoad,
470 [(set R32C:$rT, immSExt16:$val)]>;
471
472def ILf32:
473 RI16Form<0b100000010, (outs R32FP:$rT), (ins s16imm_f32:$val),
474 "il\t$rT, $val", ImmLoad,
475 [(set R32FP:$rT, (SPUFPconstant fpimmSExt16:$val))]>;
476
477def ILf64:
478 RI16Form<0b100000010, (outs R64FP:$rT), (ins s16imm_f64:$val),
479 "il\t$rT, $val", ImmLoad,
480 [(set R64FP:$rT, (SPUFPconstant fpimmSExt16:$val))]>;
481
482def ILHUv4i32:
483 RI16Form<0b010000010, (outs VECREG:$rT), (ins u16imm:$val),
484 "ilhu\t$rT, $val", ImmLoad,
485 [(set VECREG:$rT, (v4i32 immILHUvec:$val))]>;
486
487def ILHUr32:
488 RI16Form<0b010000010, (outs R32C:$rT), (ins u16imm:$val),
489 "ilhu\t$rT, $val", ImmLoad,
490 [(set R32C:$rT, hi16:$val)]>;
491
492// ILHUf32: Used to custom lower float constant loads
493def ILHUf32:
494 RI16Form<0b010000010, (outs R32FP:$rT), (ins f16imm:$val),
495 "ilhu\t$rT, $val", ImmLoad,
496 [(set R32FP:$rT, (SPUFPconstant hi16_f32:$val))]>;
497
498// ILHUhi: Used for loading high portion of an address. Note the symbolHi
499// printer used for the operand.
500def ILHUhi : RI16Form<0b010000010, (outs R32C:$rT), (ins symbolHi:$val),
501 "ilhu\t$rT, $val", ImmLoad,
502 [(set R32C:$rT, hi16:$val)]>;
503
504// Immediate load address (can also be used to load 18-bit unsigned constants,
505// see the zext 16->32 pattern)
506def ILAr64:
507 RI18Form<0b1000010, (outs R64C:$rT), (ins u18imm_i64:$val),
508 "ila\t$rT, $val", LoadNOP,
509 [(set R64C:$rT, imm18:$val)]>;
510
511// TODO: ILAv2i64
512
513def ILAv2i64:
514 RI18Form<0b1000010, (outs VECREG:$rT), (ins u18imm:$val),
515 "ila\t$rT, $val", LoadNOP,
516 [(set (v2i64 VECREG:$rT), v2i64Uns18Imm:$val)]>;
517
518def ILAv4i32:
519 RI18Form<0b1000010, (outs VECREG:$rT), (ins u18imm:$val),
520 "ila\t$rT, $val", LoadNOP,
521 [(set (v4i32 VECREG:$rT), v4i32Uns18Imm:$val)]>;
522
523def ILAr32:
524 RI18Form<0b1000010, (outs R32C:$rT), (ins u18imm:$val),
525 "ila\t$rT, $val", LoadNOP,
526 [(set R32C:$rT, imm18:$val)]>;
527
528def ILAf32:
529 RI18Form<0b1000010, (outs R32FP:$rT), (ins f18imm:$val),
530 "ila\t$rT, $val", LoadNOP,
531 [(set R32FP:$rT, (SPUFPconstant fpimm18:$val))]>;
532
533def ILAf64:
534 RI18Form<0b1000010, (outs R64FP:$rT), (ins f18imm_f64:$val),
535 "ila\t$rT, $val", LoadNOP,
536 [(set R64FP:$rT, (SPUFPconstant fpimm18:$val))]>;
537
538def ILAlo:
539 RI18Form<0b1000010, (outs R32C:$rT), (ins symbolLo:$val),
540 "ila\t$rT, $val", ImmLoad,
541 [(set R32C:$rT, imm18:$val)]>;
542
543def ILAlsa:
544 RI18Form<0b1000010, (outs R32C:$rT), (ins symbolLSA:$val),
545 "ila\t$rT, $val", ImmLoad,
546 [/* no pattern */]>;
547
548// Immediate OR, Halfword Lower: The "other" part of loading large constants
549// into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...>
550// Note that these are really two operand instructions, but they're encoded
551// as three operands with the first two arguments tied-to each other.
552
553def IOHLvec:
554 RI16Form<0b100000110, (outs VECREG:$rT), (ins VECREG:$rS, u16imm:$val),
555 "iohl\t$rT, $val", ImmLoad,
556 [/* insert intrinsic here */]>,
557 RegConstraint<"$rS = $rT">,
558 NoEncode<"$rS">;
559
560def IOHLr32:
561 RI16Form<0b100000110, (outs R32C:$rT), (ins R32C:$rS, i32imm:$val),
562 "iohl\t$rT, $val", ImmLoad,
563 [/* insert intrinsic here */]>,
564 RegConstraint<"$rS = $rT">,
565 NoEncode<"$rS">;
566
567def IOHLf32:
568 RI16Form<0b100000110, (outs R32FP:$rT), (ins R32FP:$rS, f32imm:$val),
569 "iohl\t$rT, $val", ImmLoad,
570 [/* insert intrinsic here */]>,
571 RegConstraint<"$rS = $rT">,
572 NoEncode<"$rS">;
573
574// Form select mask for bytes using immediate, used in conjunction with the
575// SELB instruction:
576
577def FSMBIv16i8 : RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
578 "fsmbi\t$rT, $val", SelectOp,
579 [(set (v16i8 VECREG:$rT), (SPUfsmbi_v16i8 immU16:$val))]>;
580
581def FSMBIv8i16 : RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
582 "fsmbi\t$rT, $val", SelectOp,
583 [(set (v8i16 VECREG:$rT), (SPUfsmbi_v8i16 immU16:$val))]>;
584
585def FSMBIvecv4i32 : RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
586 "fsmbi\t$rT, $val", SelectOp,
587 [(set (v4i32 VECREG:$rT), (SPUfsmbi_v4i32 immU16:$val))]>;
588
589//===----------------------------------------------------------------------===//
590// Integer and Logical Operations:
591//===----------------------------------------------------------------------===//
592
593def AHv8i16:
594 RRForm<0b00010011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
595 "ah\t$rT, $rA, $rB", IntegerOp,
596 [(set (v8i16 VECREG:$rT), (int_spu_si_ah VECREG:$rA, VECREG:$rB))]>;
597
598def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
599 (AHv8i16 VECREG:$rA, VECREG:$rB)>;
600
601// [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
602
603def AHr16:
604 RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
605 "ah\t$rT, $rA, $rB", IntegerOp,
606 [(set R16C:$rT, (add R16C:$rA, R16C:$rB))]>;
607
608def AHIvec:
609 RI10Form<0b10111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
610 "ahi\t$rT, $rA, $val", IntegerOp,
611 [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA),
612 v8i16SExt10Imm:$val))]>;
613
614def AHIr16 : RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
615 "ahi\t$rT, $rA, $val", IntegerOp,
616 [(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>;
617
618def Avec : RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
619 "a\t$rT, $rA, $rB", IntegerOp,
620 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
621
622def : Pat<(add (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
623 (Avec VECREG:$rA, VECREG:$rB)>;
624
625def Ar32 : RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
626 "a\t$rT, $rA, $rB", IntegerOp,
627 [(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>;
628
629def AIvec:
630 RI10Form<0b00111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
631 "ai\t$rT, $rA, $val", IntegerOp,
632 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA),
633 v4i32SExt10Imm:$val))]>;
634
635def AIr32 : RI10Form<0b00111000, (outs R32C:$rT),
636 (ins R32C:$rA, s10imm_i32:$val),
637 "ai\t$rT, $rA, $val", IntegerOp,
638 [(set R32C:$rT, (add R32C:$rA, i32ImmSExt10:$val))]>;
639
640def SFHvec : RRForm<0b00010010000, (outs VECREG:$rT),
641 (ins VECREG:$rA, VECREG:$rB),
642 "sfh\t$rT, $rA, $rB", IntegerOp,
643 [(set (v8i16 VECREG:$rT), (sub (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
644
645def SFHr16 : RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
646 "sfh\t$rT, $rA, $rB", IntegerOp,
647 [(set R16C:$rT, (sub R16C:$rA, R16C:$rB))]>;
648
649def SFHIvec:
650 RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
651 "sfhi\t$rT, $rA, $val", IntegerOp,
652 [(set (v8i16 VECREG:$rT), (sub v8i16SExt10Imm:$val,
653 (v8i16 VECREG:$rA)))]>;
654
655def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
656 "sfhi\t$rT, $rA, $val", IntegerOp,
657 [(set R16C:$rT, (sub i16ImmSExt10:$val, R16C:$rA))]>;
658
659def SFvec : RRForm<0b00000010000, (outs VECREG:$rT),
660 (ins VECREG:$rA, VECREG:$rB),
661 "sf\t$rT, $rA, $rB", IntegerOp,
662 [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
663
664def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
665 "sf\t$rT, $rA, $rB", IntegerOp,
666 [(set R32C:$rT, (sub R32C:$rA, R32C:$rB))]>;
667
668def SFIvec:
669 RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
670 "sfi\t$rT, $rA, $val", IntegerOp,
671 [(set (v4i32 VECREG:$rT), (sub v4i32SExt10Imm:$val,
672 (v4i32 VECREG:$rA)))]>;
673
674def SFIr32 : RI10Form<0b00110000, (outs R32C:$rT),
675 (ins R32C:$rA, s10imm_i32:$val),
676 "sfi\t$rT, $rA, $val", IntegerOp,
677 [(set R32C:$rT, (sub i32ImmSExt10:$val, R32C:$rA))]>;
678
679// ADDX: only available in vector form, doesn't match a pattern.
680def ADDXvec:
681 RRForm<0b00000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
682 VECREG:$rCarry),
683 "addx\t$rT, $rA, $rB", IntegerOp,
684 []>,
685 RegConstraint<"$rCarry = $rT">,
686 NoEncode<"$rCarry">;
687
688// CG: only available in vector form, doesn't match a pattern.
689def CGvec:
690 RRForm<0b01000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
691 VECREG:$rCarry),
692 "cg\t$rT, $rA, $rB", IntegerOp,
693 []>,
694 RegConstraint<"$rCarry = $rT">,
695 NoEncode<"$rCarry">;
696
697// SFX: only available in vector form, doesn't match a pattern
698def SFXvec:
699 RRForm<0b10000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
700 VECREG:$rCarry),
701 "sfx\t$rT, $rA, $rB", IntegerOp,
702 []>,
703 RegConstraint<"$rCarry = $rT">,
704 NoEncode<"$rCarry">;
705
706// BG: only available in vector form, doesn't match a pattern.
707def BGvec:
708 RRForm<0b01000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
709 VECREG:$rCarry),
710 "bg\t$rT, $rA, $rB", IntegerOp,
711 []>,
712 RegConstraint<"$rCarry = $rT">,
713 NoEncode<"$rCarry">;
714
715// BGX: only available in vector form, doesn't match a pattern.
716def BGXvec:
717 RRForm<0b11000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
718 VECREG:$rCarry),
719 "bgx\t$rT, $rA, $rB", IntegerOp,
720 []>,
721 RegConstraint<"$rCarry = $rT">,
722 NoEncode<"$rCarry">;
723
724// Halfword multiply variants:
725// N.B: These can be used to build up larger quantities (16x16 -> 32)
726
727def MPYv8i16:
728 RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
729 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
730 [(set (v8i16 VECREG:$rT), (SPUmpy_v8i16 (v8i16 VECREG:$rA),
731 (v8i16 VECREG:$rB)))]>;
732
733def MPYr16:
734 RRForm<0b00100011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
735 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
736 [(set R16C:$rT, (mul R16C:$rA, R16C:$rB))]>;
737
738def MPYUv4i32:
739 RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
740 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
741 [(set (v4i32 VECREG:$rT),
742 (SPUmpyu_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
743
744def MPYUr16:
745 RRForm<0b00110011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
746 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
747 [(set R32C:$rT, (mul (zext R16C:$rA),
748 (zext R16C:$rB)))]>;
749
750def MPYUr32:
751 RRForm<0b00110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
752 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
753 [(set R32C:$rT, (SPUmpyu_i32 R32C:$rA, R32C:$rB))]>;
754
755// mpyi: multiply 16 x s10imm -> 32 result (custom lowering for 32 bit result,
756// this only produces the lower 16 bits)
757def MPYIvec:
758 RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
759 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
760 [(set (v8i16 VECREG:$rT), (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
761
762def MPYIr16:
763 RI10Form<0b00101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
764 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
765 [(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>;
766
767// mpyui: same issues as other multiplies, plus, this doesn't match a
768// pattern... but may be used during target DAG selection or lowering
769def MPYUIvec:
770 RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
771 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
772 []>;
773
774def MPYUIr16:
775 RI10Form<0b10101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
776 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
777 []>;
778
779// mpya: 16 x 16 + 16 -> 32 bit result
780def MPYAvec:
781 RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
782 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
783 [(set (v4i32 VECREG:$rT), (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA),
784 (v8i16 VECREG:$rB)))),
785 (v4i32 VECREG:$rC)))]>;
786
787def MPYAr32:
788 RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
789 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
790 [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
791 R32C:$rC))]>;
792
793def : Pat<(add (mul (sext R16C:$rA), (sext R16C:$rB)), R32C:$rC),
794 (MPYAr32 R16C:$rA, R16C:$rB, R32C:$rC)>;
795
796def MPYAr32_sextinreg:
797 RRRForm<0b0011, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
798 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
799 [(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16),
800 (sext_inreg R32C:$rB, i16)),
801 R32C:$rC))]>;
802
803//def MPYAr32:
804// RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
805// "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
806// [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
807// R32C:$rC))]>;
808
809// mpyh: multiply high, used to synthesize 32-bit multiplies
810def MPYHv4i32:
811 RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
812 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
813 [(set (v4i32 VECREG:$rT),
814 (SPUmpyh_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
815
816def MPYHr32:
817 RRForm<0b10100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
818 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
819 [(set R32C:$rT, (SPUmpyh_i32 R32C:$rA, R32C:$rB))]>;
820
821// mpys: multiply high and shift right (returns the top half of
822// a 16-bit multiply, sign extended to 32 bits.)
823def MPYSvec:
824 RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
825 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
826 []>;
827
828def MPYSr16:
829 RRForm<0b11100011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
830 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
831 []>;
832
833// mpyhh: multiply high-high (returns the 32-bit result from multiplying
834// the top 16 bits of the $rA, $rB)
835def MPYHHv8i16:
836 RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
837 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
838 [(set (v8i16 VECREG:$rT),
839 (SPUmpyhh_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
840
841def MPYHHr32:
842 RRForm<0b01100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
843 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
844 []>;
845
846// mpyhha: Multiply high-high, add to $rT:
847def MPYHHAvec:
848 RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
849 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
850 []>;
851
852def MPYHHAr32:
853 RRForm<0b01100010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
854 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
855 []>;
856
857// mpyhhu: Multiply high-high, unsigned
858def MPYHHUvec:
859 RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
860 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
861 []>;
862
863def MPYHHUr32:
864 RRForm<0b01110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
865 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
866 []>;
867
868// mpyhhau: Multiply high-high, unsigned
869def MPYHHAUvec:
870 RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
871 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
872 []>;
873
874def MPYHHAUr32:
875 RRForm<0b01110010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
876 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
877 []>;
878
879// clz: Count leading zeroes
880def CLZv4i32:
881 RRForm_1<0b10100101010, (outs VECREG:$rT), (ins VECREG:$rA),
882 "clz\t$rT, $rA", IntegerOp,
883 [/* intrinsic */]>;
884
885def CLZr32:
886 RRForm_1<0b10100101010, (outs R32C:$rT), (ins R32C:$rA),
887 "clz\t$rT, $rA", IntegerOp,
888 [(set R32C:$rT, (ctlz R32C:$rA))]>;
889
890// cntb: Count ones in bytes (aka "population count")
891// NOTE: This instruction is really a vector instruction, but the custom
892// lowering code uses it in unorthodox ways to support CTPOP for other
893// data types!
894def CNTBv16i8:
895 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
896 "cntb\t$rT, $rA", IntegerOp,
897 [(set (v16i8 VECREG:$rT), (SPUcntb_v16i8 (v16i8 VECREG:$rA)))]>;
898
899def CNTBv8i16 :
900 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
901 "cntb\t$rT, $rA", IntegerOp,
902 [(set (v8i16 VECREG:$rT), (SPUcntb_v8i16 (v8i16 VECREG:$rA)))]>;
903
904def CNTBv4i32 :
905 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
906 "cntb\t$rT, $rA", IntegerOp,
907 [(set (v4i32 VECREG:$rT), (SPUcntb_v4i32 (v4i32 VECREG:$rA)))]>;
908
909// fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
910def FSMB:
911 RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA),
912 "fsmb\t$rT, $rA", SelectOp,
913 []>;
914
915// fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
916// only 8-bits wide (even though it's input as 16-bits here)
917def FSMH:
918 RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA),
919 "fsmh\t$rT, $rA", SelectOp,
920 []>;
921
922// fsm: Form select mask for words. Like the other fsm* instructions,
923// only the lower 4 bits of $rA are significant.
924def FSM:
925 RRForm_1<0b00101101100, (outs VECREG:$rT), (ins R16C:$rA),
926 "fsm\t$rT, $rA", SelectOp,
927 []>;
928
929// gbb: Gather all low order bits from each byte in $rA into a single 16-bit
930// quantity stored into $rT
931def GBB:
932 RRForm_1<0b01001101100, (outs R16C:$rT), (ins VECREG:$rA),
933 "gbb\t$rT, $rA", GatherOp,
934 []>;
935
936// gbh: Gather all low order bits from each halfword in $rA into a single
937// 8-bit quantity stored in $rT
938def GBH:
939 RRForm_1<0b10001101100, (outs R16C:$rT), (ins VECREG:$rA),
940 "gbh\t$rT, $rA", GatherOp,
941 []>;
942
943// gb: Gather all low order bits from each word in $rA into a single
944// 4-bit quantity stored in $rT
945def GB:
946 RRForm_1<0b00001101100, (outs R16C:$rT), (ins VECREG:$rA),
947 "gb\t$rT, $rA", GatherOp,
948 []>;
949
950// avgb: average bytes
951def AVGB:
952 RRForm<0b11001011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
953 "avgb\t$rT, $rA, $rB", ByteOp,
954 []>;
955
956// absdb: absolute difference of bytes
957def ABSDB:
958 RRForm<0b11001010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
959 "absdb\t$rT, $rA, $rB", ByteOp,
960 []>;
961
962// sumb: sum bytes into halfwords
963def SUMB:
964 RRForm<0b11001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
965 "sumb\t$rT, $rA, $rB", ByteOp,
966 []>;
967
968// Sign extension operations:
969def XSBHvec:
970 RRForm_1<0b01101101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
971 "xsbh\t$rDst, $rSrc", IntegerOp,
972 [(set (v8i16 VECREG:$rDst), (sext (v16i8 VECREG:$rSrc)))]>;
973
974// Ordinary form for XSBH
975def XSBHr16:
976 RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R16C:$rSrc),
977 "xsbh\t$rDst, $rSrc", IntegerOp,
978 [(set R16C:$rDst, (sext_inreg R16C:$rSrc, i8))]>;
979
980// 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit
981// quantities to 32-bit quantities via a 32-bit register (see the sext 8->32
982// pattern below). Intentionally doesn't match a pattern because we want the
983// sext 8->32 pattern to do the work for us, namely because we need the extra
984// XSHWr32.
985def XSBHr32:
986 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
987 "xsbh\t$rDst, $rSrc", IntegerOp,
988 [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i8))]>;
989
990// Sign extend halfwords to words:
991def XSHWvec:
992 RRForm_1<0b01101101010, (outs VECREG:$rDest), (ins VECREG:$rSrc),
993 "xshw\t$rDest, $rSrc", IntegerOp,
994 [(set (v4i32 VECREG:$rDest), (sext (v8i16 VECREG:$rSrc)))]>;
995
996def XSHWr32:
997 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
998 "xshw\t$rDst, $rSrc", IntegerOp,
999 [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i16))]>;
1000
1001def XSHWr16:
1002 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R16C:$rSrc),
1003 "xshw\t$rDst, $rSrc", IntegerOp,
1004 [(set R32C:$rDst, (sext R16C:$rSrc))]>;
1005
1006def XSWDvec:
1007 RRForm_1<0b01100101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
1008 "xswd\t$rDst, $rSrc", IntegerOp,
1009 [(set (v2i64 VECREG:$rDst), (sext (v4i32 VECREG:$rSrc)))]>;
1010
1011def XSWDr64:
1012 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R64C:$rSrc),
1013 "xswd\t$rDst, $rSrc", IntegerOp,
1014 [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>;
1015
1016def XSWDr32:
1017 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R32C:$rSrc),
1018 "xswd\t$rDst, $rSrc", IntegerOp,
1019 [(set R64C:$rDst, (SPUsext32_to_64 R32C:$rSrc))]>;
1020
1021def : Pat<(sext R32C:$inp),
1022 (XSWDr32 R32C:$inp)>;
1023
1024// AND operations
1025def ANDv16i8:
1026 RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1027 "and\t$rT, $rA, $rB", IntegerOp,
1028 [(set (v16i8 VECREG:$rT), (and (v16i8 VECREG:$rA),
1029 (v16i8 VECREG:$rB)))]>;
1030
1031def ANDv8i16:
1032 RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1033 "and\t$rT, $rA, $rB", IntegerOp,
1034 [(set (v8i16 VECREG:$rT), (and (v8i16 VECREG:$rA),
1035 (v8i16 VECREG:$rB)))]>;
1036
1037def ANDv4i32:
1038 RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1039 "and\t$rT, $rA, $rB", IntegerOp,
1040 [(set (v4i32 VECREG:$rT), (and (v4i32 VECREG:$rA),
1041 (v4i32 VECREG:$rB)))]>;
1042
1043def ANDr32:
1044 RRForm<0b10000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1045 "and\t$rT, $rA, $rB", IntegerOp,
1046 [(set R32C:$rT, (and R32C:$rA, R32C:$rB))]>;
1047
1048//===---------------------------------------------
1049// Special instructions to perform the fabs instruction
1050def ANDfabs32:
1051 RRForm<0b10000011000, (outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1052 "and\t$rT, $rA, $rB", IntegerOp,
1053 [/* Intentionally does not match a pattern */]>;
1054
1055def ANDfabs64:
1056 RRForm<0b10000011000, (outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1057 "and\t$rT, $rA, $rB", IntegerOp,
1058 [/* Intentionally does not match a pattern */]>;
1059
1060// Could use ANDv4i32, but won't for clarity
1061def ANDfabsvec:
1062 RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1063 "and\t$rT, $rA, $rB", IntegerOp,
1064 [/* Intentionally does not match a pattern */]>;
1065
1066//===---------------------------------------------
1067
1068def ANDr16:
1069 RRForm<0b10000011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1070 "and\t$rT, $rA, $rB", IntegerOp,
1071 [(set R16C:$rT, (and R16C:$rA, R16C:$rB))]>;
1072
1073// Hacked form of AND to zero-extend 16-bit quantities to 32-bit
1074// quantities -- see 16->32 zext pattern.
1075//
1076// This pattern is somewhat artificial, since it might match some
1077// compiler generated pattern but it is unlikely to do so.
1078def AND2To4:
1079 RRForm<0b10000011000, (outs R32C:$rT), (ins R16C:$rA, R32C:$rB),
1080 "and\t$rT, $rA, $rB", IntegerOp,
1081 [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>;
1082
1083// N.B.: vnot_conv is one of those special target selection pattern fragments,
1084// in which we expect there to be a bit_convert on the constant. Bear in mind
1085// that llvm translates "not <reg>" to "xor <reg>, -1" (or in this case, a
1086// constant -1 vector.)
1087def ANDCv16i8:
1088 RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1089 "andc\t$rT, $rA, $rB", IntegerOp,
1090 [(set (v16i8 VECREG:$rT), (and (v16i8 VECREG:$rA),
1091 (vnot (v16i8 VECREG:$rB))))]>;
1092
1093def ANDCv8i16:
1094 RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1095 "andc\t$rT, $rA, $rB", IntegerOp,
1096 [(set (v8i16 VECREG:$rT), (and (v8i16 VECREG:$rA),
1097 (vnot (v8i16 VECREG:$rB))))]>;
1098
1099def ANDCv4i32:
1100 RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1101 "andc\t$rT, $rA, $rB", IntegerOp,
1102 [(set (v4i32 VECREG:$rT), (and (v4i32 VECREG:$rA),
1103 (vnot (v4i32 VECREG:$rB))))]>;
1104
1105def ANDCr32:
1106 RRForm<0b10000011010, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1107 "andc\t$rT, $rA, $rB", IntegerOp,
1108 [(set R32C:$rT, (and R32C:$rA, (not R32C:$rB)))]>;
1109
1110def ANDCr16:
1111 RRForm<0b10000011010, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1112 "andc\t$rT, $rA, $rB", IntegerOp,
1113 [(set R16C:$rT, (and R16C:$rA, (not R16C:$rB)))]>;
1114
1115def ANDBIv16i8:
1116 RI10Form<0b01101000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1117 "andbi\t$rT, $rA, $val", IntegerOp,
1118 [(set (v16i8 VECREG:$rT),
1119 (and (v16i8 VECREG:$rA), (v16i8 v16i8U8Imm:$val)))]>;
1120
1121def ANDHIv8i16:
1122 RI10Form<0b10101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1123 "andhi\t$rT, $rA, $val", IntegerOp,
1124 [(set (v8i16 VECREG:$rT),
1125 (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
1126
1127def ANDHIr16:
1128 RI10Form<0b10101000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1129 "andhi\t$rT, $rA, $val", IntegerOp,
Scott Michel7b5f7ed2007-12-15 00:38:50 +0000[diff] [blame]1130 [(set R16C:$rT, (and R16C:$rA, i16ImmU10:$val))]>;
Scott Michel8b6b4202007-12-04 22:35:58 +0000[diff] [blame]1131
1132def ANDIv4i32:
1133 RI10Form<0b00101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1134 "andi\t$rT, $rA, $val", IntegerOp,
1135 [(set (v4i32 VECREG:$rT),
1136 (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>;
1137
1138def ANDIr32:
1139 RI10Form<0b10101000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1140 "andi\t$rT, $rA, $val", IntegerOp,
1141 [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>;
1142
1143// Hacked form of ANDI to zero-extend i16 quantities to i32. See the
1144// zext 16->32 pattern below.
1145//
1146// Note that this pattern is somewhat artificial, since it might match
1147// something the compiler generates but is unlikely to occur in practice.
1148def ANDI2To4:
1149 RI10Form<0b10101000, (outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1150 "andi\t$rT, $rA, $val", IntegerOp,
1151 [(set R32C:$rT, (and (zext R16C:$rA), i32ImmSExt10:$val))]>;
1152
1153// Bitwise OR group:
1154// Bitwise "or" (N.B.: These are also register-register copy instructions...)
1155def ORv16i8:
1156 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1157 "or\t$rT, $rA, $rB", IntegerOp,
1158 [(set (v16i8 VECREG:$rT), (or (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
1159
1160def ORv8i16:
1161 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1162 "or\t$rT, $rA, $rB", IntegerOp,
1163 [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
1164
1165def ORv4i32:
1166 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1167 "or\t$rT, $rA, $rB", IntegerOp,
1168 [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
1169
1170def ORv4f32:
1171 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1172 "or\t$rT, $rA, $rB", IntegerOp,
1173 [(set (v4f32 VECREG:$rT),
1174 (v4f32 (bitconvert (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))))]>;
1175
1176def ORv2f64:
1177 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1178 "or\t$rT, $rA, $rB", IntegerOp,
1179 [(set (v2f64 VECREG:$rT),
1180 (v2f64 (bitconvert (or (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)))))]>;
1181
1182def ORgprc:
1183 RRForm<0b10000010000, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1184 "or\t$rT, $rA, $rB", IntegerOp,
1185 [(set GPRC:$rT, (or GPRC:$rA, GPRC:$rB))]>;
1186
1187def ORr64:
1188 RRForm<0b10000010000, (outs R64C:$rT), (ins R64C:$rA, R64C:$rB),
1189 "or\t$rT, $rA, $rB", IntegerOp,
1190 [(set R64C:$rT, (or R64C:$rA, R64C:$rB))]>;
1191
1192def ORr32:
1193 RRForm<0b10000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1194 "or\t$rT, $rA, $rB", IntegerOp,
1195 [(set R32C:$rT, (or R32C:$rA, R32C:$rB))]>;
1196
1197def ORr16:
1198 RRForm<0b10000010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1199 "or\t$rT, $rA, $rB", IntegerOp,
1200 [(set R16C:$rT, (or R16C:$rA, R16C:$rB))]>;
1201
1202// ORv*_*: Used in scalar->vector promotions:
1203def ORv8i16_i16:
1204 RRForm<0b10000010000, (outs VECREG:$rT), (ins R16C:$rA, R16C:$rB),
1205 "or\t$rT, $rA, $rB", IntegerOp,
1206 [/* no pattern */]>;
1207
1208def : Pat<(v8i16 (SPUpromote_scalar R16C:$rA)),
1209 (ORv8i16_i16 R16C:$rA, R16C:$rA)>;
1210
1211def ORv4i32_i32:
1212 RRForm<0b10000010000, (outs VECREG:$rT), (ins R32C:$rA, R32C:$rB),
1213 "or\t$rT, $rA, $rB", IntegerOp,
1214 [/* no pattern */]>;
1215
1216def : Pat<(v4i32 (SPUpromote_scalar R32C:$rA)),
1217 (ORv4i32_i32 R32C:$rA, R32C:$rA)>;
1218
1219def ORv2i64_i64:
1220 RRForm<0b10000010000, (outs VECREG:$rT), (ins R64C:$rA, R64C:$rB),
1221 "or\t$rT, $rA, $rB", IntegerOp,
1222 [/* no pattern */]>;
1223
1224def : Pat<(v2i64 (SPUpromote_scalar R64C:$rA)),
1225 (ORv2i64_i64 R64C:$rA, R64C:$rA)>;
1226
1227def ORv4f32_f32:
1228 RRForm<0b10000010000, (outs VECREG:$rT), (ins R32FP:$rA, R32FP:$rB),
1229 "or\t$rT, $rA, $rB", IntegerOp,
1230 [/* no pattern */]>;
1231
1232def : Pat<(v4f32 (SPUpromote_scalar R32FP:$rA)),
1233 (ORv4f32_f32 R32FP:$rA, R32FP:$rA)>;
1234
1235def ORv2f64_f64:
1236 RRForm<0b10000010000, (outs VECREG:$rT), (ins R64FP:$rA, R64FP:$rB),
1237 "or\t$rT, $rA, $rB", IntegerOp,
1238 [/* no pattern */]>;
1239
1240def : Pat<(v2f64 (SPUpromote_scalar R64FP:$rA)),
1241 (ORv2f64_f64 R64FP:$rA, R64FP:$rA)>;
1242
1243// ORi*_v*: Used to extract vector element 0 (the preferred slot)
1244def ORi16_v8i16:
1245 RRForm<0b10000010000, (outs R16C:$rT), (ins VECREG:$rA, VECREG:$rB),
1246 "or\t$rT, $rA, $rB", IntegerOp,
1247 [/* no pattern */]>;
1248
1249def : Pat<(SPUextract_elt0 (v8i16 VECREG:$rA)),
1250 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1251
1252def : Pat<(SPUextract_elt0_chained (v8i16 VECREG:$rA)),
1253 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1254
1255def ORi32_v4i32:
1256 RRForm<0b10000010000, (outs R32C:$rT), (ins VECREG:$rA, VECREG:$rB),
1257 "or\t$rT, $rA, $rB", IntegerOp,
1258 [/* no pattern */]>;
1259
1260def : Pat<(SPUextract_elt0 (v4i32 VECREG:$rA)),
1261 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1262
1263def : Pat<(SPUextract_elt0_chained (v4i32 VECREG:$rA)),
1264 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1265
1266def ORi64_v2i64:
1267 RRForm<0b10000010000, (outs R64C:$rT), (ins VECREG:$rA, VECREG:$rB),
1268 "or\t$rT, $rA, $rB", IntegerOp,
1269 [/* no pattern */]>;
1270
1271def : Pat<(SPUextract_elt0 (v2i64 VECREG:$rA)),
1272 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1273
1274def : Pat<(SPUextract_elt0_chained (v2i64 VECREG:$rA)),
1275 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1276
1277def ORf32_v4f32:
1278 RRForm<0b10000010000, (outs R32FP:$rT), (ins VECREG:$rA, VECREG:$rB),
1279 "or\t$rT, $rA, $rB", IntegerOp,
1280 [/* no pattern */]>;
1281
1282def : Pat<(SPUextract_elt0 (v4f32 VECREG:$rA)),
1283 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1284
1285def : Pat<(SPUextract_elt0_chained (v4f32 VECREG:$rA)),
1286 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1287
1288def ORf64_v2f64:
1289 RRForm<0b10000010000, (outs R64FP:$rT), (ins VECREG:$rA, VECREG:$rB),
1290 "or\t$rT, $rA, $rB", IntegerOp,
1291 [/* no pattern */]>;
1292
1293def : Pat<(SPUextract_elt0 (v2f64 VECREG:$rA)),
1294 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1295
1296def : Pat<(SPUextract_elt0_chained (v2f64 VECREG:$rA)),
1297 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1298
1299// ORC: Bitwise "or" with complement (match before ORvec, ORr32)
1300def ORCv16i8:
1301 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1302 "orc\t$rT, $rA, $rB", IntegerOp,
1303 [(set (v16i8 VECREG:$rT), (or (v16i8 VECREG:$rA),
1304 (vnot (v16i8 VECREG:$rB))))]>;
1305
1306def ORCv8i16:
1307 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1308 "orc\t$rT, $rA, $rB", IntegerOp,
1309 [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA),
1310 (vnot (v8i16 VECREG:$rB))))]>;
1311
1312def ORCv4i32:
1313 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1314 "orc\t$rT, $rA, $rB", IntegerOp,
1315 [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA),
1316 (vnot (v4i32 VECREG:$rB))))]>;
1317
1318def ORCr32:
1319 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1320 "orc\t$rT, $rA, $rB", IntegerOp,
1321 [(set R32C:$rT, (or R32C:$rA, (not R32C:$rB)))]>;
1322
1323def ORCr16:
1324 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1325 "orc\t$rT, $rA, $rB", IntegerOp,
1326 [(set R16C:$rT, (or R16C:$rA, (not R16C:$rB)))]>;
1327
1328// OR byte immediate
1329def ORBIv16i8:
1330 RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1331 "orbi\t$rT, $rA, $val", IntegerOp,
1332 [(set (v16i8 VECREG:$rT),
1333 (or (v16i8 VECREG:$rA), (v16i8 v16i8U8Imm:$val)))]>;
1334
1335// OR halfword immediate
1336def ORHIv8i16:
1337 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1338 "orhi\t$rT, $rA, $val", IntegerOp,
1339 [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA),
1340 v8i16SExt10Imm:$val))]>;
1341
1342def ORHIr16:
1343 RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1344 "orhi\t$rT, $rA, $val", IntegerOp,
1345 [(set R16C:$rT, (or R16C:$rA, i16ImmSExt10:$val))]>;
1346
1347// Bitwise "or" with immediate
1348def ORIv4i32:
1349 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1350 "ori\t$rT, $rA, $val", IntegerOp,
1351 [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA),
1352 v4i32SExt10Imm:$val))]>;
1353
1354def ORIr32:
1355 RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1356 "ori\t$rT, $rA, $val", IntegerOp,
1357 [(set R32C:$rT, (or R32C:$rA, i32ImmSExt10:$val))]>;
1358
1359// Hacked forms of or immediate to copy one 32- and 64-bit FP register
1360// to another. Do not match patterns.
1361def ORIf32:
1362 RI10Form_1<0b00100000, (outs R32FP:$rT), (ins R32FP:$rA, s10imm_i32:$val),
1363 "ori\t$rT, $rA, $val", IntegerOp,
1364 [/* no pattern */]>;
1365
1366def ORIf64:
1367 RI10Form_1<0b00100000, (outs R64FP:$rT), (ins R64FP:$rA, s10imm_i32:$val),
1368 "ori\t$rT, $rA, $val", IntegerOp,
1369 [/* no pattern */]>;
1370
1371def ORIr64:
1372 RI10Form_1<0b00100000, (outs R64C:$rT), (ins R64C:$rA, s10imm_i32:$val),
1373 "ori\t$rT, $rA, $val", IntegerOp,
1374 [/* no pattern */]>;
1375
1376// ORI2To4: hacked version of the ori instruction to extend 16-bit quantities
1377// to 32-bit quantities. used exclusively to match "anyext" conversions (vide
1378// infra "anyext 16->32" pattern.)
1379def ORI2To4:
1380 RI10Form<0b00100000, (outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1381 "ori\t$rT, $rA, $val", IntegerOp,
1382 [(set R32C:$rT, (or (anyext R16C:$rA), i32ImmSExt10:$val))]>;
1383
1384// ORX: "or" across the vector: or's $rA's word slots leaving the result in
1385// $rT[0], slots 1-3 are zeroed.
1386//
1387// Needs to match an intrinsic pattern.
1388def ORXv4i32:
1389 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1390 "orx\t$rT, $rA, $rB", IntegerOp,
1391 []>;
1392
1393def XORv16i8:
1394 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1395 "xor\t$rT, $rA, $rB", IntegerOp,
1396 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
1397
1398def XORv8i16:
1399 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1400 "xor\t$rT, $rA, $rB", IntegerOp,
1401 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
1402
1403def XORv4i32:
1404 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1405 "xor\t$rT, $rA, $rB", IntegerOp,
1406 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
1407
1408def XORr32:
1409 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1410 "xor\t$rT, $rA, $rB", IntegerOp,
1411 [(set R32C:$rT, (xor R32C:$rA, R32C:$rB))]>;
1412
1413//==----------------------------------------------------------
1414// Special forms for floating point instructions.
1415// Bitwise ORs and ANDs don't make sense for normal floating
1416// point numbers. These operations (fneg and fabs), however,
1417// require bitwise logical ops to manipulate the sign bit.
1418def XORfneg32:
1419 RRForm<0b10010010000, (outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1420 "xor\t$rT, $rA, $rB", IntegerOp,
1421 [/* Intentionally does not match a pattern, see fneg32 */]>;
1422
1423// KLUDGY! Better way to do this without a VECREG? bitconvert?
1424// VECREG is assumed to contain two identical 64-bit masks, so
1425// it doesn't matter which word we select for the xor
1426def XORfneg64:
1427 RRForm<0b10010010000, (outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1428 "xor\t$rT, $rA, $rB", IntegerOp,
1429 [/* Intentionally does not match a pattern, see fneg64 */]>;
1430
1431// Could use XORv4i32, but will use this for clarity
1432def XORfnegvec:
1433 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1434 "xor\t$rT, $rA, $rB", IntegerOp,
1435 [/* Intentionally does not match a pattern, see fneg{32,64} */]>;
1436
1437//==----------------------------------------------------------
1438
1439def XORr16:
1440 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1441 "xor\t$rT, $rA, $rB", IntegerOp,
1442 [(set R16C:$rT, (xor R16C:$rA, R16C:$rB))]>;
1443
1444def XORBIv16i8:
1445 RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1446 "xorbi\t$rT, $rA, $val", IntegerOp,
1447 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
1448
1449def XORHIv8i16:
1450 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1451 "xorhi\t$rT, $rA, $val", IntegerOp,
1452 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA),
1453 v8i16SExt10Imm:$val))]>;
1454
1455def XORHIr16:
1456 RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1457 "xorhi\t$rT, $rA, $val", IntegerOp,
1458 [(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
1459
1460def XORIv4i32:
1461 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1462 "xori\t$rT, $rA, $val", IntegerOp,
1463 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
1464 v4i32SExt10Imm:$val))]>;
1465
1466def XORIr32:
1467 RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1468 "xori\t$rT, $rA, $val", IntegerOp,
1469 [(set R32C:$rT, (xor R32C:$rA, i32ImmSExt10:$val))]>;
1470
1471// NAND:
1472def NANDv16i8:
1473 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1474 "nand\t$rT, $rA, $rB", IntegerOp,
1475 [(set (v16i8 VECREG:$rT), (vnot (and (v16i8 VECREG:$rA),
1476 (v16i8 VECREG:$rB))))]>;
1477
1478def NANDv8i16:
1479 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1480 "nand\t$rT, $rA, $rB", IntegerOp,
1481 [(set (v8i16 VECREG:$rT), (vnot (and (v8i16 VECREG:$rA),
1482 (v8i16 VECREG:$rB))))]>;
1483
1484def NANDv4i32:
1485 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1486 "nand\t$rT, $rA, $rB", IntegerOp,
1487 [(set (v4i32 VECREG:$rT), (vnot (and (v4i32 VECREG:$rA),
1488 (v4i32 VECREG:$rB))))]>;
1489
1490def NANDr32:
1491 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1492 "nand\t$rT, $rA, $rB", IntegerOp,
1493 [(set R32C:$rT, (not (and R32C:$rA, R32C:$rB)))]>;
1494
1495def NANDr16:
1496 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1497 "nand\t$rT, $rA, $rB", IntegerOp,
1498 [(set R16C:$rT, (not (and R16C:$rA, R16C:$rB)))]>;
1499
1500// NOR:
1501def NORv16i8:
1502 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1503 "nor\t$rT, $rA, $rB", IntegerOp,
1504 [(set (v16i8 VECREG:$rT), (vnot (or (v16i8 VECREG:$rA),
1505 (v16i8 VECREG:$rB))))]>;
1506
1507def NORv8i16:
1508 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1509 "nor\t$rT, $rA, $rB", IntegerOp,
1510 [(set (v8i16 VECREG:$rT), (vnot (or (v8i16 VECREG:$rA),
1511 (v8i16 VECREG:$rB))))]>;
1512
1513def NORv4i32:
1514 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1515 "nor\t$rT, $rA, $rB", IntegerOp,
1516 [(set (v4i32 VECREG:$rT), (vnot (or (v4i32 VECREG:$rA),
1517 (v4i32 VECREG:$rB))))]>;
1518
1519def NORr32:
1520 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1521 "nor\t$rT, $rA, $rB", IntegerOp,
1522 [(set R32C:$rT, (not (or R32C:$rA, R32C:$rB)))]>;
1523
1524def NORr16:
1525 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1526 "nor\t$rT, $rA, $rB", IntegerOp,
1527 [(set R16C:$rT, (not (or R16C:$rA, R16C:$rB)))]>;
1528
1529// EQV: Equivalence (1 for each same bit, otherwise 0)
1530def EQVv16i8:
1531 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1532 "eqv\t$rT, $rA, $rB", IntegerOp,
1533 [(set (v16i8 VECREG:$rT), (or (and (v16i8 VECREG:$rA),
1534 (v16i8 VECREG:$rB)),
1535 (and (vnot (v16i8 VECREG:$rA)),
1536 (vnot (v16i8 VECREG:$rB)))))]>;
1537
1538def : Pat<(xor (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rB))),
1539 (EQVv16i8 VECREG:$rA, VECREG:$rB)>;
1540
1541def : Pat<(xor (vnot (v16i8 VECREG:$rA)), (v16i8 VECREG:$rB)),
1542 (EQVv16i8 VECREG:$rA, VECREG:$rB)>;
1543
1544def EQVv8i16:
1545 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1546 "eqv\t$rT, $rA, $rB", IntegerOp,
1547 [(set (v8i16 VECREG:$rT), (or (and (v8i16 VECREG:$rA),
1548 (v8i16 VECREG:$rB)),
1549 (and (vnot (v8i16 VECREG:$rA)),
1550 (vnot (v8i16 VECREG:$rB)))))]>;
1551
1552def : Pat<(xor (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rB))),
1553 (EQVv8i16 VECREG:$rA, VECREG:$rB)>;
1554
1555def : Pat<(xor (vnot (v8i16 VECREG:$rA)), (v8i16 VECREG:$rB)),
1556 (EQVv8i16 VECREG:$rA, VECREG:$rB)>;
1557
1558def EQVv4i32:
1559 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1560 "eqv\t$rT, $rA, $rB", IntegerOp,
1561 [(set (v4i32 VECREG:$rT), (or (and (v4i32 VECREG:$rA),
1562 (v4i32 VECREG:$rB)),
1563 (and (vnot (v4i32 VECREG:$rA)),
1564 (vnot (v4i32 VECREG:$rB)))))]>;
1565
1566def : Pat<(xor (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rB))),
1567 (EQVv4i32 VECREG:$rA, VECREG:$rB)>;
1568
1569def : Pat<(xor (vnot (v4i32 VECREG:$rA)), (v4i32 VECREG:$rB)),
1570 (EQVv4i32 VECREG:$rA, VECREG:$rB)>;
1571
1572def EQVr32:
1573 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1574 "eqv\t$rT, $rA, $rB", IntegerOp,
1575 [(set R32C:$rT, (or (and R32C:$rA, R32C:$rB),
1576 (and (not R32C:$rA), (not R32C:$rB))))]>;
1577
1578def : Pat<(xor R32C:$rA, (not R32C:$rB)),
1579 (EQVr32 R32C:$rA, R32C:$rB)>;
1580
1581def : Pat<(xor (not R32C:$rA), R32C:$rB),
1582 (EQVr32 R32C:$rA, R32C:$rB)>;
1583
1584def EQVr16:
1585 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1586 "eqv\t$rT, $rA, $rB", IntegerOp,
1587 [(set R16C:$rT, (or (and R16C:$rA, R16C:$rB),
1588 (and (not R16C:$rA), (not R16C:$rB))))]>;
1589
1590def : Pat<(xor R16C:$rA, (not R16C:$rB)),
1591 (EQVr16 R16C:$rA, R16C:$rB)>;
1592
1593def : Pat<(xor (not R16C:$rA), R16C:$rB),
1594 (EQVr16 R16C:$rA, R16C:$rB)>;
1595
1596// gcc optimizes (p & q) | (~p & ~q) -> ~(p | q) | (p & q), so match that
1597// pattern also:
1598def : Pat<(or (vnot (or (v16i8 VECREG:$rA), (v16i8 VECREG:$rB))),
1599 (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rB))),
1600 (EQVv16i8 VECREG:$rA, VECREG:$rB)>;
1601
1602def : Pat<(or (vnot (or (v8i16 VECREG:$rA), (v8i16 VECREG:$rB))),
1603 (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rB))),
1604 (EQVv8i16 VECREG:$rA, VECREG:$rB)>;
1605
1606def : Pat<(or (vnot (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB))),
1607 (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rB))),
1608 (EQVv4i32 VECREG:$rA, VECREG:$rB)>;
1609
1610def : Pat<(or (not (or R32C:$rA, R32C:$rB)), (and R32C:$rA, R32C:$rB)),
1611 (EQVr32 R32C:$rA, R32C:$rB)>;
1612
1613def : Pat<(or (not (or R16C:$rA, R16C:$rB)), (and R16C:$rA, R16C:$rB)),
1614 (EQVr16 R16C:$rA, R16C:$rB)>;
1615
1616// Select bits:
1617def SELBv16i8:
1618 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1619 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1620 [(set (v16i8 VECREG:$rT),
1621 (SPUselb_v16i8 (v16i8 VECREG:$rA), (v16i8 VECREG:$rB),
1622 (v16i8 VECREG:$rC)))]>;
1623
1624def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
1625 (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
1626 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1627
1628def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
1629 (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
1630 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1631
1632def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
1633 (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
1634 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1635
1636def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
1637 (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
1638 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1639
1640def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
1641 (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
1642 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1643
1644def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
1645 (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
1646 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1647
1648def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
1649 (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
1650 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1651
1652def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
1653 (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
1654 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1655
1656def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
1657 (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
1658 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1659
1660def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
1661 (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
1662 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1663
1664def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
1665 (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
1666 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1667
1668def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
1669 (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
1670 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1671
1672def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
1673 (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
1674 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1675
1676def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
1677 (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
1678 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1679
1680def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
1681 (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
1682 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1683
1684def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
1685 (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
1686 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1687
1688def SELBv8i16:
1689 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1690 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1691 [(set (v8i16 VECREG:$rT),
1692 (SPUselb_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB),
1693 (v8i16 VECREG:$rC)))]>;
1694
1695def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
1696 (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
1697 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1698
1699def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
1700 (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
1701 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1702
1703def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
1704 (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
1705 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1706
1707def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
1708 (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
1709 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1710
1711def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
1712 (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
1713 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1714
1715def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
1716 (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
1717 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1718
1719def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
1720 (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
1721 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1722
1723def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
1724 (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
1725 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1726
1727def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
1728 (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
1729 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1730
1731def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
1732 (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
1733 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1734
1735def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
1736 (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
1737 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1738
1739def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
1740 (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
1741 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1742
1743def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
1744 (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
1745 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1746
1747def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
1748 (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
1749 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1750
1751def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
1752 (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
1753 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1754
1755def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
1756 (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
1757 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1758
1759def SELBv4i32:
1760 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1761 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1762 [(set (v4i32 VECREG:$rT),
1763 (SPUselb_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB),
1764 (v4i32 VECREG:$rC)))]>;
1765
1766def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
1767 (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
1768 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1769
1770def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
1771 (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
1772 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1773
1774def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
1775 (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
1776 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1777
1778def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
1779 (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
1780 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1781
1782def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
1783 (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
1784 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1785
1786def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
1787 (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
1788 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1789
1790def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
1791 (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
1792 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1793
1794def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
1795 (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
1796 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1797
1798def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
1799 (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
1800 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1801
1802def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
1803 (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
1804 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1805
1806def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
1807 (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
1808 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1809
1810def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
1811 (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
1812 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1813
1814def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
1815 (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
1816 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1817
1818def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
1819 (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
1820 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1821
1822def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
1823 (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
1824 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1825
1826def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
1827 (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
1828 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1829
1830def SELBr32:
1831 RRRForm<0b1000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
1832 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1833 []>;
1834
1835// And the various patterns that can be matched... (all 8 of them :-)
1836def : Pat<(or (and R32C:$rA, R32C:$rC),
1837 (and R32C:$rB, (not R32C:$rC))),
1838 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1839
1840def : Pat<(or (and R32C:$rC, R32C:$rA),
1841 (and R32C:$rB, (not R32C:$rC))),
1842 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1843
1844def : Pat<(or (and R32C:$rA, R32C:$rC),
1845 (and (not R32C:$rC), R32C:$rB)),
1846 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1847
1848def : Pat<(or (and R32C:$rC, R32C:$rA),
1849 (and (not R32C:$rC), R32C:$rB)),
1850 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1851
1852def : Pat<(or (and R32C:$rA, (not R32C:$rC)),
1853 (and R32C:$rB, R32C:$rC)),
1854 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1855
1856def : Pat<(or (and R32C:$rA, (not R32C:$rC)),
1857 (and R32C:$rC, R32C:$rB)),
1858 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1859
1860def : Pat<(or (and (not R32C:$rC), R32C:$rA),
1861 (and R32C:$rB, R32C:$rC)),
1862 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1863
1864def : Pat<(or (and (not R32C:$rC), R32C:$rA),
1865 (and R32C:$rC, R32C:$rB)),
1866 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1867
1868def SELBr16:
1869 RRRForm<0b1000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB, R16C:$rC),
1870 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1871 []>;
1872
1873def : Pat<(or (and R16C:$rA, R16C:$rC),
1874 (and R16C:$rB, (not R16C:$rC))),
1875 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1876
1877def : Pat<(or (and R16C:$rC, R16C:$rA),
1878 (and R16C:$rB, (not R16C:$rC))),
1879 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1880
1881def : Pat<(or (and R16C:$rA, R16C:$rC),
1882 (and (not R16C:$rC), R16C:$rB)),
1883 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1884
1885def : Pat<(or (and R16C:$rC, R16C:$rA),
1886 (and (not R16C:$rC), R16C:$rB)),
1887 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1888
1889def : Pat<(or (and R16C:$rA, (not R16C:$rC)),
1890 (and R16C:$rB, R16C:$rC)),
1891 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1892
1893def : Pat<(or (and R16C:$rA, (not R16C:$rC)),
1894 (and R16C:$rC, R16C:$rB)),
1895 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1896
1897def : Pat<(or (and (not R16C:$rC), R16C:$rA),
1898 (and R16C:$rB, R16C:$rC)),
1899 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1900
1901def : Pat<(or (and (not R16C:$rC), R16C:$rA),
1902 (and R16C:$rC, R16C:$rB)),
1903 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1904
1905//===----------------------------------------------------------------------===//
1906// Vector shuffle...
1907//===----------------------------------------------------------------------===//
1908
1909def SHUFB:
1910 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1911 "shufb\t$rT, $rA, $rB, $rC", IntegerOp,
1912 [/* insert intrinsic here */]>;
1913
1914// SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB.
1915// See the SPUshuffle SDNode operand above, which sets up the DAG pattern
1916// matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with
1917// the SPUISD::SHUFB opcode.
1918def : Pat<(SPUshuffle (v16i8 VECREG:$rA), (v16i8 VECREG:$rB), VECREG:$rC),
1919 (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1920
1921def : Pat<(SPUshuffle (v8i16 VECREG:$rA), (v8i16 VECREG:$rB), VECREG:$rC),
1922 (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1923
1924def : Pat<(SPUshuffle (v4i32 VECREG:$rA), (v4i32 VECREG:$rB), VECREG:$rC),
1925 (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1926
1927def : Pat<(SPUshuffle (v2i64 VECREG:$rA), (v2i64 VECREG:$rB), VECREG:$rC),
1928 (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1929
1930//===----------------------------------------------------------------------===//
1931// Shift and rotate group:
1932//===----------------------------------------------------------------------===//
1933
1934def SHLHv8i16:
1935 RRForm<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1936 "shlh\t$rT, $rA, $rB", RotateShift,
1937 [(set (v8i16 VECREG:$rT),
1938 (SPUvec_shl_v8i16 (v8i16 VECREG:$rA), R16C:$rB))]>;
1939
1940// $rB gets promoted to 32-bit register type when confronted with
1941// this llvm assembly code:
1942//
1943// define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) {
1944// %A = shl i16 %arg1, %arg2
1945// ret i16 %A
1946// }
1947//
1948// However, we will generate this code when lowering 8-bit shifts and rotates.
1949
1950def SHLHr16:
1951 RRForm<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1952 "shlh\t$rT, $rA, $rB", RotateShift,
1953 [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>;
1954
1955def SHLHr16_r32:
1956 RRForm<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
1957 "shlh\t$rT, $rA, $rB", RotateShift,
1958 [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>;
1959
1960def SHLHIv8i16:
1961 RI7Form<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
1962 "shlhi\t$rT, $rA, $val", RotateShift,
1963 [(set (v8i16 VECREG:$rT),
1964 (SPUvec_shl_v8i16 (v8i16 VECREG:$rA), (i16 uimm7:$val)))]>;
1965
1966def : Pat<(SPUvec_shl_v8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val)),
1967 (SHLHIv8i16 VECREG:$rA, imm:$val)>;
1968
1969def SHLHIr16:
1970 RI7Form<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
1971 "shlhi\t$rT, $rA, $val", RotateShift,
1972 [(set R16C:$rT, (shl R16C:$rA, (i32 uimm7:$val)))]>;
1973
1974def : Pat<(shl R16C:$rA, (i16 uimm7:$val)),
1975 (SHLHIr16 R16C:$rA, uimm7:$val)>;
1976
1977def SHLv4i32:
1978 RRForm<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1979 "shl\t$rT, $rA, $rB", RotateShift,
1980 [(set (v4i32 VECREG:$rT),
1981 (SPUvec_shl_v4i32 (v4i32 VECREG:$rA), R16C:$rB))]>;
1982
1983def SHLr32:
1984 RRForm<0b11111010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1985 "shl\t$rT, $rA, $rB", RotateShift,
1986 [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
1987
1988def SHLIv4i32:
1989 RI7Form<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
1990 "shli\t$rT, $rA, $val", RotateShift,
1991 [(set (v4i32 VECREG:$rT),
1992 (SPUvec_shl_v4i32 (v4i32 VECREG:$rA), (i16 uimm7:$val)))]>;
1993
1994def: Pat<(SPUvec_shl_v4i32 (v4i32 VECREG:$rA), (i32 uimm7:$val)),
1995 (SHLIv4i32 VECREG:$rA, uimm7:$val)>;
1996
1997def SHLIr32:
1998 RI7Form<0b11111010000, (outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
1999 "shli\t$rT, $rA, $val", RotateShift,
2000 [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>;
2001
2002def : Pat<(shl R32C:$rA, (i16 uimm7:$val)),
2003 (SHLIr32 R32C:$rA, uimm7:$val)>;
2004
2005// SHLQBI vec form: Note that this will shift the entire vector (the 128-bit
2006// register) to the left. Vector form is here to ensure type correctness.
2007def SHLQBIvec:
2008 RRForm<0b11011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2009 "shlqbi\t$rT, $rA, $rB", RotateShift,
2010 [/* intrinsic */]>;
2011
2012// See note above on SHLQBI.
2013def SHLQBIIvec:
2014 RI7Form<0b11011111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2015 "shlqbii\t$rT, $rA, $val", RotateShift,
2016 [/* intrinsic */]>;
2017
2018// SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes,
2019// not by bits.
2020def SHLQBYvec:
2021 RI7Form<0b11111011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2022 "shlqbyi\t$rT, $rA, $rB", RotateShift,
2023 [/* intrinsic */]>;
2024
2025def SHLQBYIvec:
2026 RI7Form<0b11111111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2027 "shlqbyi\t$rT, $rA, $val", RotateShift,
2028 [/* intrinsic */]>;
2029
2030// ROTH v8i16 form:
2031def ROTHv8i16:
2032 RRForm<0b00111010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2033 "roth\t$rT, $rA, $rB", RotateShift,
2034 [(set (v8i16 VECREG:$rT),
2035 (SPUvec_rotl_v8i16 VECREG:$rA, VECREG:$rB))]>;
2036
2037def ROTHr16:
2038 RRForm<0b00111010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2039 "roth\t$rT, $rA, $rB", RotateShift,
2040 [(set R16C:$rT, (rotl R16C:$rA, R16C:$rB))]>;
2041
2042def ROTHr16_r32:
2043 RRForm<0b00111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2044 "roth\t$rT, $rA, $rB", RotateShift,
2045 [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>;
2046
2047def ROTHIv8i16:
2048 RI7Form<0b00111110000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2049 "rothi\t$rT, $rA, $val", RotateShift,
2050 [(set (v8i16 VECREG:$rT),
2051 (SPUvec_rotl_v8i16 VECREG:$rA, (i16 uimm7:$val)))]>;
2052
2053def : Pat<(SPUvec_rotl_v8i16 VECREG:$rA, (i16 uimm7:$val)),
2054 (ROTHIv8i16 VECREG:$rA, imm:$val)>;
2055
2056def : Pat<(SPUvec_rotl_v8i16 VECREG:$rA, (i32 uimm7:$val)),
2057 (ROTHIv8i16 VECREG:$rA, imm:$val)>;
2058
2059def ROTHIr16:
2060 RI7Form<0b00111110000, (outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2061 "rothi\t$rT, $rA, $val", RotateShift,
2062 [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>;
2063
2064def ROTHIr16_i32:
2065 RI7Form<0b00111110000, (outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
2066 "rothi\t$rT, $rA, $val", RotateShift,
2067 [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>;
2068
2069def ROTv4i32:
2070 RRForm<0b00011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2071 "rot\t$rT, $rA, $rB", RotateShift,
2072 [(set (v4i32 VECREG:$rT),
2073 (SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), R32C:$rB))]>;
2074
2075def ROTr32:
2076 RRForm<0b00011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2077 "rot\t$rT, $rA, $rB", RotateShift,
2078 [(set R32C:$rT, (rotl R32C:$rA, R32C:$rB))]>;
2079
2080def ROTIv4i32:
2081 RI7Form<0b00011110000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2082 "roti\t$rT, $rA, $val", RotateShift,
2083 [(set (v4i32 VECREG:$rT),
2084 (SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>;
2085
2086def : Pat<(SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), (i16 uimm7:$val)),
2087 (ROTIv4i32 VECREG:$rA, imm:$val)>;
2088
2089def ROTIr32:
2090 RI7Form<0b00011110000, (outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
2091 "roti\t$rT, $rA, $val", RotateShift,
2092 [(set R32C:$rT, (rotl R32C:$rA, (i32 uimm7:$val)))]>;
2093
2094def ROTIr32_i16:
2095 RI7Form<0b00111110000, (outs R32C:$rT), (ins R32C:$rA, u7imm:$val),
2096 "roti\t$rT, $rA, $val", RotateShift,
2097 [(set R32C:$rT, (rotl R32C:$rA, (i16 uimm7:$val)))]>;
2098
2099// ROTQBY* vector forms: This rotates the entire vector, but vector registers
2100// are used here for type checking (instances where ROTQBI is used actually
2101// use vector registers)
2102def ROTQBYvec:
2103 RRForm<0b00111011100, (outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
2104 "rotqby\t$rT, $rA, $rB", RotateShift,
2105 [(set (v16i8 VECREG:$rT), (SPUrotbytes_left (v16i8 VECREG:$rA), R16C:$rB))]>;
2106
2107def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), R16C:$rB),
2108 (ROTQBYvec VECREG:$rA, R16C:$rB)>;
2109
2110// See ROTQBY note above.
2111def ROTQBYIvec:
2112 RI7Form<0b00111111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2113 "rotqbyi\t$rT, $rA, $val", RotateShift,
2114 [(set (v16i8 VECREG:$rT),
2115 (SPUrotbytes_left (v16i8 VECREG:$rA), (i16 uimm7:$val)))]>;
2116
2117def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), (i16 uimm7:$val)),
2118 (ROTQBYIvec VECREG:$rA, uimm7:$val)>;
2119
2120// See ROTQBY note above.
2121def ROTQBYBIvec:
2122 RI7Form<0b00110011100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2123 "rotqbybi\t$rT, $rA, $val", RotateShift,
2124 [/* intrinsic */]>;
2125
2126// See ROTQBY note above.
2127//
2128// Assume that the user of this instruction knows to shift the rotate count
2129// into bit 29
2130def ROTQBIvec:
2131 RRForm<0b00011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2132 "rotqbi\t$rT, $rA, $rB", RotateShift,
2133 [/* insert intrinsic here */]>;
2134
2135// See ROTQBY note above.
2136def ROTQBIIvec:
2137 RI7Form<0b00011111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2138 "rotqbii\t$rT, $rA, $val", RotateShift,
2139 [/* insert intrinsic here */]>;
2140
2141// ROTHM v8i16 form:
2142// NOTE(1): No vector rotate is generated by the C/C++ frontend (today),
2143// so this only matches a synthetically generated/lowered code
2144// fragment.
2145// NOTE(2): $rB must be negated before the right rotate!
2146def ROTHMv8i16:
2147 RRForm<0b10111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2148 "rothm\t$rT, $rA, $rB", RotateShift,
2149 [/* see patterns below - $rB must be negated */]>;
2150
2151def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), R32C:$rB),
2152 (ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2153
2154def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), R16C:$rB),
2155 (ROTHMv8i16 VECREG:$rA,
2156 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2157
2158def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), /* R8C */ R16C:$rB),
2159 (ROTHMv8i16 VECREG:$rA,
2160 (SFIr32 (XSHWr16 /* (XSBHr8 R8C */ R16C:$rB) /*)*/, 0))>;
2161
2162// ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
2163// Note: This instruction doesn't match a pattern because rB must be negated
2164// for the instruction to work. Thus, the pattern below the instruction!
2165def ROTHMr16:
2166 RRForm<0b10111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2167 "rothm\t$rT, $rA, $rB", RotateShift,
2168 [/* see patterns below - $rB must be negated! */]>;
2169
2170def : Pat<(srl R16C:$rA, R32C:$rB),
2171 (ROTHMr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2172
2173def : Pat<(srl R16C:$rA, R16C:$rB),
2174 (ROTHMr16 R16C:$rA,
2175 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2176
2177def : Pat<(srl R16C:$rA, /* R8C */ R16C:$rB),
2178 (ROTHMr16 R16C:$rA,
2179 (SFIr32 (XSHWr16 /* (XSBHr8 R8C */ R16C:$rB) /* ) */, 0))>;
2180
2181// ROTHMI v8i16 form: See the comment for ROTHM v8i16. The difference here is
2182// that the immediate can be complemented, so that the user doesn't have to
2183// worry about it.
2184def ROTHMIv8i16:
2185 RI7Form<0b10111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2186 "rothmi\t$rT, $rA, $val", RotateShift,
2187 [(set (v8i16 VECREG:$rT),
2188 (SPUvec_srl_v8i16 (v8i16 VECREG:$rA), (i32 imm:$val)))]>;
2189
2190def: Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), (i16 imm:$val)),
2191 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2192
2193def ROTHMIr16:
2194 RI7Form<0b10111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
2195 "rothmi\t$rT, $rA, $val", RotateShift,
2196 [(set R16C:$rT, (srl R16C:$rA, (i32 uimm7:$val)))]>;
2197
2198def: Pat<(srl R16C:$rA, (i16 uimm7:$val)),
2199 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2200
2201// ROTM v4i32 form: See the ROTHM v8i16 comments.
2202def ROTMv4i32:
2203 RRForm<0b10011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2204 "rotm\t$rT, $rA, $rB", RotateShift,
2205 [/* see patterns below - $rB must be negated */]>;
2206
2207def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, R32C:$rB),
2208 (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2209
2210def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, R16C:$rB),
2211 (ROTMv4i32 VECREG:$rA,
2212 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2213
2214def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, /* R8C */ R16C:$rB),
2215 (ROTMv4i32 VECREG:$rA,
2216 (SFIr32 (XSHWr16 /* (XSBHr8 R8C */ R16C:$rB) /*)*/, 0))>;
2217
2218def ROTMr32:
2219 RRForm<0b10011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2220 "rotm\t$rT, $rA, $rB", RotateShift,
2221 [/* see patterns below - $rB must be negated */]>;
2222
2223def : Pat<(srl R32C:$rA, R32C:$rB),
2224 (ROTMr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2225
2226def : Pat<(srl R32C:$rA, R16C:$rB),
2227 (ROTMr32 R32C:$rA,
2228 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2229
2230// ROTMI v4i32 form: See the comment for ROTHM v8i16.
2231def ROTMIv4i32:
2232 RI7Form<0b10011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2233 "rotmi\t$rT, $rA, $val", RotateShift,
2234 [(set (v4i32 VECREG:$rT),
2235 (SPUvec_srl_v4i32 VECREG:$rA, (i32 uimm7:$val)))]>;
2236
2237def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, (i16 uimm7:$val)),
2238 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2239
2240// ROTMI r32 form: know how to complement the immediate value.
2241def ROTMIr32:
2242 RI7Form<0b10011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2243 "rotmi\t$rT, $rA, $val", RotateShift,
2244 [(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>;
2245
2246def : Pat<(srl R32C:$rA, (i16 imm:$val)),
2247 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2248
2249// ROTQMBYvec: This is a vector form merely so that when used in an
2250// instruction pattern, type checking will succeed. This instruction assumes
2251// that the user knew to complement $rB.
2252def ROTQMBYvec:
2253 RRForm<0b10111011100, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2254 "rotqmby\t$rT, $rA, $rB", RotateShift,
2255 [(set (v16i8 VECREG:$rT),
2256 (SPUrotbytes_right_zfill (v16i8 VECREG:$rA), R32C:$rB))]>;
2257
2258def ROTQMBYIvec:
2259 RI7Form<0b10111111100, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2260 "rotqmbyi\t$rT, $rA, $val", RotateShift,
2261 [(set (v16i8 VECREG:$rT),
2262 (SPUrotbytes_right_zfill (v16i8 VECREG:$rA), (i32 uimm7:$val)))]>;
2263
2264def : Pat<(SPUrotbytes_right_zfill VECREG:$rA, (i16 uimm7:$val)),
2265 (ROTQMBYIvec VECREG:$rA, uimm7:$val)>;
2266
2267def ROTQMBYBIvec:
2268 RRForm<0b10110011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2269 "rotqmbybi\t$rT, $rA, $rB", RotateShift,
2270 [/* intrinsic */]>;
2271
2272def ROTQMBIvec:
2273 RRForm<0b10011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2274 "rotqmbi\t$rT, $rA, $rB", RotateShift,
2275 [/* intrinsic */]>;
2276
2277def ROTQMBIIvec:
2278 RI7Form<0b10011111100, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2279 "rotqmbii\t$rT, $rA, $val", RotateShift,
2280 [/* intrinsic */]>;
2281
2282def ROTMAHv8i16:
2283 RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2284 "rotmah\t$rT, $rA, $rB", RotateShift,
2285 [/* see patterns below - $rB must be negated */]>;
2286
2287def : Pat<(SPUvec_sra_v8i16 VECREG:$rA, R32C:$rB),
2288 (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2289
2290def : Pat<(SPUvec_sra_v8i16 VECREG:$rA, R16C:$rB),
2291 (ROTMAHv8i16 VECREG:$rA,
2292 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2293
2294def ROTMAHr16:
2295 RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2296 "rotmah\t$rT, $rA, $rB", RotateShift,
2297 [/* see patterns below - $rB must be negated */]>;
2298
2299def : Pat<(sra R16C:$rA, R32C:$rB),
2300 (ROTMAHr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2301
2302def : Pat<(sra R16C:$rA, R16C:$rB),
2303 (ROTMAHr16 R16C:$rA,
2304 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2305
2306def ROTMAHIv8i16:
2307 RRForm<0b01111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2308 "rotmahi\t$rT, $rA, $val", RotateShift,
2309 [(set (v8i16 VECREG:$rT),
2310 (SPUvec_sra_v8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
2311
2312def : Pat<(SPUvec_sra_v8i16 (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2313 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2314
2315def ROTMAHIr16:
2316 RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val),
2317 "rotmahi\t$rT, $rA, $val", RotateShift,
2318 [(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>;
2319
2320def : Pat<(sra R16C:$rA, (i32 imm:$val)),
2321 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2322
2323def ROTMAv4i32:
2324 RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2325 "rotma\t$rT, $rA, $rB", RotateShift,
2326 [/* see patterns below - $rB must be negated */]>;
2327
2328def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, R32C:$rB),
2329 (ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>;
2330
2331def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, R16C:$rB),
2332 (ROTMAv4i32 (v4i32 VECREG:$rA),
2333 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2334
2335def ROTMAr32:
2336 RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2337 "rotma\t$rT, $rA, $rB", RotateShift,
2338 [/* see patterns below - $rB must be negated */]>;
2339
2340def : Pat<(sra R32C:$rA, R32C:$rB),
2341 (ROTMAr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2342
2343def : Pat<(sra R32C:$rA, R16C:$rB),
2344 (ROTMAr32 R32C:$rA,
2345 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2346
2347def ROTMAIv4i32:
2348 RRForm<0b01011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2349 "rotmai\t$rT, $rA, $val", RotateShift,
2350 [(set (v4i32 VECREG:$rT),
2351 (SPUvec_sra_v4i32 VECREG:$rA, (i32 uimm7:$val)))]>;
2352
2353def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, (i16 uimm7:$val)),
2354 (ROTMAIv4i32 VECREG:$rA, uimm7:$val)>;
2355
2356def ROTMAIr32:
2357 RRForm<0b01011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2358 "rotmai\t$rT, $rA, $val", RotateShift,
2359 [(set R32C:$rT, (sra R32C:$rA, (i32 uimm7:$val)))]>;
2360
2361def : Pat<(sra R32C:$rA, (i16 uimm7:$val)),
2362 (ROTMAIr32 R32C:$rA, uimm7:$val)>;
2363
2364//===----------------------------------------------------------------------===//
2365// Branch and conditionals:
2366//===----------------------------------------------------------------------===//
2367
2368let isTerminator = 1, isBarrier = 1 in {
2369 // Halt If Equal (r32 preferred slot only, no vector form)
2370 def HEQr32:
2371 RRForm_3<0b00011011110, (outs), (ins R32C:$rA, R32C:$rB),
2372 "heq\t$rA, $rB", BranchResolv,
2373 [/* no pattern to match */]>;
2374
2375 def HEQIr32 :
2376 RI10Form_2<0b11111110, (outs), (ins R32C:$rA, s10imm:$val),
2377 "heqi\t$rA, $val", BranchResolv,
2378 [/* no pattern to match */]>;
2379
2380 // HGT/HGTI: These instructions use signed arithmetic for the comparison,
2381 // contrasting with HLGT/HLGTI, which use unsigned comparison:
2382 def HGTr32:
2383 RRForm_3<0b00011010010, (outs), (ins R32C:$rA, R32C:$rB),
2384 "hgt\t$rA, $rB", BranchResolv,
2385 [/* no pattern to match */]>;
2386
2387 def HGTIr32:
2388 RI10Form_2<0b11110010, (outs), (ins R32C:$rA, s10imm:$val),
2389 "hgti\t$rA, $val", BranchResolv,
2390 [/* no pattern to match */]>;
2391
2392 def HLGTr32:
2393 RRForm_3<0b00011011010, (outs), (ins R32C:$rA, R32C:$rB),
2394 "hlgt\t$rA, $rB", BranchResolv,
2395 [/* no pattern to match */]>;
2396
2397 def HLGTIr32:
2398 RI10Form_2<0b11111010, (outs), (ins R32C:$rA, s10imm:$val),
2399 "hlgti\t$rA, $val", BranchResolv,
2400 [/* no pattern to match */]>;
2401}
2402
2403// Comparison operators:
2404
2405def CEQBv16i8:
2406 RRForm<0b00001011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2407 "ceqb\t$rT, $rA, $rB", ByteOp,
2408 [/* no pattern to match: intrinsic */]>;
2409
2410def CEQBIv16i8:
2411 RI10Form<0b01111110, (outs VECREG:$rT), (ins VECREG:$rA, s7imm:$val),
2412 "ceqbi\t$rT, $rA, $val", ByteOp,
2413 [/* no pattern to match: intrinsic */]>;
2414
2415def CEQHr16:
2416 RRForm<0b00010011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2417 "ceqh\t$rT, $rA, $rB", ByteOp,
2418 [/* no pattern to match */]>;
2419
2420def CEQHv8i16:
2421 RRForm<0b00010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2422 "ceqh\t$rT, $rA, $rB", ByteOp,
2423 [/* no pattern to match: intrinsic */]>;
2424
2425def CEQHIr16:
2426 RI10Form<0b10111110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2427 "ceqhi\t$rT, $rA, $val", ByteOp,
2428 [/* no pattern to match: intrinsic */]>;
2429
2430def CEQHIv8i16:
2431 RI10Form<0b10111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2432 "ceqhi\t$rT, $rA, $val", ByteOp,
2433 [/* no pattern to match: intrinsic */]>;
2434
2435def CEQr32:
2436 RRForm<0b00000011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2437 "ceq\t$rT, $rA, $rB", ByteOp,
2438 [/* no pattern to match: intrinsic */]>;
2439
2440def CEQv4i32:
2441 RRForm<0b00000011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2442 "ceq\t$rT, $rA, $rB", ByteOp,
2443 [/* no pattern to match: intrinsic */]>;
2444
2445def CEQIr32:
2446 RI10Form<0b00111110, (outs R32C:$rT), (ins R32C:$rA, s10imm:$val),
2447 "ceqi\t$rT, $rA, $val", ByteOp,
2448 [/* no pattern to match: intrinsic */]>;
2449
2450def CEQIv4i32:
2451 RI10Form<0b00111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2452 "ceqi\t$rT, $rA, $val", ByteOp,
2453 [/* no pattern to match: intrinsic */]>;
2454
2455let isCall = 1,
2456 // All calls clobber the non-callee-saved registers:
2457 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,
2458 R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,
2459 R20,R21,R22,R23,R24,R25,R26,R27,R28,R29,
2460 R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,
2461 R40,R41,R42,R43,R44,R45,R46,R47,R48,R49,
2462 R50,R51,R52,R53,R54,R55,R56,R57,R58,R59,
2463 R60,R61,R62,R63,R64,R65,R66,R67,R68,R69,
2464 R70,R71,R72,R73,R74,R75,R76,R77,R78,R79],
2465 // All of these instructions use $lr (aka $0)
2466 Uses = [R0] in {
2467 // Branch relative and set link: Used if we actually know that the target
2468 // is within [-32768, 32767] bytes of the target
2469 def BRSL:
2470 BranchSetLink<0b011001100, (outs), (ins relcalltarget:$func, variable_ops),
2471 "brsl\t$$lr, $func",
2472 [(SPUcall (SPUpcrel tglobaladdr:$func, 0))]>;
2473
2474 // Branch absolute and set link: Used if we actually know that the target
2475 // is an absolute address
2476 def BRASL:
2477 BranchSetLink<0b011001100, (outs), (ins calltarget:$func, variable_ops),
2478 "brasl\t$$lr, $func",
2479 [(SPUcall tglobaladdr:$func)]>;
2480
2481 // Branch indirect and set link if external data. These instructions are not
2482 // actually generated, matched by an intrinsic:
2483 def BISLED_00: BISLEDForm<0b11, "bisled\t$$lr, $func", [/* empty pattern */]>;
2484 def BISLED_E0: BISLEDForm<0b10, "bisled\t$$lr, $func", [/* empty pattern */]>;
2485 def BISLED_0D: BISLEDForm<0b01, "bisled\t$$lr, $func", [/* empty pattern */]>;
2486 def BISLED_ED: BISLEDForm<0b00, "bisled\t$$lr, $func", [/* empty pattern */]>;
2487
2488 // Branch indirect and set link. This is the "X-form" address version of a
2489 // function call
2490 def BISL:
2491 BIForm<0b10010101100, "bisl\t$$lr, $func", [(SPUcall R32C:$func)]>;
2492}
2493
2494// Unconditional branches:
2495let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
2496 def BR :
2497 UncondBranch<0b001001100, (outs), (ins brtarget:$dest),
2498 "br\t$dest",
2499 [(br bb:$dest)]>;
2500
2501 // Unconditional, absolute address branch
2502 def BRA:
2503 UncondBranch<0b001100000, (outs), (ins brtarget:$dest),
2504 "bra\t$dest",
2505 [/* no pattern */]>;
2506
2507 // Indirect branch
2508 def BI:
2509 BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>;
2510
2511 // Various branches:
2512 def BRNZ:
2513 RI16Form<0b010000100, (outs), (ins R32C:$rCond, brtarget:$dest),
2514 "brnz\t$rCond,$dest",
2515 BranchResolv,
2516 [(brcond R32C:$rCond, bb:$dest)]>;
2517
2518 def BRZ:
2519 RI16Form<0b000000100, (outs), (ins R32C:$rT, brtarget:$dest),
2520 "brz\t$rT,$dest",
2521 BranchResolv,
2522 [/* no pattern */]>;
2523
2524 def BRHNZ:
2525 RI16Form<0b011000100, (outs), (ins R16C:$rCond, brtarget:$dest),
2526 "brhnz\t$rCond,$dest",
2527 BranchResolv,
2528 [(brcond R16C:$rCond, bb:$dest)]>;
2529
2530 def BRHZ:
2531 RI16Form<0b001000100, (outs), (ins R16C:$rT, brtarget:$dest),
2532 "brhz\t$rT,$dest",
2533 BranchResolv,
2534 [/* no pattern */]>;
2535
2536/*
2537 def BINZ:
2538 BICondForm<0b10010100100, "binz\t$rA, $func",
2539 [(SPUbinz R32C:$rA, R32C:$func)]>;
2540
2541 def BIZ:
2542 BICondForm<0b00010100100, "biz\t$rA, $func",
2543 [(SPUbiz R32C:$rA, R32C:$func)]>;
2544*/
2545}
2546
2547def : Pat<(brcond (i16 (seteq R16C:$rA, 0)), bb:$dest),
2548 (BRHZ R16C:$rA, bb:$dest)>;
2549def : Pat<(brcond (i16 (setne R16C:$rA, 0)), bb:$dest),
2550 (BRHNZ R16C:$rA, bb:$dest)>;
2551
2552def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
2553 (BRZ R32C:$rA, bb:$dest)>;
2554def : Pat<(brcond (i32 (setne R32C:$rA, 0)), bb:$dest),
2555 (BRZ R32C:$rA, bb:$dest)>;
2556
2557let isTerminator = 1, isBarrier = 1 in {
2558 let isReturn = 1 in {
2559 def RET:
2560 RETForm<"bi\t$$lr", [(retflag)]>;
2561 }
2562}
2563
2564//===----------------------------------------------------------------------===//
2565// Various brcond predicates:
2566//===----------------------------------------------------------------------===//
2567/*
2568def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
2569 (BRZ R32C:$rA, bb:$dest)>;
2570
2571def : Pat<(brcond (i32 (seteq R32C:$rA, R32C:$rB)), bb:$dest),
2572 (BRNZ (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>;
2573
2574def : Pat<(brcond (i16 (seteq R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
2575 (BRHNZ (CEQHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
2576
2577def : Pat<(brcond (i16 (seteq R16C:$rA, R16C:$rB)), bb:$dest),
2578 (BRHNZ (CEQHr16 R16C:$rA, R16C:$rB), bb:$dest)>;
2579*/
2580
2581//===----------------------------------------------------------------------===//
2582// Single precision floating point instructions
2583//===----------------------------------------------------------------------===//
2584
2585def FAv4f32:
2586 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2587 "fa\t$rT, $rA, $rB", SPrecFP,
2588 [(set (v4f32 VECREG:$rT), (fadd (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
2589
2590def FAf32 :
2591 RRForm<0b00100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
2592 "fa\t$rT, $rA, $rB", SPrecFP,
2593 [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>;
2594
2595def FSv4f32:
2596 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2597 "fs\t$rT, $rA, $rB", SPrecFP,
2598 [(set (v4f32 VECREG:$rT), (fsub (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
2599
2600def FSf32 :
2601 RRForm<0b10100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
2602 "fs\t$rT, $rA, $rB", SPrecFP,
2603 [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>;
2604
2605// Floating point reciprocal estimate
2606def FREv4f32 :
2607 RRForm_1<0b00011101100, (outs VECREG:$rT), (ins VECREG:$rA),
2608 "frest\t$rT, $rA", SPrecFP,
2609 [(set (v4f32 VECREG:$rT), (SPUreciprocalEst (v4f32 VECREG:$rA)))]>;
2610
2611def FREf32 :
2612 RRForm_1<0b00011101100, (outs R32FP:$rT), (ins R32FP:$rA),
2613 "frest\t$rT, $rA", SPrecFP,
2614 [(set R32FP:$rT, (SPUreciprocalEst R32FP:$rA))]>;
2615
2616// Floating point interpolate (used in conjunction with reciprocal estimate)
2617def FIv4f32 :
2618 RRForm<0b00101011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2619 "fi\t$rT, $rA, $rB", SPrecFP,
2620 [(set (v4f32 VECREG:$rT), (SPUinterpolate (v4f32 VECREG:$rA),
2621 (v4f32 VECREG:$rB)))]>;
2622
2623def FIf32 :
2624 RRForm<0b00101011110, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
2625 "fi\t$rT, $rA, $rB", SPrecFP,
2626 [(set R32FP:$rT, (SPUinterpolate R32FP:$rA, R32FP:$rB))]>;
2627
2628// Floating Compare Equal
2629def FCEQf32 :
2630 RRForm<0b01000011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
2631 "fceq\t$rT, $rA, $rB", SPrecFP,
2632 [(set R32C:$rT, (setoeq R32FP:$rA, R32FP:$rB))]>;
2633
2634def FCMEQf32 :
2635 RRForm<0b01010011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
2636 "fcmeq\t$rT, $rA, $rB", SPrecFP,
2637 [(set R32C:$rT, (setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
2638
2639def FCGTf32 :
2640 RRForm<0b01000011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
2641 "fcgt\t$rT, $rA, $rB", SPrecFP,
2642 [(set R32C:$rT, (setogt R32FP:$rA, R32FP:$rB))]>;
2643
2644def FCMGTf32 :
2645 RRForm<0b01010011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
2646 "fcmgt\t$rT, $rA, $rB", SPrecFP,
2647 [(set R32C:$rT, (setogt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
2648
2649// FP Status and Control Register Write
2650// Why isn't rT a don't care in the ISA?
2651// Should we create a special RRForm_3 for this guy and zero out the rT?
2652def FSCRWf32 :
2653 RRForm_1<0b01011101110, (outs R32FP:$rT), (ins R32FP:$rA),
2654 "fscrwr\t$rA", SPrecFP,
2655 [/* This instruction requires an intrinsic. Note: rT is unused. */]>;
2656
2657// FP Status and Control Register Read
2658def FSCRRf32 :
2659 RRForm_2<0b01011101110, (outs R32FP:$rT), (ins),
2660 "fscrrd\t$rT", SPrecFP,
2661 [/* This instruction requires an intrinsic */]>;
2662
2663// llvm instruction space
2664// How do these map onto cell instructions?
2665// fdiv rA rB
2666// frest rC rB # c = 1/b (both lines)
2667// fi rC rB rC
2668// fm rD rA rC # d = a * 1/b
2669// fnms rB rD rB rA # b = - (d * b - a) --should == 0 in a perfect world
2670// fma rB rB rC rD # b = b * c + d
2671// = -(d *b -a) * c + d
2672// = a * c - c ( a *b *c - a)
2673
2674// fcopysign (???)
2675
2676// Library calls:
2677// These llvm instructions will actually map to library calls.
2678// All that's needed, then, is to check that the appropriate library is
2679// imported and do a brsl to the proper function name.
2680// frem # fmod(x, y): x - (x/y) * y
2681// (Note: fmod(double, double), fmodf(float,float)
2682// fsqrt?
2683// fsin?
2684// fcos?
2685// Unimplemented SPU instruction space
2686// floating reciprocal absolute square root estimate (frsqest)
2687
2688// The following are probably just intrinsics
2689// status and control register write
2690// status and control register read
2691
2692//--------------------------------------
2693// Floating point multiply instructions
2694//--------------------------------------
2695
2696def FMv4f32:
2697 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2698 "fm\t$rT, $rA, $rB", SPrecFP,
2699 [(set (v4f32 VECREG:$rT), (fmul (v4f32 VECREG:$rA),
2700 (v4f32 VECREG:$rB)))]>;
2701
2702def FMf32 :
2703 RRForm<0b01100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
2704 "fm\t$rT, $rA, $rB", SPrecFP,
2705 [(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>;
2706
2707// Floating point multiply and add
2708// e.g. d = c + (a * b)
2709def FMAv4f32:
2710 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
2711 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
2712 [(set (v4f32 VECREG:$rT),
2713 (fadd (v4f32 VECREG:$rC),
2714 (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>;
2715
2716def FMAf32:
2717 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
2718 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
2719 [(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
2720
2721// FP multiply and subtract
2722// Subtracts value in rC from product
2723// res = a * b - c
2724def FMSv4f32 :
2725 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
2726 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
2727 [(set (v4f32 VECREG:$rT),
2728 (fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
2729 (v4f32 VECREG:$rC)))]>;
2730
2731def FMSf32 :
2732 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
2733 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
2734 [(set R32FP:$rT,
2735 (fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>;
2736
2737// Floating Negative Mulitply and Subtract
2738// Subtracts product from value in rC
2739// res = fneg(fms a b c)
2740// = - (a * b - c)
2741// = c - a * b
2742// NOTE: subtraction order
2743// fsub a b = a - b
2744// fs a b = b - a?
2745def FNMSf32 :
2746 RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
2747 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
2748 [(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
2749
2750def FNMSv4f32 :
2751 RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
2752 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
2753 [(set (v4f32 VECREG:$rT),
2754 (fsub (v4f32 VECREG:$rC),
2755 (fmul (v4f32 VECREG:$rA),
2756 (v4f32 VECREG:$rB))))]>;
2757
2758//--------------------------------------
2759// Floating Point Conversions
2760// Signed conversions:
2761def CSiFv4f32:
2762 CVTIntFPForm<0b0101101110, (outs VECREG:$rT), (ins VECREG:$rA),
2763 "csflt\t$rT, $rA, 0", SPrecFP,
2764 [(set (v4f32 VECREG:$rT), (sint_to_fp (v4i32 VECREG:$rA)))]>;
2765
2766// Convert signed integer to floating point
2767def CSiFf32 :
2768 CVTIntFPForm<0b0101101110, (outs R32FP:$rT), (ins R32C:$rA),
2769 "csflt\t$rT, $rA, 0", SPrecFP,
2770 [(set R32FP:$rT, (sint_to_fp R32C:$rA))]>;
2771
2772// Convert unsigned into to float
2773def CUiFv4f32 :
2774 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
2775 "cuflt\t$rT, $rA, 0", SPrecFP,
2776 [(set (v4f32 VECREG:$rT), (uint_to_fp (v4i32 VECREG:$rA)))]>;
2777
2778def CUiFf32 :
2779 CVTIntFPForm<0b1101101110, (outs R32FP:$rT), (ins R32C:$rA),
2780 "cuflt\t$rT, $rA, 0", SPrecFP,
2781 [(set R32FP:$rT, (uint_to_fp R32C:$rA))]>;
2782
2783// Convert float to unsigned int
2784// Assume that scale = 0
2785
2786def CFUiv4f32 :
2787 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
2788 "cfltu\t$rT, $rA, 0", SPrecFP,
2789 [(set (v4i32 VECREG:$rT), (fp_to_uint (v4f32 VECREG:$rA)))]>;
2790
2791def CFUif32 :
2792 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
2793 "cfltu\t$rT, $rA, 0", SPrecFP,
2794 [(set R32C:$rT, (fp_to_uint R32FP:$rA))]>;
2795
2796// Convert float to signed int
2797// Assume that scale = 0
2798
2799def CFSiv4f32 :
2800 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
2801 "cflts\t$rT, $rA, 0", SPrecFP,
2802 [(set (v4i32 VECREG:$rT), (fp_to_sint (v4f32 VECREG:$rA)))]>;
2803
2804def CFSif32 :
2805 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
2806 "cflts\t$rT, $rA, 0", SPrecFP,
2807 [(set R32C:$rT, (fp_to_sint R32FP:$rA))]>;
2808
2809//===----------------------------------------------------------------------==//
2810// Single<->Double precision conversions
2811//===----------------------------------------------------------------------==//
2812
2813// NOTE: We use "vec" name suffix here to avoid confusion (e.g. input is a
2814// v4f32, output is v2f64--which goes in the name?)
2815
2816// Floating point extend single to double
2817// NOTE: Not sure if passing in v4f32 to FESDvec is correct since it
2818// operates on two double-word slots (i.e. 1st and 3rd fp numbers
2819// are ignored).
2820def FESDvec :
2821 RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA),
2822 "fesd\t$rT, $rA", SPrecFP,
2823 [(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))]>;
2824
2825def FESDf32 :
2826 RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA),
2827 "fesd\t$rT, $rA", SPrecFP,
2828 [(set R64FP:$rT, (fextend R32FP:$rA))]>;
2829
2830// Floating point round double to single
2831//def FRDSvec :
2832// RRForm_1<0b10011101110, (outs VECREG:$rT), (ins VECREG:$rA),
2833// "frds\t$rT, $rA,", SPrecFP,
2834// [(set (v4f32 R32FP:$rT), (fround (v2f64 R64FP:$rA)))]>;
2835
2836def FRDSf64 :
2837 RRForm_1<0b10011101110, (outs R32FP:$rT), (ins R64FP:$rA),
2838 "frds\t$rT, $rA", SPrecFP,
2839 [(set R32FP:$rT, (fround R64FP:$rA))]>;
2840
2841//ToDo include anyextend?
2842
2843//===----------------------------------------------------------------------==//
2844// Double precision floating point instructions
2845//===----------------------------------------------------------------------==//
2846def FAf64 :
2847 RRForm<0b00110011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
2848 "dfa\t$rT, $rA, $rB", DPrecFP,
2849 [(set R64FP:$rT, (fadd R64FP:$rA, R64FP:$rB))]>;
2850
2851def FAv2f64 :
2852 RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2853 "dfa\t$rT, $rA, $rB", DPrecFP,
2854 [(set (v2f64 VECREG:$rT), (fadd (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
2855
2856def FSf64 :
2857 RRForm<0b10100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
2858 "dfs\t$rT, $rA, $rB", DPrecFP,
2859 [(set R64FP:$rT, (fsub R64FP:$rA, R64FP:$rB))]>;
2860
2861def FSv2f64 :
2862 RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2863 "dfs\t$rT, $rA, $rB", DPrecFP,
2864 [(set (v2f64 VECREG:$rT),
2865 (fsub (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
2866
2867def FMf64 :
2868 RRForm<0b01100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
2869 "dfm\t$rT, $rA, $rB", DPrecFP,
2870 [(set R64FP:$rT, (fmul R64FP:$rA, R64FP:$rB))]>;
2871
2872def FMv2f64:
2873 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2874 "dfm\t$rT, $rA, $rB", DPrecFP,
2875 [(set (v2f64 VECREG:$rT),
2876 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
2877
2878def FMAf64:
2879 RRForm<0b00111010110, (outs R64FP:$rT),
2880 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
2881 "dfma\t$rT, $rA, $rB", DPrecFP,
2882 [(set R64FP:$rT, (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
2883 RegConstraint<"$rC = $rT">,
2884 NoEncode<"$rC">;
2885
2886def FMAv2f64:
2887 RRForm<0b00111010110, (outs VECREG:$rT),
2888 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
2889 "dfma\t$rT, $rA, $rB", DPrecFP,
2890 [(set (v2f64 VECREG:$rT),
2891 (fadd (v2f64 VECREG:$rC),
2892 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB))))]>,
2893 RegConstraint<"$rC = $rT">,
2894 NoEncode<"$rC">;
2895
2896def FMSf64 :
2897 RRForm<0b10111010110, (outs R64FP:$rT),
2898 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
2899 "dfms\t$rT, $rA, $rB", DPrecFP,
2900 [(set R64FP:$rT, (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))]>,
2901 RegConstraint<"$rC = $rT">,
2902 NoEncode<"$rC">;
2903
2904def FMSv2f64 :
2905 RRForm<0b10111010110, (outs VECREG:$rT),
2906 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
2907 "dfms\t$rT, $rA, $rB", DPrecFP,
2908 [(set (v2f64 VECREG:$rT),
2909 (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
2910 (v2f64 VECREG:$rC)))]>;
2911
2912// FNMS: - (a * b - c)
2913// - (a * b) + c => c - (a * b)
2914def FNMSf64 :
2915 RRForm<0b01111010110, (outs R64FP:$rT),
2916 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
2917 "dfnms\t$rT, $rA, $rB", DPrecFP,
2918 [(set R64FP:$rT, (fsub R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
2919 RegConstraint<"$rC = $rT">,
2920 NoEncode<"$rC">;
2921
2922def : Pat<(fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC)),
2923 (FNMSf64 R64FP:$rA, R64FP:$rB, R64FP:$rC)>;
2924
2925def FNMSv2f64 :
2926 RRForm<0b01111010110, (outs VECREG:$rT),
2927 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
2928 "dfnms\t$rT, $rA, $rB", DPrecFP,
2929 [(set (v2f64 VECREG:$rT),
2930 (fsub (v2f64 VECREG:$rC),
2931 (fmul (v2f64 VECREG:$rA),
2932 (v2f64 VECREG:$rB))))]>,
2933 RegConstraint<"$rC = $rT">,
2934 NoEncode<"$rC">;
2935
2936def : Pat<(fneg (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
2937 (v2f64 VECREG:$rC))),
2938 (FNMSv2f64 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
2939
2940// - (a * b + c)
2941// - (a * b) - c
2942def FNMAf64 :
2943 RRForm<0b11111010110, (outs R64FP:$rT),
2944 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
2945 "dfnma\t$rT, $rA, $rB", DPrecFP,
2946 [(set R64FP:$rT, (fneg (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB))))]>,
2947 RegConstraint<"$rC = $rT">,
2948 NoEncode<"$rC">;
2949
2950def FNMAv2f64 :
2951 RRForm<0b11111010110, (outs VECREG:$rT),
2952 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
2953 "dfnma\t$rT, $rA, $rB", DPrecFP,
2954 [(set (v2f64 VECREG:$rT),
2955 (fneg (fadd (v2f64 VECREG:$rC),
2956 (fmul (v2f64 VECREG:$rA),
2957 (v2f64 VECREG:$rB)))))]>,
2958 RegConstraint<"$rC = $rT">,
2959 NoEncode<"$rC">;
2960
2961//===----------------------------------------------------------------------==//
2962// Floating point negation and absolute value
2963//===----------------------------------------------------------------------==//
2964
2965def : Pat<(fneg (v4f32 VECREG:$rA)),
2966 (XORfnegvec (v4f32 VECREG:$rA),
2967 (v4f32 (ILHUv4i32 0x8000)))>;
2968
2969def : Pat<(fneg R32FP:$rA),
2970 (XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>;
2971
2972def : Pat<(fneg (v2f64 VECREG:$rA)),
2973 (XORfnegvec (v2f64 VECREG:$rA),
2974 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80)))>;
2975
2976def : Pat<(fneg R64FP:$rA),
2977 (XORfneg64 R64FP:$rA,
2978 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80))>;
2979
2980// Floating point absolute value
2981
2982def : Pat<(fabs R32FP:$rA),
2983 (ANDfabs32 R32FP:$rA, (IOHLr32 (ILHUr32 0x7fff), 0xffff))>;
2984
2985def : Pat<(fabs (v4f32 VECREG:$rA)),
2986 (ANDfabsvec (v4f32 VECREG:$rA),
2987 (v4f32 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
2988
2989def : Pat<(fabs R64FP:$rA),
2990 (ANDfabs64 R64FP:$rA, (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f))>;
2991
2992def : Pat<(fabs (v2f64 VECREG:$rA)),
2993 (ANDfabsvec (v2f64 VECREG:$rA),
2994 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
2995
2996//===----------------------------------------------------------------------===//
2997// Execution, Load NOP (execute NOPs belong in even pipeline, load NOPs belong
2998// in the odd pipeline)
2999//===----------------------------------------------------------------------===//
3000
3001def ENOP : I<(outs), (ins), "enop", ExecNOP> {
3002 let Pattern = [];
3003
3004 let Inst{0-10} = 0b10000000010;
3005 let Inst{11-17} = 0;
3006 let Inst{18-24} = 0;
3007 let Inst{25-31} = 0;
3008}
3009
3010def LNOP : I<(outs), (ins), "lnop", LoadNOP> {
3011 let Pattern = [];
3012
3013 let Inst{0-10} = 0b10000000000;
3014 let Inst{11-17} = 0;
3015 let Inst{18-24} = 0;
3016 let Inst{25-31} = 0;
3017}
3018
3019//===----------------------------------------------------------------------===//
3020// Bit conversions (type conversions between vector/packed types)
3021// NOTE: Promotions are handled using the XS* instructions. Truncation
3022// is not handled.
3023//===----------------------------------------------------------------------===//
3024def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>;
3025def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>;
3026def : Pat<(v16i8 (bitconvert (v2i64 VECREG:$src))), (v16i8 VECREG:$src)>;
3027def : Pat<(v16i8 (bitconvert (v4f32 VECREG:$src))), (v16i8 VECREG:$src)>;
3028def : Pat<(v16i8 (bitconvert (v2f64 VECREG:$src))), (v16i8 VECREG:$src)>;
3029
3030def : Pat<(v8i16 (bitconvert (v16i8 VECREG:$src))), (v8i16 VECREG:$src)>;
3031def : Pat<(v8i16 (bitconvert (v4i32 VECREG:$src))), (v8i16 VECREG:$src)>;
3032def : Pat<(v8i16 (bitconvert (v2i64 VECREG:$src))), (v8i16 VECREG:$src)>;
3033def : Pat<(v8i16 (bitconvert (v4f32 VECREG:$src))), (v8i16 VECREG:$src)>;
3034def : Pat<(v8i16 (bitconvert (v2f64 VECREG:$src))), (v8i16 VECREG:$src)>;
3035
3036def : Pat<(v4i32 (bitconvert (v16i8 VECREG:$src))), (v4i32 VECREG:$src)>;
3037def : Pat<(v4i32 (bitconvert (v8i16 VECREG:$src))), (v4i32 VECREG:$src)>;
3038def : Pat<(v4i32 (bitconvert (v2i64 VECREG:$src))), (v4i32 VECREG:$src)>;
3039def : Pat<(v4i32 (bitconvert (v4f32 VECREG:$src))), (v4i32 VECREG:$src)>;
3040def : Pat<(v4i32 (bitconvert (v2f64 VECREG:$src))), (v4i32 VECREG:$src)>;
3041
3042def : Pat<(v2i64 (bitconvert (v16i8 VECREG:$src))), (v2i64 VECREG:$src)>;
3043def : Pat<(v2i64 (bitconvert (v8i16 VECREG:$src))), (v2i64 VECREG:$src)>;
3044def : Pat<(v2i64 (bitconvert (v4i32 VECREG:$src))), (v2i64 VECREG:$src)>;
3045def : Pat<(v2i64 (bitconvert (v4f32 VECREG:$src))), (v2i64 VECREG:$src)>;
3046def : Pat<(v2i64 (bitconvert (v2f64 VECREG:$src))), (v2i64 VECREG:$src)>;
3047
3048def : Pat<(v4f32 (bitconvert (v16i8 VECREG:$src))), (v4f32 VECREG:$src)>;
3049def : Pat<(v4f32 (bitconvert (v8i16 VECREG:$src))), (v4f32 VECREG:$src)>;
3050def : Pat<(v4f32 (bitconvert (v2i64 VECREG:$src))), (v4f32 VECREG:$src)>;
3051def : Pat<(v4f32 (bitconvert (v4i32 VECREG:$src))), (v4f32 VECREG:$src)>;
3052def : Pat<(v4f32 (bitconvert (v2f64 VECREG:$src))), (v4f32 VECREG:$src)>;
3053
3054def : Pat<(v2f64 (bitconvert (v16i8 VECREG:$src))), (v2f64 VECREG:$src)>;
3055def : Pat<(v2f64 (bitconvert (v8i16 VECREG:$src))), (v2f64 VECREG:$src)>;
3056def : Pat<(v2f64 (bitconvert (v4i32 VECREG:$src))), (v2f64 VECREG:$src)>;
3057def : Pat<(v2f64 (bitconvert (v2i64 VECREG:$src))), (v2f64 VECREG:$src)>;
3058def : Pat<(v2f64 (bitconvert (v2f64 VECREG:$src))), (v2f64 VECREG:$src)>;
3059
3060def : Pat<(f32 (bitconvert (i32 R32C:$src))), (f32 R32FP:$src)>;
3061
3062//===----------------------------------------------------------------------===//
3063// Instruction patterns:
3064//===----------------------------------------------------------------------===//
3065
3066// General 32-bit constants:
3067def : Pat<(i32 imm:$imm),
3068 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm))>;
3069
3070// Single precision float constants:
3071def : Pat<(SPUFPconstant (f32 fpimm:$imm)),
3072 (IOHLf32 (ILHUf32 (HI16_f32 fpimm:$imm)), (LO16_f32 fpimm:$imm))>;
3073
3074// General constant 32-bit vectors
3075def : Pat<(v4i32 v4i32Imm:$imm),
3076 (IOHLvec (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))),
3077 (LO16_vec v4i32Imm:$imm))>;
3078
3079//===----------------------------------------------------------------------===//
3080// Call instruction patterns:
3081//===----------------------------------------------------------------------===//
3082// Return void
3083def : Pat<(ret),
3084 (RET)>;
3085
3086//===----------------------------------------------------------------------===//
3087// Zero/Any/Sign extensions
3088//===----------------------------------------------------------------------===//
3089
3090// zext 1->32: Zero extend i1 to i32
3091def : Pat<(SPUextract_i1_zext R32C:$rSrc),
3092 (ANDIr32 R32C:$rSrc, 0x1)>;
3093
3094// sext 8->32: Sign extend bytes to words
3095def : Pat<(sext_inreg R32C:$rSrc, i8),
3096 (XSHWr32 (XSBHr32 R32C:$rSrc))>;
3097
3098def : Pat<(SPUextract_i8_sext VECREG:$rSrc),
3099 (XSHWr32 (XSBHr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc),
3100 (v4i32 VECREG:$rSrc))))>;
3101
3102def : Pat<(SPUextract_i8_zext VECREG:$rSrc),
3103 (ANDIr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc), (v4i32 VECREG:$rSrc)),
3104 0xff)>;
3105
3106// zext 16->32: Zero extend halfwords to words (note that we have to juggle the
3107// 0xffff constant since it will not fit into an immediate.)
3108def : Pat<(i32 (zext R16C:$rSrc)),
3109 (AND2To4 R16C:$rSrc, (ILAr32 0xffff))>;
3110
3111def : Pat<(i32 (zext (and R16C:$rSrc, 0xf))),
3112 (ANDI2To4 R16C:$rSrc, 0xf)>;
3113
3114def : Pat<(i32 (zext (and R16C:$rSrc, 0xff))),
3115 (ANDI2To4 R16C:$rSrc, 0xff)>;
3116
3117def : Pat<(i32 (zext (and R16C:$rSrc, 0xfff))),
3118 (ANDI2To4 R16C:$rSrc, 0xfff)>;
3119
3120// anyext 16->32: Extend 16->32 bits, irrespective of sign
3121def : Pat<(i32 (anyext R16C:$rSrc)),
3122 (ORI2To4 R16C:$rSrc, 0)>;
3123
3124//===----------------------------------------------------------------------===//
3125// Address translation: SPU, like PPC, has to split addresses into high and
3126// low parts in order to load them into a register.
3127//===----------------------------------------------------------------------===//
3128
3129def : Pat<(SPUhi tglobaladdr:$in, 0), (ILHUhi tglobaladdr:$in)>;
3130def : Pat<(SPUlo tglobaladdr:$in, 0), (ILAlo tglobaladdr:$in)>;
3131def : Pat<(SPUdform tglobaladdr:$in, imm:$imm), (ILAlsa tglobaladdr:$in)>;
3132def : Pat<(SPUhi tconstpool:$in , 0), (ILHUhi tconstpool:$in)>;
3133def : Pat<(SPUlo tconstpool:$in , 0), (ILAlo tconstpool:$in)>;
3134def : Pat<(SPUdform tconstpool:$in, imm:$imm), (ILAlsa tconstpool:$in)>;
3135def : Pat<(SPUhi tjumptable:$in, 0), (ILHUhi tjumptable:$in)>;
3136def : Pat<(SPUlo tjumptable:$in, 0), (ILAlo tjumptable:$in)>;
3137def : Pat<(SPUdform tjumptable:$in, imm:$imm), (ILAlsa tjumptable:$in)>;
3138
3139// Force load of global address to a register. These forms show up in
3140// SPUISD::DFormAddr pseudo instructions:
3141/*
3142def : Pat<(add tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
3143def : Pat<(add tconstpool:$in, 0), (ILAlsa tglobaladdr:$in)>;
3144def : Pat<(add tjumptable:$in, 0), (ILAlsa tglobaladdr:$in)>;
3145 */
3146// Instrinsics:
3147include "CellSDKIntrinsics.td"