blob: 4384c2889662a51aa05000c54aceb7bfaf042227 [file] [log] [blame]
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00001//===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the "Instituto Nokia de Tecnologia" and
6// is distributed under the University of Illinois Open Source
7// License. See LICENSE.TXT for details.
8//
9//===----------------------------------------------------------------------===//
10//
11// This file contains the ARM implementation of the TargetInstrInfo class.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARMInstrInfo.h"
16#include "ARM.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "ARMGenInstrInfo.inc"
19using namespace llvm;
20
21ARMInstrInfo::ARMInstrInfo()
22 : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])) {
23}
24
Rafael Espindola46adf812006-08-08 20:35:03 +000025const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
26 return &ARM::IntRegsRegClass;
27}
28
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000029/// Return true if the instruction is a register to register move and
30/// leave the source and dest operands in the passed parameters.
31///
32bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
33 unsigned &SrcReg, unsigned &DstReg) const {
Rafael Espindola49e44152006-06-27 21:52:45 +000034 MachineOpCode oc = MI.getOpcode();
35 switch (oc) {
36 default:
37 return false;
38 case ARM::movrr:
39 assert(MI.getNumOperands() == 2 &&
40 MI.getOperand(0).isRegister() &&
41 MI.getOperand(1).isRegister() &&
42 "Invalid ARM MOV instruction");
43 SrcReg = MI.getOperand(1).getReg();;
44 DstReg = MI.getOperand(0).getReg();;
45 return true;
46 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000047}