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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 4a4f15122d4db278e4004971ba91e0020ef56ef6 / . / lib / Target / X86 / X86InstrSSE.td
blob: f2466b5efbd3666aafe19d8057ede35e4f29f52e [file] [log] [blame]
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1//====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by Evan Cheng and is distributed under the University
6// of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 SSE instruction set, defining the instructions,
11// and properties of the instructions which are needed for code generation,
12// machine code emission, and analysis.
13//
14//===----------------------------------------------------------------------===//
15
16
17//===----------------------------------------------------------------------===//
18// SSE specific DAG Nodes.
19//===----------------------------------------------------------------------===//
20
21def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23
24def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad, [SDNPHasChain]>;
25def X86loadu : SDNode<"X86ISD::LOAD_UA", SDTLoad, [SDNPHasChain]>;
26def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
38 [SDNPHasChain, SDNPOutFlag]>;
39def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
40 [SDNPHasChain, SDNPOutFlag]>;
41def X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
42def X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
43def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
44
45//===----------------------------------------------------------------------===//
46// SSE 'Special' Instructions
47//===----------------------------------------------------------------------===//
48
49def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
50 "#IMPLICIT_DEF $dst",
51 [(set VR128:$dst, (v4f32 (undef)))]>,
52 Requires<[HasSSE1]>;
53def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
54 "#IMPLICIT_DEF $dst",
55 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
56def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
57 "#IMPLICIT_DEF $dst",
58 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
59
60//===----------------------------------------------------------------------===//
61// SSE Complex Patterns
62//===----------------------------------------------------------------------===//
63
64// These are 'extloads' from a scalar to the low element of a vector, zeroing
65// the top elements. These are used for the SSE 'ss' and 'sd' instruction
66// forms.
67def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
68 [SDNPHasChain]>;
69def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
70 [SDNPHasChain]>;
71
72def ssmem : Operand<v4f32> {
73 let PrintMethod = "printf32mem";
74 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
75}
76def sdmem : Operand<v2f64> {
77 let PrintMethod = "printf64mem";
78 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
79}
80
81//===----------------------------------------------------------------------===//
82// SSE pattern fragments
83//===----------------------------------------------------------------------===//
84
85def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
86def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
87
88def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
89def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
90def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
91def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
92
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]93// Like 'store', but always requires natural alignment.
94def alignedstore : PatFrag<(ops node:$val, node:$ptr),
95 (st node:$val, node:$ptr), [{
96 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
97 return !ST->isTruncatingStore() &&
98 ST->getAddressingMode() == ISD::UNINDEXED &&
99 ST->getAlignment() * 8 >= MVT::getSizeInBits(ST->getStoredVT());
100 return false;
101}]>;
102
103// Like 'load', but always requires natural alignment.
104def alignedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
105 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
106 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
107 LD->getAddressingMode() == ISD::UNINDEXED &&
108 LD->getAlignment() * 8 >= MVT::getSizeInBits(LD->getLoadedVT());
109 return false;
110}]>;
111
112def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
113def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
114def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
115def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
116
117// Like 'load', but uses special alignment checks suitable for use in
118// memory operands in most SSE instructions, which are required to
119// be naturally aligned on some targets but not on others.
120// FIXME: Actually implement support for targets that don't require the
121// alignment. This probably wants a subtarget predicate.
122def memop : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
123 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
124 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
125 LD->getAddressingMode() == ISD::UNINDEXED &&
126 LD->getAlignment() * 8 >= MVT::getSizeInBits(LD->getLoadedVT());
127 return false;
128}]>;
129
130def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
131def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
132def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
133def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
134
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]135def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
136def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
137def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
138def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
139def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
140def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
141
142def fp32imm0 : PatLeaf<(f32 fpimm), [{
143 return N->isExactlyValue(+0.0);
144}]>;
145
146def PSxLDQ_imm : SDNodeXForm<imm, [{
147 // Transformation function: imm >> 3
148 return getI32Imm(N->getValue() >> 3);
149}]>;
150
151// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
152// SHUFP* etc. imm.
153def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
154 return getI8Imm(X86::getShuffleSHUFImmediate(N));
155}]>;
156
157// SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
158// PSHUFHW imm.
159def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
160 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
161}]>;
162
163// SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
164// PSHUFLW imm.
165def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
166 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
167}]>;
168
169def SSE_splat_mask : PatLeaf<(build_vector), [{
170 return X86::isSplatMask(N);
171}], SHUFFLE_get_shuf_imm>;
172
173def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
174 return X86::isSplatLoMask(N);
175}]>;
176
177def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
178 return X86::isMOVHLPSMask(N);
179}]>;
180
181def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
182 return X86::isMOVHLPS_v_undef_Mask(N);
183}]>;
184
185def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
186 return X86::isMOVHPMask(N);
187}]>;
188
189def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
190 return X86::isMOVLPMask(N);
191}]>;
192
193def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
194 return X86::isMOVLMask(N);
195}]>;
196
197def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
198 return X86::isMOVSHDUPMask(N);
199}]>;
200
201def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
202 return X86::isMOVSLDUPMask(N);
203}]>;
204
205def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
206 return X86::isUNPCKLMask(N);
207}]>;
208
209def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
210 return X86::isUNPCKHMask(N);
211}]>;
212
213def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
214 return X86::isUNPCKL_v_undef_Mask(N);
215}]>;
216
217def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
218 return X86::isUNPCKH_v_undef_Mask(N);
219}]>;
220
221def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
222 return X86::isPSHUFDMask(N);
223}], SHUFFLE_get_shuf_imm>;
224
225def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
226 return X86::isPSHUFHWMask(N);
227}], SHUFFLE_get_pshufhw_imm>;
228
229def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
230 return X86::isPSHUFLWMask(N);
231}], SHUFFLE_get_pshuflw_imm>;
232
233def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
234 return X86::isPSHUFDMask(N);
235}], SHUFFLE_get_shuf_imm>;
236
237def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
238 return X86::isSHUFPMask(N);
239}], SHUFFLE_get_shuf_imm>;
240
241def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
242 return X86::isSHUFPMask(N);
243}], SHUFFLE_get_shuf_imm>;
244
245//===----------------------------------------------------------------------===//
246// SSE scalar FP Instructions
247//===----------------------------------------------------------------------===//
248
249// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
250// scheduler into a branch sequence.
251let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
252 def CMOV_FR32 : I<0, Pseudo,
253 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
254 "#CMOV_FR32 PSEUDO!",
255 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
256 def CMOV_FR64 : I<0, Pseudo,
257 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
258 "#CMOV_FR64 PSEUDO!",
259 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
260 def CMOV_V4F32 : I<0, Pseudo,
261 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
262 "#CMOV_V4F32 PSEUDO!",
263 [(set VR128:$dst,
264 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
265 def CMOV_V2F64 : I<0, Pseudo,
266 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
267 "#CMOV_V2F64 PSEUDO!",
268 [(set VR128:$dst,
269 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
270 def CMOV_V2I64 : I<0, Pseudo,
271 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
272 "#CMOV_V2I64 PSEUDO!",
273 [(set VR128:$dst,
274 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
275}
276
277//===----------------------------------------------------------------------===//
278// SSE1 Instructions
279//===----------------------------------------------------------------------===//
280
281// SSE1 Instruction Templates:
282//
283// SSI - SSE1 instructions with XS prefix.
284// PSI - SSE1 instructions with TB prefix.
285// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
286
287class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
288 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
289class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
290 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
291class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
292 : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
293
294// Move Instructions
295def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
296 "movss {$src, $dst|$dst, $src}", []>;
297def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
298 "movss {$src, $dst|$dst, $src}",
299 [(set FR32:$dst, (loadf32 addr:$src))]>;
300def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
301 "movss {$src, $dst|$dst, $src}",
302 [(store FR32:$src, addr:$dst)]>;
303
304// Conversion instructions
305def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (ops GR32:$dst, FR32:$src),
306 "cvttss2si {$src, $dst|$dst, $src}",
307 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
308def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
309 "cvttss2si {$src, $dst|$dst, $src}",
310 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
311def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (ops FR32:$dst, GR32:$src),
312 "cvtsi2ss {$src, $dst|$dst, $src}",
313 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
314def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
315 "cvtsi2ss {$src, $dst|$dst, $src}",
316 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
317
318// Match intrinsics which expect XMM operand(s).
319def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
320 "cvtss2si {$src, $dst|$dst, $src}",
321 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
322def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
323 "cvtss2si {$src, $dst|$dst, $src}",
324 [(set GR32:$dst, (int_x86_sse_cvtss2si
325 (load addr:$src)))]>;
326
327// Aliases for intrinsics
328def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
329 "cvttss2si {$src, $dst|$dst, $src}",
330 [(set GR32:$dst,
331 (int_x86_sse_cvttss2si VR128:$src))]>;
332def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
333 "cvttss2si {$src, $dst|$dst, $src}",
334 [(set GR32:$dst,
335 (int_x86_sse_cvttss2si(load addr:$src)))]>;
336
337let isTwoAddress = 1 in {
338 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
339 (ops VR128:$dst, VR128:$src1, GR32:$src2),
340 "cvtsi2ss {$src2, $dst|$dst, $src2}",
341 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
342 GR32:$src2))]>;
343 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
344 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
345 "cvtsi2ss {$src2, $dst|$dst, $src2}",
346 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
347 (loadi32 addr:$src2)))]>;
348}
349
350// Comparison instructions
351let isTwoAddress = 1 in {
352 def CMPSSrr : SSI<0xC2, MRMSrcReg,
353 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
354 "cmp${cc}ss {$src, $dst|$dst, $src}",
355 []>;
356 def CMPSSrm : SSI<0xC2, MRMSrcMem,
357 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
358 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
359}
360
361def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
362 "ucomiss {$src2, $src1|$src1, $src2}",
363 [(X86cmp FR32:$src1, FR32:$src2)]>;
364def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
365 "ucomiss {$src2, $src1|$src1, $src2}",
366 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
367
368// Aliases to match intrinsics which expect XMM operand(s).
369let isTwoAddress = 1 in {
370 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
371 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
372 "cmp${cc}ss {$src, $dst|$dst, $src}",
373 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
374 VR128:$src, imm:$cc))]>;
375 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
376 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
377 "cmp${cc}ss {$src, $dst|$dst, $src}",
378 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
379 (load addr:$src), imm:$cc))]>;
380}
381
382def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
383 "ucomiss {$src2, $src1|$src1, $src2}",
384 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
385def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
386 "ucomiss {$src2, $src1|$src1, $src2}",
387 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2))]>;
388
389def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
390 "comiss {$src2, $src1|$src1, $src2}",
391 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
392def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
393 "comiss {$src2, $src1|$src1, $src2}",
394 [(X86comi (v4f32 VR128:$src1), (load addr:$src2))]>;
395
396// Aliases of packed SSE1 instructions for scalar use. These all have names that
397// start with 'Fs'.
398
399// Alias instructions that map fld0 to pxor for sse.
400def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
401 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
402 Requires<[HasSSE1]>, TB, OpSize;
403
404// Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
405// disregarded.
406def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
407 "movaps {$src, $dst|$dst, $src}", []>;
408
409// Alias instruction to load FR32 from f128mem using movaps. Upper bits are
410// disregarded.
411def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
412 "movaps {$src, $dst|$dst, $src}",
413 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
414
415// Alias bitwise logical operations using SSE logical ops on packed FP values.
416let isTwoAddress = 1 in {
417let isCommutable = 1 in {
418 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
419 "andps {$src2, $dst|$dst, $src2}",
420 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
421 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
422 "orps {$src2, $dst|$dst, $src2}",
423 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
424 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
425 "xorps {$src2, $dst|$dst, $src2}",
426 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
427}
428
429def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
430 "andps {$src2, $dst|$dst, $src2}",
431 [(set FR32:$dst, (X86fand FR32:$src1,
432 (X86loadpf32 addr:$src2)))]>;
433def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
434 "orps {$src2, $dst|$dst, $src2}",
435 [(set FR32:$dst, (X86for FR32:$src1,
436 (X86loadpf32 addr:$src2)))]>;
437def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
438 "xorps {$src2, $dst|$dst, $src2}",
439 [(set FR32:$dst, (X86fxor FR32:$src1,
440 (X86loadpf32 addr:$src2)))]>;
441
442def FsANDNPSrr : PSI<0x55, MRMSrcReg,
443 (ops FR32:$dst, FR32:$src1, FR32:$src2),
444 "andnps {$src2, $dst|$dst, $src2}", []>;
445def FsANDNPSrm : PSI<0x55, MRMSrcMem,
446 (ops FR32:$dst, FR32:$src1, f128mem:$src2),
447 "andnps {$src2, $dst|$dst, $src2}", []>;
448}
449
450/// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
451///
452/// In addition, we also have a special variant of the scalar form here to
453/// represent the associated intrinsic operation. This form is unlike the
454/// plain scalar form, in that it takes an entire vector (instead of a scalar)
455/// and leaves the top elements undefined.
456///
457/// These three forms can each be reg+reg or reg+mem, so there are a total of
458/// six "instructions".
459///
460let isTwoAddress = 1 in {
461multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
462 SDNode OpNode, Intrinsic F32Int,
463 bit Commutable = 0> {
464 // Scalar operation, reg+reg.
465 def SSrr : SSI<opc, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
466 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
467 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
468 let isCommutable = Commutable;
469 }
470
471 // Scalar operation, reg+mem.
472 def SSrm : SSI<opc, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
473 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
474 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
475
476 // Vector operation, reg+reg.
477 def PSrr : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
478 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
479 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
480 let isCommutable = Commutable;
481 }
482
483 // Vector operation, reg+mem.
484 def PSrm : PSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
485 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]486 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]487
488 // Intrinsic operation, reg+reg.
489 def SSrr_Int : SSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
490 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
491 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
492 let isCommutable = Commutable;
493 }
494
495 // Intrinsic operation, reg+mem.
496 def SSrm_Int : SSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, ssmem:$src2),
497 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
498 [(set VR128:$dst, (F32Int VR128:$src1,
499 sse_load_f32:$src2))]>;
500}
501}
502
503// Arithmetic instructions
504defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
505defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
506defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
507defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
508
509/// sse1_fp_binop_rm - Other SSE1 binops
510///
511/// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
512/// instructions for a full-vector intrinsic form. Operations that map
513/// onto C operators don't use this form since they just use the plain
514/// vector form instead of having a separate vector intrinsic form.
515///
516/// This provides a total of eight "instructions".
517///
518let isTwoAddress = 1 in {
519multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
520 SDNode OpNode,
521 Intrinsic F32Int,
522 Intrinsic V4F32Int,
523 bit Commutable = 0> {
524
525 // Scalar operation, reg+reg.
526 def SSrr : SSI<opc, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
527 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
528 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
529 let isCommutable = Commutable;
530 }
531
532 // Scalar operation, reg+mem.
533 def SSrm : SSI<opc, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
534 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
535 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
536
537 // Vector operation, reg+reg.
538 def PSrr : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
539 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
540 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
541 let isCommutable = Commutable;
542 }
543
544 // Vector operation, reg+mem.
545 def PSrm : PSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
546 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]547 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]548
549 // Intrinsic operation, reg+reg.
550 def SSrr_Int : SSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
551 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
552 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
553 let isCommutable = Commutable;
554 }
555
556 // Intrinsic operation, reg+mem.
557 def SSrm_Int : SSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, ssmem:$src2),
558 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
559 [(set VR128:$dst, (F32Int VR128:$src1,
560 sse_load_f32:$src2))]>;
561
562 // Vector intrinsic operation, reg+reg.
563 def PSrr_Int : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
564 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
565 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
566 let isCommutable = Commutable;
567 }
568
569 // Vector intrinsic operation, reg+mem.
570 def PSrm_Int : PSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
571 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
572 [(set VR128:$dst, (V4F32Int VR128:$src1, (load addr:$src2)))]>;
573}
574}
575
576defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
577 int_x86_sse_max_ss, int_x86_sse_max_ps>;
578defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
579 int_x86_sse_min_ss, int_x86_sse_min_ps>;
580
581//===----------------------------------------------------------------------===//
582// SSE packed FP Instructions
583
584// Move Instructions
585def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
586 "movaps {$src, $dst|$dst, $src}", []>;
587def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
588 "movaps {$src, $dst|$dst, $src}",
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]589 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]590
591def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
592 "movaps {$src, $dst|$dst, $src}",
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]593 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]594
595def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
596 "movups {$src, $dst|$dst, $src}", []>;
597def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
598 "movups {$src, $dst|$dst, $src}",
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]599 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]600def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
601 "movups {$src, $dst|$dst, $src}",
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]602 [(store (v4f32 VR128:$src), addr:$dst)]>;
603
604// Intrinsic forms of MOVUPS load and store
605def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
606 "movups {$src, $dst|$dst, $src}",
607 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
608def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
609 "movups {$src, $dst|$dst, $src}",
610 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]611
612let isTwoAddress = 1 in {
613 let AddedComplexity = 20 in {
614 def MOVLPSrm : PSI<0x12, MRMSrcMem,
615 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
616 "movlps {$src2, $dst|$dst, $src2}",
617 [(set VR128:$dst,
618 (v4f32 (vector_shuffle VR128:$src1,
619 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
620 MOVLP_shuffle_mask)))]>;
621 def MOVHPSrm : PSI<0x16, MRMSrcMem,
622 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
623 "movhps {$src2, $dst|$dst, $src2}",
624 [(set VR128:$dst,
625 (v4f32 (vector_shuffle VR128:$src1,
626 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
627 MOVHP_shuffle_mask)))]>;
628 } // AddedComplexity
629} // isTwoAddress
630
631def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
632 "movlps {$src, $dst|$dst, $src}",
633 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
634 (iPTR 0))), addr:$dst)]>;
635
636// v2f64 extract element 1 is always custom lowered to unpack high to low
637// and extract element 0 so the non-store version isn't too horrible.
638def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
639 "movhps {$src, $dst|$dst, $src}",
640 [(store (f64 (vector_extract
641 (v2f64 (vector_shuffle
642 (bc_v2f64 (v4f32 VR128:$src)), (undef),
643 UNPCKH_shuffle_mask)), (iPTR 0))),
644 addr:$dst)]>;
645
646let isTwoAddress = 1 in {
647let AddedComplexity = 15 in {
648def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
649 "movlhps {$src2, $dst|$dst, $src2}",
650 [(set VR128:$dst,
651 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
652 MOVHP_shuffle_mask)))]>;
653
654def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
655 "movhlps {$src2, $dst|$dst, $src2}",
656 [(set VR128:$dst,
657 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
658 MOVHLPS_shuffle_mask)))]>;
659} // AddedComplexity
660} // isTwoAddress
661
662
663
664// Arithmetic
665
666/// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
667///
668/// In addition, we also have a special variant of the scalar form here to
669/// represent the associated intrinsic operation. This form is unlike the
670/// plain scalar form, in that it takes an entire vector (instead of a
671/// scalar) and leaves the top elements undefined.
672///
673/// And, we have a special variant form for a full-vector intrinsic form.
674///
675/// These four forms can each have a reg or a mem operand, so there are a
676/// total of eight "instructions".
677///
678multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
679 SDNode OpNode,
680 Intrinsic F32Int,
681 Intrinsic V4F32Int,
682 bit Commutable = 0> {
683 // Scalar operation, reg.
684 def SSr : SSI<opc, MRMSrcReg, (ops FR32:$dst, FR32:$src),
685 !strconcat(OpcodeStr, "ss {$src, $dst|$dst, $src}"),
686 [(set FR32:$dst, (OpNode FR32:$src))]> {
687 let isCommutable = Commutable;
688 }
689
690 // Scalar operation, mem.
691 def SSm : SSI<opc, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
692 !strconcat(OpcodeStr, "ss {$src, $dst|$dst, $src}"),
693 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
694
695 // Vector operation, reg.
696 def PSr : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src),
697 !strconcat(OpcodeStr, "ps {$src, $dst|$dst, $src}"),
698 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
699 let isCommutable = Commutable;
700 }
701
702 // Vector operation, mem.
703 def PSm : PSI<opc, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
704 !strconcat(OpcodeStr, "ps {$src, $dst|$dst, $src}"),
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]705 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]706
707 // Intrinsic operation, reg.
708 def SSr_Int : SSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src),
709 !strconcat(OpcodeStr, "ss {$src, $dst|$dst, $src}"),
710 [(set VR128:$dst, (F32Int VR128:$src))]> {
711 let isCommutable = Commutable;
712 }
713
714 // Intrinsic operation, mem.
715 def SSm_Int : SSI<opc, MRMSrcMem, (ops VR128:$dst, ssmem:$src),
716 !strconcat(OpcodeStr, "ss {$src, $dst|$dst, $src}"),
717 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
718
719 // Vector intrinsic operation, reg
720 def PSr_Int : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src),
721 !strconcat(OpcodeStr, "ps {$src, $dst|$dst, $src}"),
722 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
723 let isCommutable = Commutable;
724 }
725
726 // Vector intrinsic operation, mem
727 def PSm_Int : PSI<opc, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
728 !strconcat(OpcodeStr, "ps {$src, $dst|$dst, $src}"),
729 [(set VR128:$dst, (V4F32Int (load addr:$src)))]>;
730}
731
732// Square root.
733defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
734 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
735
736// Reciprocal approximations. Note that these typically require refinement
737// in order to obtain suitable precision.
738defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
739 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
740defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
741 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
742
743// Logical
744let isTwoAddress = 1 in {
745 let isCommutable = 1 in {
746 def ANDPSrr : PSI<0x54, MRMSrcReg,
747 (ops VR128:$dst, VR128:$src1, VR128:$src2),
748 "andps {$src2, $dst|$dst, $src2}",
749 [(set VR128:$dst, (v2i64
750 (and VR128:$src1, VR128:$src2)))]>;
751 def ORPSrr : PSI<0x56, MRMSrcReg,
752 (ops VR128:$dst, VR128:$src1, VR128:$src2),
753 "orps {$src2, $dst|$dst, $src2}",
754 [(set VR128:$dst, (v2i64
755 (or VR128:$src1, VR128:$src2)))]>;
756 def XORPSrr : PSI<0x57, MRMSrcReg,
757 (ops VR128:$dst, VR128:$src1, VR128:$src2),
758 "xorps {$src2, $dst|$dst, $src2}",
759 [(set VR128:$dst, (v2i64
760 (xor VR128:$src1, VR128:$src2)))]>;
761 }
762
763 def ANDPSrm : PSI<0x54, MRMSrcMem,
764 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
765 "andps {$src2, $dst|$dst, $src2}",
766 [(set VR128:$dst, (and VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]767 (bc_v2i64 (memopv4f32 addr:$src2))))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]768 def ORPSrm : PSI<0x56, MRMSrcMem,
769 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
770 "orps {$src2, $dst|$dst, $src2}",
771 [(set VR128:$dst, (or VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]772 (bc_v2i64 (memopv4f32 addr:$src2))))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]773 def XORPSrm : PSI<0x57, MRMSrcMem,
774 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
775 "xorps {$src2, $dst|$dst, $src2}",
776 [(set VR128:$dst, (xor VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]777 (bc_v2i64 (memopv4f32 addr:$src2))))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]778 def ANDNPSrr : PSI<0x55, MRMSrcReg,
779 (ops VR128:$dst, VR128:$src1, VR128:$src2),
780 "andnps {$src2, $dst|$dst, $src2}",
781 [(set VR128:$dst,
782 (v2i64 (and (xor VR128:$src1,
783 (bc_v2i64 (v4i32 immAllOnesV))),
784 VR128:$src2)))]>;
785 def ANDNPSrm : PSI<0x55, MRMSrcMem,
786 (ops VR128:$dst, VR128:$src1,f128mem:$src2),
787 "andnps {$src2, $dst|$dst, $src2}",
788 [(set VR128:$dst,
789 (v2i64 (and (xor VR128:$src1,
790 (bc_v2i64 (v4i32 immAllOnesV))),
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]791 (bc_v2i64 (memopv4f32 addr:$src2)))))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]792}
793
794let isTwoAddress = 1 in {
795 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
796 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
797 "cmp${cc}ps {$src, $dst|$dst, $src}",
798 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
799 VR128:$src, imm:$cc))]>;
800 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
801 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
802 "cmp${cc}ps {$src, $dst|$dst, $src}",
803 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
804 (load addr:$src), imm:$cc))]>;
805}
806
807// Shuffle and unpack instructions
808let isTwoAddress = 1 in {
809 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
810 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
811 (ops VR128:$dst, VR128:$src1,
812 VR128:$src2, i32i8imm:$src3),
813 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
814 [(set VR128:$dst,
815 (v4f32 (vector_shuffle
816 VR128:$src1, VR128:$src2,
817 SHUFP_shuffle_mask:$src3)))]>;
818 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
819 (ops VR128:$dst, VR128:$src1,
820 f128mem:$src2, i32i8imm:$src3),
821 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
822 [(set VR128:$dst,
823 (v4f32 (vector_shuffle
824 VR128:$src1, (load addr:$src2),
825 SHUFP_shuffle_mask:$src3)))]>;
826
827 let AddedComplexity = 10 in {
828 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
829 (ops VR128:$dst, VR128:$src1, VR128:$src2),
830 "unpckhps {$src2, $dst|$dst, $src2}",
831 [(set VR128:$dst,
832 (v4f32 (vector_shuffle
833 VR128:$src1, VR128:$src2,
834 UNPCKH_shuffle_mask)))]>;
835 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
836 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
837 "unpckhps {$src2, $dst|$dst, $src2}",
838 [(set VR128:$dst,
839 (v4f32 (vector_shuffle
840 VR128:$src1, (load addr:$src2),
841 UNPCKH_shuffle_mask)))]>;
842
843 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
844 (ops VR128:$dst, VR128:$src1, VR128:$src2),
845 "unpcklps {$src2, $dst|$dst, $src2}",
846 [(set VR128:$dst,
847 (v4f32 (vector_shuffle
848 VR128:$src1, VR128:$src2,
849 UNPCKL_shuffle_mask)))]>;
850 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
851 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
852 "unpcklps {$src2, $dst|$dst, $src2}",
853 [(set VR128:$dst,
854 (v4f32 (vector_shuffle
855 VR128:$src1, (load addr:$src2),
856 UNPCKL_shuffle_mask)))]>;
857 } // AddedComplexity
858} // isTwoAddress
859
860// Mask creation
861def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
862 "movmskps {$src, $dst|$dst, $src}",
863 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
864def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
865 "movmskpd {$src, $dst|$dst, $src}",
866 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
867
868// Prefetching loads.
869// TODO: no intrinsics for these?
870def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src), "prefetcht0 $src", []>;
871def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src), "prefetcht1 $src", []>;
872def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src), "prefetcht2 $src", []>;
873def PREFETCHNTA : PSI<0x18, MRM0m, (ops i8mem:$src), "prefetchnta $src", []>;
874
875// Non-temporal stores
876def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
877 "movntps {$src, $dst|$dst, $src}",
878 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
879
880// Load, store, and memory fence
881def SFENCE : PSI<0xAE, MRM7m, (ops), "sfence", [(int_x86_sse_sfence)]>;
882
883// MXCSR register
884def LDMXCSR : PSI<0xAE, MRM2m, (ops i32mem:$src),
885 "ldmxcsr $src", [(int_x86_sse_ldmxcsr addr:$src)]>;
886def STMXCSR : PSI<0xAE, MRM3m, (ops i32mem:$dst),
887 "stmxcsr $dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
888
889// Alias instructions that map zero vector to pxor / xorp* for sse.
890// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
891let isReMaterializable = 1 in
892def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst),
893 "xorps $dst, $dst",
894 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
895
896// FR32 to 128-bit vector conversion.
897def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
898 "movss {$src, $dst|$dst, $src}",
899 [(set VR128:$dst,
900 (v4f32 (scalar_to_vector FR32:$src)))]>;
901def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
902 "movss {$src, $dst|$dst, $src}",
903 [(set VR128:$dst,
904 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
905
906// FIXME: may not be able to eliminate this movss with coalescing the src and
907// dest register classes are different. We really want to write this pattern
908// like this:
909// def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
910// (f32 FR32:$src)>;
911def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
912 "movss {$src, $dst|$dst, $src}",
913 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
914 (iPTR 0)))]>;
915def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
916 "movss {$src, $dst|$dst, $src}",
917 [(store (f32 (vector_extract (v4f32 VR128:$src),
918 (iPTR 0))), addr:$dst)]>;
919
920
921// Move to lower bits of a VR128, leaving upper bits alone.
922// Three operand (but two address) aliases.
923let isTwoAddress = 1 in {
924 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
925 (ops VR128:$dst, VR128:$src1, FR32:$src2),
926 "movss {$src2, $dst|$dst, $src2}", []>;
927
928 let AddedComplexity = 15 in
929 def MOVLPSrr : SSI<0x10, MRMSrcReg,
930 (ops VR128:$dst, VR128:$src1, VR128:$src2),
931 "movss {$src2, $dst|$dst, $src2}",
932 [(set VR128:$dst,
933 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
934 MOVL_shuffle_mask)))]>;
935}
936
937// Move to lower bits of a VR128 and zeroing upper bits.
938// Loading from memory automatically zeroing upper bits.
939let AddedComplexity = 20 in
940def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
941 "movss {$src, $dst|$dst, $src}",
942 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV,
943 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
944 MOVL_shuffle_mask)))]>;
945
946
947//===----------------------------------------------------------------------===//
948// SSE2 Instructions
949//===----------------------------------------------------------------------===//
950
951// SSE2 Instruction Templates:
952//
953// SDI - SSE2 instructions with XD prefix.
954// PDI - SSE2 instructions with TB and OpSize prefixes.
955// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
956
957class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
958 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
959class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
960 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
961class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
962 : Ii8<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
963
964// Move Instructions
965def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
966 "movsd {$src, $dst|$dst, $src}", []>;
967def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
968 "movsd {$src, $dst|$dst, $src}",
969 [(set FR64:$dst, (loadf64 addr:$src))]>;
970def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
971 "movsd {$src, $dst|$dst, $src}",
972 [(store FR64:$src, addr:$dst)]>;
973
974// Conversion instructions
975def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (ops GR32:$dst, FR64:$src),
976 "cvttsd2si {$src, $dst|$dst, $src}",
977 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
978def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f64mem:$src),
979 "cvttsd2si {$src, $dst|$dst, $src}",
980 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
981def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
982 "cvtsd2ss {$src, $dst|$dst, $src}",
983 [(set FR32:$dst, (fround FR64:$src))]>;
984def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
985 "cvtsd2ss {$src, $dst|$dst, $src}",
986 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
987def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (ops FR64:$dst, GR32:$src),
988 "cvtsi2sd {$src, $dst|$dst, $src}",
989 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
990def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
991 "cvtsi2sd {$src, $dst|$dst, $src}",
992 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
993
994// SSE2 instructions with XS prefix
995def CVTSS2SDrr : I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
996 "cvtss2sd {$src, $dst|$dst, $src}",
997 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
998 Requires<[HasSSE2]>;
999def CVTSS2SDrm : I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
1000 "cvtss2sd {$src, $dst|$dst, $src}",
1001 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1002 Requires<[HasSSE2]>;
1003
1004// Match intrinsics which expect XMM operand(s).
1005def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1006 "cvtsd2si {$src, $dst|$dst, $src}",
1007 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1008def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
1009 "cvtsd2si {$src, $dst|$dst, $src}",
1010 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1011 (load addr:$src)))]>;
1012
1013// Aliases for intrinsics
1014def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1015 "cvttsd2si {$src, $dst|$dst, $src}",
1016 [(set GR32:$dst,
1017 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1018def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
1019 "cvttsd2si {$src, $dst|$dst, $src}",
1020 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1021 (load addr:$src)))]>;
1022
1023// Comparison instructions
1024let isTwoAddress = 1 in {
1025 def CMPSDrr : SDI<0xC2, MRMSrcReg,
1026 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
1027 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
1028 def CMPSDrm : SDI<0xC2, MRMSrcMem,
1029 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
1030 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
1031}
1032
1033def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
1034 "ucomisd {$src2, $src1|$src1, $src2}",
1035 [(X86cmp FR64:$src1, FR64:$src2)]>;
1036def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
1037 "ucomisd {$src2, $src1|$src1, $src2}",
1038 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
1039
1040// Aliases to match intrinsics which expect XMM operand(s).
1041let isTwoAddress = 1 in {
1042 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
1043 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1044 "cmp${cc}sd {$src, $dst|$dst, $src}",
1045 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1046 VR128:$src, imm:$cc))]>;
1047 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
1048 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
1049 "cmp${cc}sd {$src, $dst|$dst, $src}",
1050 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1051 (load addr:$src), imm:$cc))]>;
1052}
1053
1054def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
1055 "ucomisd {$src2, $src1|$src1, $src2}",
1056 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
1057def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
1058 "ucomisd {$src2, $src1|$src1, $src2}",
1059 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2))]>;
1060
1061def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
1062 "comisd {$src2, $src1|$src1, $src2}",
1063 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
1064def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
1065 "comisd {$src2, $src1|$src1, $src2}",
1066 [(X86comi (v2f64 VR128:$src1), (load addr:$src2))]>;
1067
1068// Aliases of packed SSE2 instructions for scalar use. These all have names that
1069// start with 'Fs'.
1070
1071// Alias instructions that map fld0 to pxor for sse.
1072def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
1073 "pxor $dst, $dst", [(set FR64:$dst, fpimm0)]>,
1074 Requires<[HasSSE2]>, TB, OpSize;
1075
1076// Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1077// disregarded.
1078def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
1079 "movapd {$src, $dst|$dst, $src}", []>;
1080
1081// Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1082// disregarded.
1083def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
1084 "movapd {$src, $dst|$dst, $src}",
1085 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
1086
1087// Alias bitwise logical operations using SSE logical ops on packed FP values.
1088let isTwoAddress = 1 in {
1089let isCommutable = 1 in {
1090 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
1091 "andpd {$src2, $dst|$dst, $src2}",
1092 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1093 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
1094 "orpd {$src2, $dst|$dst, $src2}",
1095 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1096 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
1097 "xorpd {$src2, $dst|$dst, $src2}",
1098 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1099}
1100
1101def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
1102 "andpd {$src2, $dst|$dst, $src2}",
1103 [(set FR64:$dst, (X86fand FR64:$src1,
1104 (X86loadpf64 addr:$src2)))]>;
1105def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
1106 "orpd {$src2, $dst|$dst, $src2}",
1107 [(set FR64:$dst, (X86for FR64:$src1,
1108 (X86loadpf64 addr:$src2)))]>;
1109def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
1110 "xorpd {$src2, $dst|$dst, $src2}",
1111 [(set FR64:$dst, (X86fxor FR64:$src1,
1112 (X86loadpf64 addr:$src2)))]>;
1113
1114def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1115 (ops FR64:$dst, FR64:$src1, FR64:$src2),
1116 "andnpd {$src2, $dst|$dst, $src2}", []>;
1117def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1118 (ops FR64:$dst, FR64:$src1, f128mem:$src2),
1119 "andnpd {$src2, $dst|$dst, $src2}", []>;
1120}
1121
1122/// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1123///
1124/// In addition, we also have a special variant of the scalar form here to
1125/// represent the associated intrinsic operation. This form is unlike the
1126/// plain scalar form, in that it takes an entire vector (instead of a scalar)
1127/// and leaves the top elements undefined.
1128///
1129/// These three forms can each be reg+reg or reg+mem, so there are a total of
1130/// six "instructions".
1131///
1132let isTwoAddress = 1 in {
1133multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1134 SDNode OpNode, Intrinsic F64Int,
1135 bit Commutable = 0> {
1136 // Scalar operation, reg+reg.
1137 def SDrr : SDI<opc, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
1138 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1139 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1140 let isCommutable = Commutable;
1141 }
1142
1143 // Scalar operation, reg+mem.
1144 def SDrm : SDI<opc, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
1145 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1146 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1147
1148 // Vector operation, reg+reg.
1149 def PDrr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1150 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
1151 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1152 let isCommutable = Commutable;
1153 }
1154
1155 // Vector operation, reg+mem.
1156 def PDrm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1157 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1158 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1159
1160 // Intrinsic operation, reg+reg.
1161 def SDrr_Int : SDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1162 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1163 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1164 let isCommutable = Commutable;
1165 }
1166
1167 // Intrinsic operation, reg+mem.
1168 def SDrm_Int : SDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, sdmem:$src2),
1169 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1170 [(set VR128:$dst, (F64Int VR128:$src1,
1171 sse_load_f64:$src2))]>;
1172}
1173}
1174
1175// Arithmetic instructions
1176defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1177defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1178defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1179defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1180
1181/// sse2_fp_binop_rm - Other SSE2 binops
1182///
1183/// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1184/// instructions for a full-vector intrinsic form. Operations that map
1185/// onto C operators don't use this form since they just use the plain
1186/// vector form instead of having a separate vector intrinsic form.
1187///
1188/// This provides a total of eight "instructions".
1189///
1190let isTwoAddress = 1 in {
1191multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1192 SDNode OpNode,
1193 Intrinsic F64Int,
1194 Intrinsic V2F64Int,
1195 bit Commutable = 0> {
1196
1197 // Scalar operation, reg+reg.
1198 def SDrr : SDI<opc, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
1199 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1200 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1201 let isCommutable = Commutable;
1202 }
1203
1204 // Scalar operation, reg+mem.
1205 def SDrm : SDI<opc, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
1206 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1207 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1208
1209 // Vector operation, reg+reg.
1210 def PDrr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1211 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
1212 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1213 let isCommutable = Commutable;
1214 }
1215
1216 // Vector operation, reg+mem.
1217 def PDrm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1218 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1219 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1220
1221 // Intrinsic operation, reg+reg.
1222 def SDrr_Int : SDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1223 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1224 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1225 let isCommutable = Commutable;
1226 }
1227
1228 // Intrinsic operation, reg+mem.
1229 def SDrm_Int : SDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, sdmem:$src2),
1230 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1231 [(set VR128:$dst, (F64Int VR128:$src1,
1232 sse_load_f64:$src2))]>;
1233
1234 // Vector intrinsic operation, reg+reg.
1235 def PDrr_Int : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1236 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
1237 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1238 let isCommutable = Commutable;
1239 }
1240
1241 // Vector intrinsic operation, reg+mem.
1242 def PDrm_Int : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
1243 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
1244 [(set VR128:$dst, (V2F64Int VR128:$src1, (load addr:$src2)))]>;
1245}
1246}
1247
1248defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1249 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1250defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1251 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1252
1253//===----------------------------------------------------------------------===//
1254// SSE packed FP Instructions
1255
1256// Move Instructions
1257def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1258 "movapd {$src, $dst|$dst, $src}", []>;
1259def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1260 "movapd {$src, $dst|$dst, $src}",
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1261 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1262
1263def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1264 "movapd {$src, $dst|$dst, $src}",
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1265 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1266
1267def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1268 "movupd {$src, $dst|$dst, $src}", []>;
1269def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1270 "movupd {$src, $dst|$dst, $src}",
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1271 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1272def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1273 "movupd {$src, $dst|$dst, $src}",
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1274 [(store (v2f64 VR128:$src), addr:$dst)]>;
1275
1276// Intrinsic forms of MOVUPD load and store
1277def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1278 "movupd {$src, $dst|$dst, $src}",
1279 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1280def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1281 "movupd {$src, $dst|$dst, $src}",
1282 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1283
1284let isTwoAddress = 1 in {
1285 let AddedComplexity = 20 in {
1286 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1287 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
1288 "movlpd {$src2, $dst|$dst, $src2}",
1289 [(set VR128:$dst,
1290 (v2f64 (vector_shuffle VR128:$src1,
1291 (scalar_to_vector (loadf64 addr:$src2)),
1292 MOVLP_shuffle_mask)))]>;
1293 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1294 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
1295 "movhpd {$src2, $dst|$dst, $src2}",
1296 [(set VR128:$dst,
1297 (v2f64 (vector_shuffle VR128:$src1,
1298 (scalar_to_vector (loadf64 addr:$src2)),
1299 MOVHP_shuffle_mask)))]>;
1300 } // AddedComplexity
1301} // isTwoAddress
1302
1303def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
1304 "movlpd {$src, $dst|$dst, $src}",
1305 [(store (f64 (vector_extract (v2f64 VR128:$src),
1306 (iPTR 0))), addr:$dst)]>;
1307
1308// v2f64 extract element 1 is always custom lowered to unpack high to low
1309// and extract element 0 so the non-store version isn't too horrible.
1310def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
1311 "movhpd {$src, $dst|$dst, $src}",
1312 [(store (f64 (vector_extract
1313 (v2f64 (vector_shuffle VR128:$src, (undef),
1314 UNPCKH_shuffle_mask)), (iPTR 0))),
1315 addr:$dst)]>;
1316
1317// SSE2 instructions without OpSize prefix
1318def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1319 "cvtdq2ps {$src, $dst|$dst, $src}",
1320 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1321 TB, Requires<[HasSSE2]>;
1322def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1323 "cvtdq2ps {$src, $dst|$dst, $src}",
1324 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1325 (bitconvert (memopv2i64 addr:$src))))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1326 TB, Requires<[HasSSE2]>;
1327
1328// SSE2 instructions with XS prefix
1329def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1330 "cvtdq2pd {$src, $dst|$dst, $src}",
1331 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1332 XS, Requires<[HasSSE2]>;
1333def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1334 "cvtdq2pd {$src, $dst|$dst, $src}",
1335 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1336 (bitconvert (memopv2i64 addr:$src))))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1337 XS, Requires<[HasSSE2]>;
1338
1339def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1340 "cvtps2dq {$src, $dst|$dst, $src}",
1341 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1342def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1343 "cvtps2dq {$src, $dst|$dst, $src}",
1344 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1345 (load addr:$src)))]>;
1346// SSE2 packed instructions with XS prefix
1347def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1348 "cvttps2dq {$src, $dst|$dst, $src}",
1349 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1350 XS, Requires<[HasSSE2]>;
1351def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1352 "cvttps2dq {$src, $dst|$dst, $src}",
1353 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1354 (load addr:$src)))]>,
1355 XS, Requires<[HasSSE2]>;
1356
1357// SSE2 packed instructions with XD prefix
1358def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1359 "cvtpd2dq {$src, $dst|$dst, $src}",
1360 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1361 XD, Requires<[HasSSE2]>;
1362def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1363 "cvtpd2dq {$src, $dst|$dst, $src}",
1364 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1365 (load addr:$src)))]>,
1366 XD, Requires<[HasSSE2]>;
1367
1368def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1369 "cvttpd2dq {$src, $dst|$dst, $src}",
1370 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1371def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1372 "cvttpd2dq {$src, $dst|$dst, $src}",
1373 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1374 (load addr:$src)))]>;
1375
1376// SSE2 instructions without OpSize prefix
1377def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1378 "cvtps2pd {$src, $dst|$dst, $src}",
1379 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1380 TB, Requires<[HasSSE2]>;
1381def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
1382 "cvtps2pd {$src, $dst|$dst, $src}",
1383 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1384 (load addr:$src)))]>,
1385 TB, Requires<[HasSSE2]>;
1386
1387def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1388 "cvtpd2ps {$src, $dst|$dst, $src}",
1389 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1390def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
1391 "cvtpd2ps {$src, $dst|$dst, $src}",
1392 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1393 (load addr:$src)))]>;
1394
1395// Match intrinsics which expect XMM operand(s).
1396// Aliases for intrinsics
1397let isTwoAddress = 1 in {
1398def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1399 (ops VR128:$dst, VR128:$src1, GR32:$src2),
1400 "cvtsi2sd {$src2, $dst|$dst, $src2}",
1401 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1402 GR32:$src2))]>;
1403def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1404 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
1405 "cvtsi2sd {$src2, $dst|$dst, $src2}",
1406 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1407 (loadi32 addr:$src2)))]>;
1408def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1409 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1410 "cvtsd2ss {$src2, $dst|$dst, $src2}",
1411 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1412 VR128:$src2))]>;
1413def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1414 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
1415 "cvtsd2ss {$src2, $dst|$dst, $src2}",
1416 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1417 (load addr:$src2)))]>;
1418def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1419 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1420 "cvtss2sd {$src2, $dst|$dst, $src2}",
1421 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1422 VR128:$src2))]>, XS,
1423 Requires<[HasSSE2]>;
1424def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1425 (ops VR128:$dst, VR128:$src1, f32mem:$src2),
1426 "cvtss2sd {$src2, $dst|$dst, $src2}",
1427 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1428 (load addr:$src2)))]>, XS,
1429 Requires<[HasSSE2]>;
1430}
1431
1432// Arithmetic
1433
1434/// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1435///
1436/// In addition, we also have a special variant of the scalar form here to
1437/// represent the associated intrinsic operation. This form is unlike the
1438/// plain scalar form, in that it takes an entire vector (instead of a
1439/// scalar) and leaves the top elements undefined.
1440///
1441/// And, we have a special variant form for a full-vector intrinsic form.
1442///
1443/// These four forms can each have a reg or a mem operand, so there are a
1444/// total of eight "instructions".
1445///
1446multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1447 SDNode OpNode,
1448 Intrinsic F64Int,
1449 Intrinsic V2F64Int,
1450 bit Commutable = 0> {
1451 // Scalar operation, reg.
1452 def SDr : SDI<opc, MRMSrcReg, (ops FR64:$dst, FR64:$src),
1453 !strconcat(OpcodeStr, "sd {$src, $dst|$dst, $src}"),
1454 [(set FR64:$dst, (OpNode FR64:$src))]> {
1455 let isCommutable = Commutable;
1456 }
1457
1458 // Scalar operation, mem.
1459 def SDm : SDI<opc, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
1460 !strconcat(OpcodeStr, "sd {$src, $dst|$dst, $src}"),
1461 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1462
1463 // Vector operation, reg.
1464 def PDr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1465 !strconcat(OpcodeStr, "pd {$src, $dst|$dst, $src}"),
1466 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1467 let isCommutable = Commutable;
1468 }
1469
1470 // Vector operation, mem.
1471 def PDm : PDI<opc, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1472 !strconcat(OpcodeStr, "pd {$src, $dst|$dst, $src}"),
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1473 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1474
1475 // Intrinsic operation, reg.
1476 def SDr_Int : SDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1477 !strconcat(OpcodeStr, "sd {$src, $dst|$dst, $src}"),
1478 [(set VR128:$dst, (F64Int VR128:$src))]> {
1479 let isCommutable = Commutable;
1480 }
1481
1482 // Intrinsic operation, mem.
1483 def SDm_Int : SDI<opc, MRMSrcMem, (ops VR128:$dst, sdmem:$src),
1484 !strconcat(OpcodeStr, "sd {$src, $dst|$dst, $src}"),
1485 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1486
1487 // Vector intrinsic operation, reg
1488 def PDr_Int : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1489 !strconcat(OpcodeStr, "pd {$src, $dst|$dst, $src}"),
1490 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1491 let isCommutable = Commutable;
1492 }
1493
1494 // Vector intrinsic operation, mem
1495 def PDm_Int : PDI<opc, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1496 !strconcat(OpcodeStr, "pd {$src, $dst|$dst, $src}"),
1497 [(set VR128:$dst, (V2F64Int (load addr:$src)))]>;
1498}
1499
1500// Square root.
1501defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1502 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1503
1504// There is no f64 version of the reciprocal approximation instructions.
1505
1506// Logical
1507let isTwoAddress = 1 in {
1508 let isCommutable = 1 in {
1509 def ANDPDrr : PDI<0x54, MRMSrcReg,
1510 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1511 "andpd {$src2, $dst|$dst, $src2}",
1512 [(set VR128:$dst,
1513 (and (bc_v2i64 (v2f64 VR128:$src1)),
1514 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1515 def ORPDrr : PDI<0x56, MRMSrcReg,
1516 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1517 "orpd {$src2, $dst|$dst, $src2}",
1518 [(set VR128:$dst,
1519 (or (bc_v2i64 (v2f64 VR128:$src1)),
1520 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1521 def XORPDrr : PDI<0x57, MRMSrcReg,
1522 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1523 "xorpd {$src2, $dst|$dst, $src2}",
1524 [(set VR128:$dst,
1525 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1526 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1527 }
1528
1529 def ANDPDrm : PDI<0x54, MRMSrcMem,
1530 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1531 "andpd {$src2, $dst|$dst, $src2}",
1532 [(set VR128:$dst,
1533 (and (bc_v2i64 (v2f64 VR128:$src1)),
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1534 (bc_v2i64 (memopv2f64 addr:$src2))))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1535 def ORPDrm : PDI<0x56, MRMSrcMem,
1536 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1537 "orpd {$src2, $dst|$dst, $src2}",
1538 [(set VR128:$dst,
1539 (or (bc_v2i64 (v2f64 VR128:$src1)),
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1540 (bc_v2i64 (memopv2f64 addr:$src2))))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1541 def XORPDrm : PDI<0x57, MRMSrcMem,
1542 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1543 "xorpd {$src2, $dst|$dst, $src2}",
1544 [(set VR128:$dst,
1545 (xor (bc_v2i64 (v2f64 VR128:$src1)),
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1546 (bc_v2i64 (memopv2f64 addr:$src2))))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1547 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1548 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1549 "andnpd {$src2, $dst|$dst, $src2}",
1550 [(set VR128:$dst,
1551 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1552 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1553 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1554 (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1555 "andnpd {$src2, $dst|$dst, $src2}",
1556 [(set VR128:$dst,
1557 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1558 (bc_v2i64 (memopv2f64 addr:$src2))))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1559}
1560
1561let isTwoAddress = 1 in {
1562 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1563 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1564 "cmp${cc}pd {$src, $dst|$dst, $src}",
1565 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1566 VR128:$src, imm:$cc))]>;
1567 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1568 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1569 "cmp${cc}pd {$src, $dst|$dst, $src}",
1570 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1571 (load addr:$src), imm:$cc))]>;
1572}
1573
1574// Shuffle and unpack instructions
1575let isTwoAddress = 1 in {
1576 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1577 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1578 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1579 [(set VR128:$dst, (v2f64 (vector_shuffle
1580 VR128:$src1, VR128:$src2,
1581 SHUFP_shuffle_mask:$src3)))]>;
1582 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1583 (ops VR128:$dst, VR128:$src1,
1584 f128mem:$src2, i8imm:$src3),
1585 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1586 [(set VR128:$dst,
1587 (v2f64 (vector_shuffle
1588 VR128:$src1, (load addr:$src2),
1589 SHUFP_shuffle_mask:$src3)))]>;
1590
1591 let AddedComplexity = 10 in {
1592 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1593 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1594 "unpckhpd {$src2, $dst|$dst, $src2}",
1595 [(set VR128:$dst,
1596 (v2f64 (vector_shuffle
1597 VR128:$src1, VR128:$src2,
1598 UNPCKH_shuffle_mask)))]>;
1599 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1600 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1601 "unpckhpd {$src2, $dst|$dst, $src2}",
1602 [(set VR128:$dst,
1603 (v2f64 (vector_shuffle
1604 VR128:$src1, (load addr:$src2),
1605 UNPCKH_shuffle_mask)))]>;
1606
1607 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1608 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1609 "unpcklpd {$src2, $dst|$dst, $src2}",
1610 [(set VR128:$dst,
1611 (v2f64 (vector_shuffle
1612 VR128:$src1, VR128:$src2,
1613 UNPCKL_shuffle_mask)))]>;
1614 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1615 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1616 "unpcklpd {$src2, $dst|$dst, $src2}",
1617 [(set VR128:$dst,
1618 (v2f64 (vector_shuffle
1619 VR128:$src1, (load addr:$src2),
1620 UNPCKL_shuffle_mask)))]>;
1621 } // AddedComplexity
1622} // isTwoAddress
1623
1624
1625//===----------------------------------------------------------------------===//
1626// SSE integer instructions
1627
1628// Move Instructions
1629def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1630 "movdqa {$src, $dst|$dst, $src}", []>;
1631def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1632 "movdqa {$src, $dst|$dst, $src}",
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1633 [(set VR128:$dst, (alignedloadv2i64 addr:$src))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1634def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1635 "movdqa {$src, $dst|$dst, $src}",
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1636 [(alignedstore (v2i64 VR128:$src), addr:$dst)]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1637def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1638 "movdqu {$src, $dst|$dst, $src}",
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1639 [(set VR128:$dst, (loadv2i64 addr:$src))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1640 XS, Requires<[HasSSE2]>;
1641def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1642 "movdqu {$src, $dst|$dst, $src}",
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1643 [(store (v2i64 VR128:$src), addr:$dst)]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1644 XS, Requires<[HasSSE2]>;
1645
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1646// Intrinsic forms of MOVDQU load and store
1647def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1648 "movdqu {$src, $dst|$dst, $src}",
1649 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1650 XS, Requires<[HasSSE2]>;
1651def MOVDQUmr_Int : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1652 "movdqu {$src, $dst|$dst, $src}",
1653 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1654 XS, Requires<[HasSSE2]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1655
1656let isTwoAddress = 1 in {
1657
1658multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1659 bit Commutable = 0> {
1660 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1661 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1662 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1663 let isCommutable = Commutable;
1664 }
1665 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1666 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1667 [(set VR128:$dst, (IntId VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1668 (bitconvert (memopv2i64 addr:$src2))))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1669}
1670
1671multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1672 string OpcodeStr, Intrinsic IntId> {
1673 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1674 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1675 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1676 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1677 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1678 [(set VR128:$dst, (IntId VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1679 (bitconvert (memopv2i64 addr:$src2))))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1680 def ri : PDIi8<opc2, ImmForm, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1681 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1682 [(set VR128:$dst, (IntId VR128:$src1,
1683 (scalar_to_vector (i32 imm:$src2))))]>;
1684}
1685
1686
1687/// PDI_binop_rm - Simple SSE2 binary operator.
1688multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1689 ValueType OpVT, bit Commutable = 0> {
1690 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1691 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1692 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1693 let isCommutable = Commutable;
1694 }
1695 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1696 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1697 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1698 (bitconvert (memopv2i64 addr:$src2)))))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1699}
1700
1701/// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1702///
1703/// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1704/// to collapse (bitconvert VT to VT) into its operand.
1705///
1706multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1707 bit Commutable = 0> {
1708 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1709 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1710 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1711 let isCommutable = Commutable;
1712 }
1713 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1714 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1715 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1716}
1717
1718} // isTwoAddress
1719
1720// 128-bit Integer Arithmetic
1721
1722defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1723defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1724defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1725defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1726
1727defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1728defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1729defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1730defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1731
1732defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1733defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1734defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1735defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1736
1737defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1738defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1739defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1740defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1741
1742defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1743
1744defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1745defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1746defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1747
1748defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1749
1750defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1751defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1752
1753
1754defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1755defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1756defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1757defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1758defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1759
1760
1761defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", int_x86_sse2_psll_w>;
1762defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", int_x86_sse2_psll_d>;
1763defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", int_x86_sse2_psll_q>;
1764
1765defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", int_x86_sse2_psrl_w>;
1766defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", int_x86_sse2_psrl_d>;
1767defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", int_x86_sse2_psrl_q>;
1768
1769defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", int_x86_sse2_psra_w>;
1770defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", int_x86_sse2_psra_d>;
1771// PSRAQ doesn't exist in SSE[1-3].
1772
1773// 128-bit logical shifts.
1774let isTwoAddress = 1 in {
1775 def PSLLDQri : PDIi8<0x73, MRM7r,
1776 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1777 "pslldq {$src2, $dst|$dst, $src2}", []>;
1778 def PSRLDQri : PDIi8<0x73, MRM3r,
1779 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1780 "psrldq {$src2, $dst|$dst, $src2}", []>;
1781 // PSRADQri doesn't exist in SSE[1-3].
1782}
1783
1784let Predicates = [HasSSE2] in {
1785 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1786 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1787 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1788 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1789 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1790 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1791}
1792
1793// Logical
1794defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1795defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1796defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1797
1798let isTwoAddress = 1 in {
1799 def PANDNrr : PDI<0xDF, MRMSrcReg,
1800 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1801 "pandn {$src2, $dst|$dst, $src2}",
1802 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1803 VR128:$src2)))]>;
1804
1805 def PANDNrm : PDI<0xDF, MRMSrcMem,
1806 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1807 "pandn {$src2, $dst|$dst, $src2}",
1808 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1809 (load addr:$src2))))]>;
1810}
1811
1812// SSE2 Integer comparison
1813defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1814defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1815defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1816defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1817defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1818defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1819
1820// Pack instructions
1821defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
1822defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
1823defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
1824
1825// Shuffle and unpack instructions
1826def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1827 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1828 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1829 [(set VR128:$dst, (v4i32 (vector_shuffle
1830 VR128:$src1, (undef),
1831 PSHUFD_shuffle_mask:$src2)))]>;
1832def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1833 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1834 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1835 [(set VR128:$dst, (v4i32 (vector_shuffle
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1836 (bc_v4i32(memopv2i64 addr:$src1)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1837 (undef),
1838 PSHUFD_shuffle_mask:$src2)))]>;
1839
1840// SSE2 with ImmT == Imm8 and XS prefix.
1841def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1842 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1843 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1844 [(set VR128:$dst, (v8i16 (vector_shuffle
1845 VR128:$src1, (undef),
1846 PSHUFHW_shuffle_mask:$src2)))]>,
1847 XS, Requires<[HasSSE2]>;
1848def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1849 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1850 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1851 [(set VR128:$dst, (v8i16 (vector_shuffle
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1852 (bc_v8i16 (memopv2i64 addr:$src1)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1853 (undef),
1854 PSHUFHW_shuffle_mask:$src2)))]>,
1855 XS, Requires<[HasSSE2]>;
1856
1857// SSE2 with ImmT == Imm8 and XD prefix.
1858def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1859 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1860 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1861 [(set VR128:$dst, (v8i16 (vector_shuffle
1862 VR128:$src1, (undef),
1863 PSHUFLW_shuffle_mask:$src2)))]>,
1864 XD, Requires<[HasSSE2]>;
1865def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1866 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1867 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1868 [(set VR128:$dst, (v8i16 (vector_shuffle
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1869 (bc_v8i16 (memopv2i64 addr:$src1)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1870 (undef),
1871 PSHUFLW_shuffle_mask:$src2)))]>,
1872 XD, Requires<[HasSSE2]>;
1873
1874
1875let isTwoAddress = 1 in {
1876 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1877 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1878 "punpcklbw {$src2, $dst|$dst, $src2}",
1879 [(set VR128:$dst,
1880 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1881 UNPCKL_shuffle_mask)))]>;
1882 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1883 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1884 "punpcklbw {$src2, $dst|$dst, $src2}",
1885 [(set VR128:$dst,
1886 (v16i8 (vector_shuffle VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1887 (bc_v16i8 (memopv2i64 addr:$src2)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1888 UNPCKL_shuffle_mask)))]>;
1889 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1890 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1891 "punpcklwd {$src2, $dst|$dst, $src2}",
1892 [(set VR128:$dst,
1893 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1894 UNPCKL_shuffle_mask)))]>;
1895 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1896 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1897 "punpcklwd {$src2, $dst|$dst, $src2}",
1898 [(set VR128:$dst,
1899 (v8i16 (vector_shuffle VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1900 (bc_v8i16 (memopv2i64 addr:$src2)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1901 UNPCKL_shuffle_mask)))]>;
1902 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1903 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1904 "punpckldq {$src2, $dst|$dst, $src2}",
1905 [(set VR128:$dst,
1906 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1907 UNPCKL_shuffle_mask)))]>;
1908 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1909 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1910 "punpckldq {$src2, $dst|$dst, $src2}",
1911 [(set VR128:$dst,
1912 (v4i32 (vector_shuffle VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1913 (bc_v4i32 (memopv2i64 addr:$src2)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1914 UNPCKL_shuffle_mask)))]>;
1915 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1916 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1917 "punpcklqdq {$src2, $dst|$dst, $src2}",
1918 [(set VR128:$dst,
1919 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1920 UNPCKL_shuffle_mask)))]>;
1921 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1922 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1923 "punpcklqdq {$src2, $dst|$dst, $src2}",
1924 [(set VR128:$dst,
1925 (v2i64 (vector_shuffle VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1926 (memopv2i64 addr:$src2),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1927 UNPCKL_shuffle_mask)))]>;
1928
1929 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1930 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1931 "punpckhbw {$src2, $dst|$dst, $src2}",
1932 [(set VR128:$dst,
1933 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1934 UNPCKH_shuffle_mask)))]>;
1935 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1936 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1937 "punpckhbw {$src2, $dst|$dst, $src2}",
1938 [(set VR128:$dst,
1939 (v16i8 (vector_shuffle VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1940 (bc_v16i8 (memopv2i64 addr:$src2)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1941 UNPCKH_shuffle_mask)))]>;
1942 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1943 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1944 "punpckhwd {$src2, $dst|$dst, $src2}",
1945 [(set VR128:$dst,
1946 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1947 UNPCKH_shuffle_mask)))]>;
1948 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1949 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1950 "punpckhwd {$src2, $dst|$dst, $src2}",
1951 [(set VR128:$dst,
1952 (v8i16 (vector_shuffle VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1953 (bc_v8i16 (memopv2i64 addr:$src2)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1954 UNPCKH_shuffle_mask)))]>;
1955 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1956 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1957 "punpckhdq {$src2, $dst|$dst, $src2}",
1958 [(set VR128:$dst,
1959 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1960 UNPCKH_shuffle_mask)))]>;
1961 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1962 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1963 "punpckhdq {$src2, $dst|$dst, $src2}",
1964 [(set VR128:$dst,
1965 (v4i32 (vector_shuffle VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1966 (bc_v4i32 (memopv2i64 addr:$src2)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1967 UNPCKH_shuffle_mask)))]>;
1968 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1969 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1970 "punpckhqdq {$src2, $dst|$dst, $src2}",
1971 [(set VR128:$dst,
1972 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1973 UNPCKH_shuffle_mask)))]>;
1974 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1975 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1976 "punpckhqdq {$src2, $dst|$dst, $src2}",
1977 [(set VR128:$dst,
1978 (v2i64 (vector_shuffle VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]1979 (memopv2i64 addr:$src2),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1980 UNPCKH_shuffle_mask)))]>;
1981}
1982
1983// Extract / Insert
1984def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
1985 (ops GR32:$dst, VR128:$src1, i32i8imm:$src2),
1986 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
1987 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
1988 (iPTR imm:$src2)))]>;
1989let isTwoAddress = 1 in {
1990 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
1991 (ops VR128:$dst, VR128:$src1,
1992 GR32:$src2, i32i8imm:$src3),
1993 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1994 [(set VR128:$dst,
1995 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1996 GR32:$src2, (iPTR imm:$src3))))]>;
1997 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
1998 (ops VR128:$dst, VR128:$src1,
1999 i16mem:$src2, i32i8imm:$src3),
2000 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
2001 [(set VR128:$dst,
2002 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2003 (i32 (anyext (loadi16 addr:$src2))),
2004 (iPTR imm:$src3))))]>;
2005}
2006
2007// Mask creation
2008def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops GR32:$dst, VR128:$src),
2009 "pmovmskb {$src, $dst|$dst, $src}",
2010 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2011
2012// Conditional store
2013def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (ops VR128:$src, VR128:$mask),
2014 "maskmovdqu {$mask, $src|$src, $mask}",
2015 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
2016 Imp<[EDI],[]>;
2017
2018// Non-temporal stores
2019def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
2020 "movntpd {$src, $dst|$dst, $src}",
2021 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2022def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
2023 "movntdq {$src, $dst|$dst, $src}",
2024 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2025def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, GR32:$src),
2026 "movnti {$src, $dst|$dst, $src}",
2027 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2028 TB, Requires<[HasSSE2]>;
2029
2030// Flush cache
2031def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src),
2032 "clflush $src", [(int_x86_sse2_clflush addr:$src)]>,
2033 TB, Requires<[HasSSE2]>;
2034
2035// Load, store, and memory fence
2036def LFENCE : I<0xAE, MRM5m, (ops),
2037 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2038def MFENCE : I<0xAE, MRM6m, (ops),
2039 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2040
2041
2042// Alias instructions that map zero vector to pxor / xorp* for sse.
2043// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2044let isReMaterializable = 1 in
2045 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
2046 "pcmpeqd $dst, $dst",
2047 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
2048
2049// FR64 to 128-bit vector conversion.
2050def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
2051 "movsd {$src, $dst|$dst, $src}",
2052 [(set VR128:$dst,
2053 (v2f64 (scalar_to_vector FR64:$src)))]>;
2054def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2055 "movsd {$src, $dst|$dst, $src}",
2056 [(set VR128:$dst,
2057 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2058
2059def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
2060 "movd {$src, $dst|$dst, $src}",
2061 [(set VR128:$dst,
2062 (v4i32 (scalar_to_vector GR32:$src)))]>;
2063def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2064 "movd {$src, $dst|$dst, $src}",
2065 [(set VR128:$dst,
2066 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2067
2068def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (ops FR32:$dst, GR32:$src),
2069 "movd {$src, $dst|$dst, $src}",
2070 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2071
2072def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
2073 "movd {$src, $dst|$dst, $src}",
2074 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2075
2076// SSE2 instructions with XS prefix
2077def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2078 "movq {$src, $dst|$dst, $src}",
2079 [(set VR128:$dst,
2080 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2081 Requires<[HasSSE2]>;
2082def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
2083 "movq {$src, $dst|$dst, $src}",
2084 [(store (i64 (vector_extract (v2i64 VR128:$src),
2085 (iPTR 0))), addr:$dst)]>;
2086
2087// FIXME: may not be able to eliminate this movss with coalescing the src and
2088// dest register classes are different. We really want to write this pattern
2089// like this:
2090// def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2091// (f32 FR32:$src)>;
2092def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
2093 "movsd {$src, $dst|$dst, $src}",
2094 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2095 (iPTR 0)))]>;
2096def MOVPD2SDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, VR128:$src),
2097 "movsd {$src, $dst|$dst, $src}",
2098 [(store (f64 (vector_extract (v2f64 VR128:$src),
2099 (iPTR 0))), addr:$dst)]>;
2100def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, VR128:$src),
2101 "movd {$src, $dst|$dst, $src}",
2102 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2103 (iPTR 0)))]>;
2104def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
2105 "movd {$src, $dst|$dst, $src}",
2106 [(store (i32 (vector_extract (v4i32 VR128:$src),
2107 (iPTR 0))), addr:$dst)]>;
2108
2109def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, FR32:$src),
2110 "movd {$src, $dst|$dst, $src}",
2111 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2112def MOVSS2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, FR32:$src),
2113 "movd {$src, $dst|$dst, $src}",
2114 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2115
2116
2117// Move to lower bits of a VR128, leaving upper bits alone.
2118// Three operand (but two address) aliases.
2119let isTwoAddress = 1 in {
2120 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2121 (ops VR128:$dst, VR128:$src1, FR64:$src2),
2122 "movsd {$src2, $dst|$dst, $src2}", []>;
2123
2124 let AddedComplexity = 15 in
2125 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2126 (ops VR128:$dst, VR128:$src1, VR128:$src2),
2127 "movsd {$src2, $dst|$dst, $src2}",
2128 [(set VR128:$dst,
2129 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2130 MOVL_shuffle_mask)))]>;
2131}
2132
2133// Store / copy lower 64-bits of a XMM register.
2134def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
2135 "movq {$src, $dst|$dst, $src}",
2136 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2137
2138// Move to lower bits of a VR128 and zeroing upper bits.
2139// Loading from memory automatically zeroing upper bits.
2140let AddedComplexity = 20 in
2141 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2142 "movsd {$src, $dst|$dst, $src}",
2143 [(set VR128:$dst,
2144 (v2f64 (vector_shuffle immAllZerosV,
2145 (v2f64 (scalar_to_vector
2146 (loadf64 addr:$src))),
2147 MOVL_shuffle_mask)))]>;
2148
2149let AddedComplexity = 15 in
2150// movd / movq to XMM register zero-extends
2151def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
2152 "movd {$src, $dst|$dst, $src}",
2153 [(set VR128:$dst,
2154 (v4i32 (vector_shuffle immAllZerosV,
2155 (v4i32 (scalar_to_vector GR32:$src)),
2156 MOVL_shuffle_mask)))]>;
2157let AddedComplexity = 20 in
2158def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2159 "movd {$src, $dst|$dst, $src}",
2160 [(set VR128:$dst,
2161 (v4i32 (vector_shuffle immAllZerosV,
2162 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
2163 MOVL_shuffle_mask)))]>;
2164
2165// Moving from XMM to XMM but still clear upper 64 bits.
2166let AddedComplexity = 15 in
2167def MOVZQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR128:$src),
2168 "movq {$src, $dst|$dst, $src}",
2169 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>,
2170 XS, Requires<[HasSSE2]>;
2171let AddedComplexity = 20 in
2172def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2173 "movq {$src, $dst|$dst, $src}",
2174 [(set VR128:$dst, (int_x86_sse2_movl_dq
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2175 (bitconvert (memopv2i64 addr:$src))))]>,
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2176 XS, Requires<[HasSSE2]>;
2177
2178
2179//===----------------------------------------------------------------------===//
2180// SSE3 Instructions
2181//===----------------------------------------------------------------------===//
2182
2183// SSE3 Instruction Templates:
2184//
2185// S3I - SSE3 instructions with TB and OpSize prefixes.
2186// S3SI - SSE3 instructions with XS prefix.
2187// S3DI - SSE3 instructions with XD prefix.
2188
2189class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
2190 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>;
2191class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
2192 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
2193class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
2194 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
2195
2196// Move Instructions
2197def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
2198 "movshdup {$src, $dst|$dst, $src}",
2199 [(set VR128:$dst, (v4f32 (vector_shuffle
2200 VR128:$src, (undef),
2201 MOVSHDUP_shuffle_mask)))]>;
2202def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
2203 "movshdup {$src, $dst|$dst, $src}",
2204 [(set VR128:$dst, (v4f32 (vector_shuffle
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2205 (memopv4f32 addr:$src), (undef),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2206 MOVSHDUP_shuffle_mask)))]>;
2207
2208def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
2209 "movsldup {$src, $dst|$dst, $src}",
2210 [(set VR128:$dst, (v4f32 (vector_shuffle
2211 VR128:$src, (undef),
2212 MOVSLDUP_shuffle_mask)))]>;
2213def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
2214 "movsldup {$src, $dst|$dst, $src}",
2215 [(set VR128:$dst, (v4f32 (vector_shuffle
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2216 (memopv4f32 addr:$src), (undef),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2217 MOVSLDUP_shuffle_mask)))]>;
2218
2219def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
2220 "movddup {$src, $dst|$dst, $src}",
2221 [(set VR128:$dst, (v2f64 (vector_shuffle
2222 VR128:$src, (undef),
2223 SSE_splat_lo_mask)))]>;
2224def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2225 "movddup {$src, $dst|$dst, $src}",
2226 [(set VR128:$dst,
2227 (v2f64 (vector_shuffle
2228 (scalar_to_vector (loadf64 addr:$src)),
2229 (undef),
2230 SSE_splat_lo_mask)))]>;
2231
2232// Arithmetic
2233let isTwoAddress = 1 in {
2234 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2235 (ops VR128:$dst, VR128:$src1, VR128:$src2),
2236 "addsubps {$src2, $dst|$dst, $src2}",
2237 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2238 VR128:$src2))]>;
2239 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2240 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
2241 "addsubps {$src2, $dst|$dst, $src2}",
2242 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2243 (load addr:$src2)))]>;
2244 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2245 (ops VR128:$dst, VR128:$src1, VR128:$src2),
2246 "addsubpd {$src2, $dst|$dst, $src2}",
2247 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2248 VR128:$src2))]>;
2249 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2250 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
2251 "addsubpd {$src2, $dst|$dst, $src2}",
2252 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2253 (load addr:$src2)))]>;
2254}
2255
2256def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
2257 "lddqu {$src, $dst|$dst, $src}",
2258 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2259
2260// Horizontal ops
2261class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2262 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2263 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2264 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2265class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2266 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
2267 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2268 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
2269class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2270 : S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2271 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2272 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2273class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2274 : S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
2275 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2276 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
2277
2278let isTwoAddress = 1 in {
2279 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2280 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2281 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2282 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2283 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2284 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2285 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2286 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2287}
2288
2289// Thread synchronization
2290def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
2291 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2292def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
2293 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2294
2295// vector_shuffle v1, <undef> <1, 1, 3, 3>
2296let AddedComplexity = 15 in
2297def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2298 MOVSHDUP_shuffle_mask)),
2299 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2300let AddedComplexity = 20 in
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2301def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2302 MOVSHDUP_shuffle_mask)),
2303 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2304
2305// vector_shuffle v1, <undef> <0, 0, 2, 2>
2306let AddedComplexity = 15 in
2307 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2308 MOVSLDUP_shuffle_mask)),
2309 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2310let AddedComplexity = 20 in
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2311 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2312 MOVSLDUP_shuffle_mask)),
2313 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2314
2315//===----------------------------------------------------------------------===//
2316// SSSE3 Instructions
2317//===----------------------------------------------------------------------===//
2318
2319// SSE3 Instruction Templates:
2320//
2321// SS38I - SSSE3 instructions with T8 and OpSize prefixes.
2322// SS3AI - SSSE3 instructions with TA and OpSize prefixes.
2323
2324class SS38I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
2325 : I<o, F, ops, asm, pattern>, T8, OpSize, Requires<[HasSSSE3]>;
2326class SS3AI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
2327 : I<o, F, ops, asm, pattern>, TA, OpSize, Requires<[HasSSSE3]>;
2328
2329/// SS3I_binop_rm_int - Simple SSSE3 binary operatr whose type is v2i64.
2330let isTwoAddress = 1 in {
2331 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2332 bit Commutable = 0> {
2333 def rr : SS38I<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2334 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2335 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
2336 let isCommutable = Commutable;
2337 }
2338 def rm : SS38I<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
2339 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2340 [(set VR128:$dst,
2341 (IntId VR128:$src1,
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2342 (bitconvert (memopv2i64 addr:$src2))))]>;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2343 }
2344}
2345
2346defm PMULHRSW128 : SS3I_binop_rm_int<0x0B, "pmulhrsw",
2347 int_x86_ssse3_pmulhrsw_128, 1>;
2348
2349//===----------------------------------------------------------------------===//
2350// Non-Instruction Patterns
2351//===----------------------------------------------------------------------===//
2352
2353// 128-bit vector undef's.
2354def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2355def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2356def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2357def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2358def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2359
2360// 128-bit vector all zero's.
2361def : Pat<(v16i8 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2362def : Pat<(v8i16 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2363def : Pat<(v4i32 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2364def : Pat<(v2i64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2365def : Pat<(v2f64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2366
2367// 128-bit vector all one's.
2368def : Pat<(v16i8 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2369def : Pat<(v8i16 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2370def : Pat<(v4i32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2371def : Pat<(v2i64 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2372def : Pat<(v4f32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE1]>;
2373
2374// Store 128-bit integer vector values.
2375def : Pat<(store (v16i8 VR128:$src), addr:$dst),
2376 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2377def : Pat<(store (v8i16 VR128:$src), addr:$dst),
2378 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2379def : Pat<(store (v4i32 VR128:$src), addr:$dst),
2380 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2381
2382// Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or
2383// 16-bits matter.
2384def : Pat<(v8i16 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2385 Requires<[HasSSE2]>;
2386def : Pat<(v16i8 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2387 Requires<[HasSSE2]>;
2388
2389// bit_convert
2390let Predicates = [HasSSE2] in {
2391 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2392 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2393 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2394 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2395 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2396 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2397 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2398 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2399 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2400 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2401 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2402 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2403 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2404 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2405 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2406 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2407 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2408 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2409 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2410 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2411 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2412 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2413 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2414 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2415 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2416 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2417 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2418 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2419 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2420 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2421}
2422
2423// Move scalar to XMM zero-extended
2424// movd to XMM register zero-extends
2425let AddedComplexity = 15 in {
2426def : Pat<(v8i16 (vector_shuffle immAllZerosV,
2427 (v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
2428 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
2429def : Pat<(v16i8 (vector_shuffle immAllZerosV,
2430 (v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
2431 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
2432// Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2433def : Pat<(v2f64 (vector_shuffle immAllZerosV,
2434 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
2435 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2436def : Pat<(v4f32 (vector_shuffle immAllZerosV,
2437 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
2438 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2439}
2440
2441// Splat v2f64 / v2i64
2442let AddedComplexity = 10 in {
2443def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2444 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2445def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2446 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2447def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2448 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2449def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2450 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2451}
2452
2453// Splat v4f32
2454def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2455 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)>,
2456 Requires<[HasSSE1]>;
2457
2458// Special unary SHUFPSrri case.
2459// FIXME: when we want non two-address code, then we should use PSHUFD?
2460def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
2461 SHUFP_unary_shuffle_mask:$sm),
2462 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2463 Requires<[HasSSE1]>;
2464// Unary v4f32 shuffle with PSHUF* in order to fold a load.
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2465def : Pat<(vector_shuffle (memopv4f32 addr:$src1), (undef),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2466 SHUFP_unary_shuffle_mask:$sm),
2467 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2468 Requires<[HasSSE2]>;
2469// Special binary v4i32 shuffle cases with SHUFPS.
2470def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
2471 PSHUFD_binary_shuffle_mask:$sm),
2472 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2473 Requires<[HasSSE2]>;
2474def : Pat<(vector_shuffle (v4i32 VR128:$src1),
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2475 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2476 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2477 Requires<[HasSSE2]>;
2478
2479// vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2480let AddedComplexity = 10 in {
2481def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2482 UNPCKL_v_undef_shuffle_mask)),
2483 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2484def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2485 UNPCKL_v_undef_shuffle_mask)),
2486 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2487def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2488 UNPCKL_v_undef_shuffle_mask)),
2489 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2490def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2491 UNPCKL_v_undef_shuffle_mask)),
2492 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2493}
2494
2495// vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2496let AddedComplexity = 10 in {
2497def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2498 UNPCKH_v_undef_shuffle_mask)),
2499 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2500def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2501 UNPCKH_v_undef_shuffle_mask)),
2502 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2503def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2504 UNPCKH_v_undef_shuffle_mask)),
2505 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2506def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2507 UNPCKH_v_undef_shuffle_mask)),
2508 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2509}
2510
2511let AddedComplexity = 15 in {
2512// vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2513def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2514 MOVHP_shuffle_mask)),
2515 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2516
2517// vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2518def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2519 MOVHLPS_shuffle_mask)),
2520 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2521
2522// vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2523def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2524 MOVHLPS_v_undef_shuffle_mask)),
2525 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2526def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2527 MOVHLPS_v_undef_shuffle_mask)),
2528 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2529}
2530
2531let AddedComplexity = 20 in {
2532// vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2533// vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2534def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2535 MOVLP_shuffle_mask)),
2536 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2537def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2538 MOVLP_shuffle_mask)),
2539 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2540def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2541 MOVHP_shuffle_mask)),
2542 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2543def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2544 MOVHP_shuffle_mask)),
2545 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2546
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2547def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2548 MOVLP_shuffle_mask)),
2549 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2550def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2551 MOVLP_shuffle_mask)),
2552 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2553def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2554 MOVHP_shuffle_mask)),
2555 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
Dan Gohman4a4f1512007-07-18 20:23:34 +0000[diff] [blame^]2556def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]2557 MOVLP_shuffle_mask)),
2558 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2559}
2560
2561let AddedComplexity = 15 in {
2562// Setting the lowest element in the vector.
2563def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2564 MOVL_shuffle_mask)),
2565 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2566def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2567 MOVL_shuffle_mask)),
2568 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2569
2570// vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2571def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2572 MOVLP_shuffle_mask)),
2573 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2574def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2575 MOVLP_shuffle_mask)),
2576 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2577}
2578
2579// Set lowest element and zero upper elements.
2580let AddedComplexity = 20 in
2581def : Pat<(bc_v2i64 (vector_shuffle immAllZerosV,
2582 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
2583 MOVL_shuffle_mask)),
2584 (MOVZQI2PQIrm addr:$src)>, Requires<[HasSSE2]>;
2585
2586// FIXME: Temporary workaround since 2-wide shuffle is broken.
2587def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2588 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2589def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2590 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2591def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2592 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2593def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2594 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2595 Requires<[HasSSE2]>;
2596def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2597 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2598 Requires<[HasSSE2]>;
2599def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2600 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2601def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2602 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2603def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2604 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2605def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2606 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2607def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2608 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2609def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2610 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2611def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2612 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2613def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2614 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2615
2616// Some special case pandn patterns.
2617def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2618 VR128:$src2)),
2619 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2620def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2621 VR128:$src2)),
2622 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2623def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2624 VR128:$src2)),
2625 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2626
2627def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2628 (load addr:$src2))),
2629 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2630def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2631 (load addr:$src2))),
2632 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2633def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2634 (load addr:$src2))),
2635 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2636
2637// Unaligned load
2638def : Pat<(v4f32 (X86loadu addr:$src)), (MOVUPSrm addr:$src)>,
2639 Requires<[HasSSE1]>;